diff options
28 files changed, 15929 insertions, 2 deletions
diff --git a/src/usr/diag/prdf/common/framework/resolution/prdfCalloutMap.H b/src/usr/diag/prdf/common/framework/resolution/prdfCalloutMap.H index d6e5156bc..fc9a89a1d 100644 --- a/src/usr/diag/prdf/common/framework/resolution/prdfCalloutMap.H +++ b/src/usr/diag/prdf/common/framework/resolution/prdfCalloutMap.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2017 */ +/* Contributors Listed Below - COPYRIGHT 2012,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -179,6 +179,7 @@ PRDF_TARGET_TYPE_ALIAS( TYPE_EQ, TARGETING::TYPE_EQ ) PRDF_TARGET_TYPE_ALIAS( TYPE_EX, TARGETING::TYPE_EX ) PRDF_TARGET_TYPE_ALIAS( TYPE_CORE, TARGETING::TYPE_CORE ) PRDF_TARGET_TYPE_ALIAS( TYPE_CAPP, TARGETING::TYPE_CAPP ) +PRDF_TARGET_TYPE_ALIAS( TYPE_NPU, TARGETING::TYPE_NPU ) PRDF_TARGET_TYPE_ALIAS( TYPE_PEC, TARGETING::TYPE_PEC ) PRDF_TARGET_TYPE_ALIAS( TYPE_PHB, TARGETING::TYPE_PHB ) PRDF_TARGET_TYPE_ALIAS( TYPE_OBUS, TARGETING::TYPE_OBUS ) @@ -192,6 +193,8 @@ PRDF_TARGET_TYPE_ALIAS( TYPE_MCA, TARGETING::TYPE_MCA ) PRDF_TARGET_TYPE_ALIAS( TYPE_MC, TARGETING::TYPE_MC ) PRDF_TARGET_TYPE_ALIAS( TYPE_MI, TARGETING::TYPE_MI ) PRDF_TARGET_TYPE_ALIAS( TYPE_DMI, TARGETING::TYPE_DMI ) +PRDF_TARGET_TYPE_ALIAS( TYPE_MCC, TARGETING::TYPE_MCC ) +PRDF_TARGET_TYPE_ALIAS( TYPE_OMIC, TARGETING::TYPE_OMIC ) PRDF_TARGET_TYPE_ALIAS( TYPE_MEMBUF, TARGETING::TYPE_MEMBUF ) PRDF_TARGET_TYPE_ALIAS( TYPE_L4, TARGETING::TYPE_L4 ) PRDF_TARGET_TYPE_ALIAS( TYPE_MBA, TARGETING::TYPE_MBA ) diff --git a/src/usr/diag/prdf/common/plat/axone/axone_capp.rule b/src/usr/diag/prdf/common/plat/axone/axone_capp.rule new file mode 100644 index 000000000..1afbe83fb --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_capp.rule @@ -0,0 +1,415 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_capp.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_capp +{ + name "AXONE CAPP target"; + targettype TYPE_CAPP; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # P9 CAPP target CXAFIR + ############################################################################ + + register CXAFIR + { + name "P9 CAPP target CXAFIR"; + scomaddr 0x02010800; + reset (&, 0x02010801); + mask (|, 0x02010805); + capture group default; + }; + + register CXAFIR_MASK + { + name "P9 CAPP target CXAFIR MASK"; + scomaddr 0x02010803; + capture group default; + }; + + register CXAFIR_ACT0 + { + name "P9 CAPP target CXAFIR ACT0"; + scomaddr 0x02010806; + capture group default; + capture req nonzero("CXAFIR"); + }; + + register CXAFIR_ACT1 + { + name "P9 CAPP target CXAFIR ACT1"; + scomaddr 0x02010807; + capture group default; + capture req nonzero("CXAFIR"); + }; + +# Include registers not defined by the xml +.include "p9_common_capp_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Summary for CAPP +################################################################################ + +rule rCAPP +{ + CHECK_STOP: + summary( 0, rCXAFIR ); + + RECOVERABLE: + summary( 0, rCXAFIR ); + + UNIT_CS: + summary( 0, rCXAFIR ); + +}; + +group gCAPP attntype CHECK_STOP, RECOVERABLE, UNIT_CS + filter singlebit +{ + (rCAPP, bit(0)) ? analyzeCXAFIR; +}; + +################################################################################ +# P9 CAPP target CXAFIR +################################################################################ + +rule rCXAFIR +{ + CHECK_STOP: + CXAFIR & ~CXAFIR_MASK & ~CXAFIR_ACT0 & ~CXAFIR_ACT1; + RECOVERABLE: + CXAFIR & ~CXAFIR_MASK & ~CXAFIR_ACT0 & CXAFIR_ACT1; + UNIT_CS: + CXAFIR & ~CXAFIR_MASK & CXAFIR_ACT0 & CXAFIR_ACT1; +}; + +group gCXAFIR + filter singlebit, + cs_root_cause +{ + /** CXAFIR[0] + * CXA Informational PE + */ + (rCXAFIR, bit(0)) ? defaultMaskedError; + + /** CXAFIR[1] + * CXA System Xstop PE + */ + (rCXAFIR, bit(1)) ? self_th_1; + + /** CXAFIR[2] + * CXA CE on Master array. + */ + (rCXAFIR, bit(2)) ? self_th_32perDay; + + /** CXAFIR[3] + * CXA UE on Master array. + */ + (rCXAFIR, bit(3)) ? self_th_1; + + /** CXAFIR[4] + * CXA Timer expired recoverable error + */ + (rCXAFIR, bit(4)) ? level2_th_1; + + /** CXAFIR[5] + * Recovery sequencer hang detection + */ + (rCXAFIR, bit(5)) ? self_th_1; + + /** CXAFIR[6] + * XPT saw UE on PB data + */ + (rCXAFIR, bit(6)) ? level2_th_1; + + /** CXAFIR[7] + * XPT saw SUE on PB data + */ + (rCXAFIR, bit(7)) ? level2_th_1_SUE; + + /** CXAFIR[8] + * Correctable error on Snooper array. + */ + (rCXAFIR, bit(8)) ? self_th_5perHour; + + /** CXAFIR[9] + * Uncorrectable error on Snooper array. + */ + (rCXAFIR, bit(9)) ? self_th_1; + + /** CXAFIR[10] + * RECOVERY_FAILED: CAPP recovery failed + */ + (rCXAFIR, bit(10)) ? self_th_1; + + /** CXAFIR[11] + * Illegal LPC BAR access + */ + (rCXAFIR, bit(11)) ? defaultMaskedError; + + /** CXAFIR[12] + * XPT recoverable error + */ + (rCXAFIR, bit(12)) ? defaultMaskedError; + + /** CXAFIR[13] + * Recoverable errors detected in Master + */ + (rCXAFIR, bit(13)) ? level2_th_1; + + /** CXAFIR[14] + * spare + */ + (rCXAFIR, bit(14)) ? defaultMaskedError; + + /** CXAFIR[15] + * Scom satellite parity error + */ + (rCXAFIR, bit(15)) ? defaultMaskedError; + + /** CXAFIR[16] + * CXA System checkstop errors in master + */ + (rCXAFIR, bit(16)) ? self_th_1; + + /** CXAFIR[17] + * CXA System checkstop errors in Snooper + */ + (rCXAFIR, bit(17)) ? self_th_1; + + /** CXAFIR[18] + * CXA transport System checkstop errors + */ + (rCXAFIR, bit(18)) ? self_th_1; + + /** CXAFIR[19] + * CXA Master uOP FIR 1 for lab use + */ + (rCXAFIR, bit(19)) ? defaultMaskedError; + + /** CXAFIR[20] + * CXA Master uOP FIR 2 for lab use + */ + (rCXAFIR, bit(20)) ? defaultMaskedError; + + /** CXAFIR[21] + * CXA Master uOP FIR 3 for lab use + */ + (rCXAFIR, bit(21)) ? defaultMaskedError; + + /** CXAFIR[22] + * Snooper uOP FIR 1 for lab use + */ + (rCXAFIR, bit(22)) ? defaultMaskedError; + + /** CXAFIR[23] + * Snooper uOP FIR 2 for lab use + */ + (rCXAFIR, bit(23)) ? defaultMaskedError; + + /** CXAFIR[24] + * Snooper uOP FIR 3 for lab use + */ + (rCXAFIR, bit(24)) ? defaultMaskedError; + + /** CXAFIR[25] + * Misc informational PowerBus error + */ + (rCXAFIR, bit(25)) ? parent_proc_th_1; + + /** CXAFIR[26] + * CXA Parity error on PowerBus interface + */ + (rCXAFIR, bit(26)) ? parent_proc_th_1; + + /** CXAFIR[27] + * CXA: Any PowerBus data hang poll error + */ + (rCXAFIR, bit(27)) ? defaultMaskedError; + + /** CXAFIR[28] + * CXA: PowerBus command hang error + */ + (rCXAFIR, bit(28)) ? defaultMaskedError; + + /** CXAFIR[29] + * CXA: PB Addr Error detected by APC : ld + */ + (rCXAFIR, bit(29)) ? self_M_level2_L_th_1; + + /** CXAFIR[30] + * CXA PB Addr Err detected by APC : st + */ + (rCXAFIR, bit(30)) ? self_M_level2_L_th_1; + + /** CXAFIR[31] + * CXA: PPHB0 or PHB1 i linkdown + */ + (rCXAFIR, bit(31)) ? level2_th_1; + + /** CXAFIR[32] + * APC ack_dead or ack_ed_dead + */ + (rCXAFIR, bit(32)) ? defaultMaskedError; + + /** CXAFIR[33] + * CXA Any PowerBus command hang error + */ + (rCXAFIR, bit(33)) ? defaultMaskedError; + + /** CXAFIR[34] + * CXA CE on data received from PB + */ + (rCXAFIR, bit(34)) ? self_th_5perHour; + + /** CXAFIR[35] + * CXA: UE on data received from PowerBus + */ + (rCXAFIR, bit(35)) ? self_th_1; # NIMBUS_20,CUMULUS_10 + + /** CXAFIR[36] + * CXA: SUE on data received from PowerBus + */ + (rCXAFIR, bit(36)) ? defaultMaskedError; + + /** CXAFIR[37] + * CXA: TLBI Timeout error. + */ + (rCXAFIR, bit(37)) ? level2_th_1; + + /** CXAFIR[38] + * CXA: TLBI seq_err. + */ + (rCXAFIR, bit(38)) ? parent_proc_th_1; + + /** CXAFIR[39] + * CXA: TLBI bad op error. + */ + (rCXAFIR, bit(39)) ? parent_proc_th_1; + + /** CXAFIR[40] + * CXA: PE on TLBI sequence number + */ + (rCXAFIR, bit(40)) ? level2_th_1; + + /** CXAFIR[41] + * APC received ack_dead or ack_ed_dead + */ + (rCXAFIR, bit(41)) ? defaultMaskedError; + + /** CXAFIR[42] + * TimeBase error + */ + (rCXAFIR, bit(42)) ? defaultMaskedError; + + /** CXAFIR[43] + * XPT Informational Error + */ + (rCXAFIR, bit(43)) ? defaultMaskedError; + + /** CXAFIR[44] + * Command_queue_CE + */ + (rCXAFIR, bit(44)) ? self_th_5perHour; + + /** CXAFIR[45] + * Command_queue_UE + */ + (rCXAFIR, bit(45)) ? self_th_1; + + /** CXAFIR[46] + * PSL credit timeout error + */ + (rCXAFIR, bit(46)) ? level2_th_1; + + /** CXAFIR[47] + * spare + */ + (rCXAFIR, bit(47)) ? defaultMaskedError; + + /** CXAFIR[48] + * Hypervisor asserted + */ + (rCXAFIR, bit(48)) ? level2_th_1; + + /** CXAFIR[49] + * spare + */ + (rCXAFIR, bit(49)) ? defaultMaskedError; + + /** CXAFIR[50] + * SCOM err + */ + (rCXAFIR, bit(50)) ? defaultMaskedError; + + /** CXAFIR[51] + * SCOM err + */ + (rCXAFIR, bit(51)) ? defaultMaskedError; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "p9_common_capp_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_ec.rule b/src/usr/diag/prdf/common/plat/axone/axone_ec.rule new file mode 100644 index 000000000..09602866f --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_ec.rule @@ -0,0 +1,651 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_ec.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_ec +{ + name "AXONE EC target"; + targettype TYPE_CORE; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # EC Chiplet FIR + ############################################################################ + + register EC_CHIPLET_CS_FIR + { + name "EC Chiplet Checkstop FIR"; + scomaddr 0x20040000; + capture group default; + }; + + register EC_CHIPLET_RE_FIR + { + name "EC Chiplet Recoverable FIR"; + scomaddr 0x20040001; + capture group default; + }; + + register EC_CHIPLET_FIR_MASK + { + name "EC Chiplet FIR MASK"; + scomaddr 0x20040002; + capture group default; + }; + + ############################################################################ + # EC Chiplet Unit Checkstop FIR + ############################################################################ + + register EC_CHIPLET_UCS_FIR + { + name "EC Chiplet Unit Checkstop FIR"; + scomaddr 0x20040018; + capture group default; + }; + + register EC_CHIPLET_UCS_FIR_MASK + { + name "EC Chiplet Unit Checkstop FIR MASK"; + scomaddr 0x20040019; + capture group default; + }; + + ############################################################################ + # P9 EC target EC_LFIR + ############################################################################ + + register EC_LFIR + { + name "P9 EC target EC_LFIR"; + scomaddr 0x2004000a; + reset (&, 0x2004000b); + mask (|, 0x2004000f); + capture group default; + }; + + register EC_LFIR_MASK + { + name "P9 EC target EC_LFIR MASK"; + scomaddr 0x2004000d; + capture group default; + }; + + register EC_LFIR_ACT0 + { + name "P9 EC target EC_LFIR ACT0"; + scomaddr 0x20040010; + capture group default; + capture req nonzero("EC_LFIR"); + }; + + register EC_LFIR_ACT1 + { + name "P9 EC target EC_LFIR ACT1"; + scomaddr 0x20040011; + capture group default; + capture req nonzero("EC_LFIR"); + }; + + ############################################################################ + # P9 EC target COREFIR + ############################################################################ + + register COREFIR + { + name "P9 EC target COREFIR"; + scomaddr 0x20010a40; + mask (|, 0x20010a45); + capture group default; + }; + + register COREFIR_MASK + { + name "P9 EC target COREFIR MASK"; + scomaddr 0x20010a43; + capture group default; + }; + + register COREFIR_ACT0 + { + name "P9 EC target COREFIR ACT0"; + scomaddr 0x20010a46; + capture group default; + }; + + register COREFIR_ACT1 + { + name "P9 EC target COREFIR ACT1"; + scomaddr 0x20010a47; + capture group default; + }; + + register COREFIR_WOF + { + name "P9 EC target COREFIR WOF"; + scomaddr 0x20010a48; + reset (|, 0x20010a48); + capture group default; + }; + +# Include registers not defined by the xml +.include "p9_common_ec_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# EC Chiplet FIR +################################################################################ + +rule rEC_CHIPLET_FIR +{ + CHECK_STOP: + EC_CHIPLET_CS_FIR & ~EC_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (EC_CHIPLET_RE_FIR >> 2) & ~EC_CHIPLET_FIR_MASK & `3fffffffffffffff`; +}; + +group gEC_CHIPLET_FIR attntype CHECK_STOP, RECOVERABLE + filter singlebit +{ + /** EC_CHIPLET_FIR[2] + * Unit Checkstop from COREFIR (bit0 in RER) + */ + (rEC_CHIPLET_FIR, bit(2)) ? analyzeCOREFIR; + + /** EC_CHIPLET_FIR[3] + * Attention from EC_LFIR + */ + (rEC_CHIPLET_FIR, bit(3)) ? analyzeEC_LFIR; + + /** EC_CHIPLET_FIR[4] + * Attention from COREFIR + */ + (rEC_CHIPLET_FIR, bit(4)) ? analyzeCOREFIR; + +}; + +################################################################################ +# EC Chiplet Unit Checkstop FIR +################################################################################ + +rule rEC_CHIPLET_UCS_FIR +{ + UNIT_CS: + EC_CHIPLET_UCS_FIR & ~(EC_CHIPLET_UCS_FIR_MASK >> 1) & `7fffffffffffffff`; +}; + +group gEC_CHIPLET_UCS_FIR attntype UNIT_CS + filter singlebit +{ + /** EC_CHIPLET_UCS_FIR[1] + * Attention from COREFIR + */ + (rEC_CHIPLET_UCS_FIR, bit(1)) ? analyzeCOREFIR; + +}; + +################################################################################ +# P9 EC target EC_LFIR +################################################################################ + +rule rEC_LFIR +{ + CHECK_STOP: + EC_LFIR & ~EC_LFIR_MASK & ~EC_LFIR_ACT0 & ~EC_LFIR_ACT1; + RECOVERABLE: + EC_LFIR & ~EC_LFIR_MASK & ~EC_LFIR_ACT0 & EC_LFIR_ACT1; +}; + +group gEC_LFIR + filter singlebit, + cs_root_cause +{ + /** EC_LFIR[0] + * CFIR internal parity error + */ + (rEC_LFIR, bit(0)) ? self_th_32perDay; + + /** EC_LFIR[1] + * Chiplet Control Reg: PCB Access Error + */ + (rEC_LFIR, bit(1)) ? self_th_32perDay; + + /** EC_LFIR[2] + * Clock Controller: PCB Access Error + */ + (rEC_LFIR, bit(2)) ? self_th_32perDay; + + /** EC_LFIR[3] + * Clock Controller: Summarized Error + */ + (rEC_LFIR, bit(3)) ? self_th_32perDay; + + /** EC_LFIR[4] + * PSCOM Logic: PCB Access Error + */ + (rEC_LFIR, bit(4)) ? defaultMaskedError; + + /** EC_LFIR[5] + * PSCOM Logic: Summarized internal errors + */ + (rEC_LFIR, bit(5)) ? defaultMaskedError; + + /** EC_LFIR[6] + * Therm Logic: Summarized internal errors + */ + (rEC_LFIR, bit(6)) ? defaultMaskedError; + + /** EC_LFIR[7] + * Therm Logic: PCB Access Error + */ + (rEC_LFIR, bit(7)) ? defaultMaskedError; + + /** EC_LFIR[8] + * Therm Logic: Temperature critical trip + */ + (rEC_LFIR, bit(8)) ? defaultMaskedError; + + /** EC_LFIR[9] + * Therm Logic: Temperature fatal trip + */ + (rEC_LFIR, bit(9)) ? defaultMaskedError; + + /** EC_LFIR[10] + * UNUSED in P9 + */ + (rEC_LFIR, bit(10)) ? defaultMaskedError; + + /** EC_LFIR[11] + * Debug Logic: Scom Satellite Error + */ + (rEC_LFIR, bit(11)) ? defaultMaskedError; + + /** EC_LFIR[12:40] + * spare + */ + (rEC_LFIR, bit(12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError; + + /** EC_LFIR[41] + * Malfunction Alert or Local Checkstop + */ + (rEC_LFIR, bit(41)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 EC target COREFIR +################################################################################ + +rule rCOREFIR +{ + CHECK_STOP: + COREFIR & ~COREFIR_MASK & ~COREFIR_ACT0 & ~COREFIR_ACT1; + RECOVERABLE: + COREFIR_WOF & ~COREFIR_MASK & ~COREFIR_ACT0 & COREFIR_ACT1; + UNIT_CS: + COREFIR & ~COREFIR_MASK & COREFIR_ACT0 & COREFIR_ACT1; +}; + +group gCOREFIR + filter priority(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,58,59,60,61,62,63,57), + cs_root_cause +{ + /** COREFIR[0] + * IFU SRAM Recoverable error + */ + (rCOREFIR, bit(0)) ? self_th_5perHour; + + /** COREFIR[1] + * TC Checkstop + */ + (rCOREFIR, bit(1)) ? self_th_1; + + /** COREFIR[2] + * Regfile Recoverable error from IFU + */ + (rCOREFIR, bit(2)) ? self_th_5perHour; + + /** COREFIR[3] + * Regfile core checkstop + */ + (rCOREFIR, bit(3)) ? self_th_1; + + /** COREFIR[4] + * IF Logic Recovery Err + */ + (rCOREFIR, bit(4)) ? self_th_5perHour; + + /** COREFIR[5] + * If Logic Checkstop + */ + (rCOREFIR, bit(5)) ? self_th_1; + + /** COREFIR[6:7] + * spare + */ + (rCOREFIR, bit(6|7)) ? defaultMaskedError; + + /** COREFIR[8] + * Recovery core checkstop + */ + (rCOREFIR, bit(8)) ? self_th_1; + + /** COREFIR[9] + * ISU Register File Recoverable Error + */ + (rCOREFIR, bit(9)) ? self_th_5perHour; + + /** COREFIR[10] + * ISU Regifle Core Checkstop Err + */ + (rCOREFIR, bit(10)) ? self_th_1; + + /** COREFIR[11] + * ISU Logic Recoverable Error + */ + (rCOREFIR, bit(11)) ? self_th_5perHour; + + /** COREFIR[12] + * ISU Logic Core Checkstop Err + */ + (rCOREFIR, bit(12)) ? self_th_1; + + /** COREFIR[13] + * ISU errr, recov if not in mt window + */ + (rCOREFIR, bit(13)) ? self_th_5perHour; + + /** COREFIR[14] + * Machine check and ME = 0 Err + */ + (rCOREFIR, bit(14)) ? self_th_1_SUE; + + /** COREFIR[15] + * LSU or IFU detected UE from L2 + */ + (rCOREFIR, bit(15)) ? defaultMaskedError; + + /** COREFIR[16] + * L2 UE over threshold error + */ + (rCOREFIR, bit(16)) ? defaultMaskedError; + + /** COREFIR[17] + * UE on a cache inhibited operation + */ + (rCOREFIR, bit(17)) ? defaultMaskedError; + + /** COREFIR[18] + * SW initiated reboot with diagnostics + */ + (rCOREFIR, bit(18)) ? level2_th_1; + + /** COREFIR[19] + * spare + */ + (rCOREFIR, bit(19)) ? defaultMaskedError; + + /** COREFIR[20] + * ISU checkstop MSR corrupted + */ + (rCOREFIR, bit(20)) ? self_th_1; + + /** COREFIR[21:23] + * spare + */ + (rCOREFIR, bit(21|22|23)) ? defaultMaskedError; + + /** COREFIR[24] + * VSU recoverable logic error + */ + (rCOREFIR, bit(24)) ? self_th_5perHour; + + /** COREFIR[25] + * VS Logic core checkstop + */ + (rCOREFIR, bit(25)) ? self_th_1; + + /** COREFIR[26] + * Core errors while in maintenance mode + */ + (rCOREFIR, bit(26)) ? level2_th_1; + + /** COREFIR[27] + * DFU recoverable error + */ + (rCOREFIR, bit(27)) ? self_th_5perHour; + + /** COREFIR[28] + * PC System Checkstop (recovery disabled) + */ + (rCOREFIR, bit(28)) ? self_th_1; + + /** COREFIR[29] + * LSU SRAM recoverable error + */ + (rCOREFIR, bit(29)) ? self_th_5perHour; + + /** COREFIR[30] + * LSU Set Delete Err + */ + (rCOREFIR, bit(30)) ? self_th_1; + + /** COREFIR[31] + * LSU Reg File Recoverable + */ + (rCOREFIR, bit(31)) ? self_th_5perHour; + + /** COREFIR[32] + * LSU Reg core checkstop + */ + (rCOREFIR, bit(32)) ? self_th_1; + + /** COREFIR[33] + * Special recovery error, tlb multi-hit + */ + (rCOREFIR, bit(33)) ? threshold_and_mask_self; + + /** COREFIR[34] + * LSU SLB multihit error + */ + (rCOREFIR, bit(34)) ? threshold_and_mask_self; + + /** COREFIR[35] + * LSU ERAT multihit error + */ + (rCOREFIR, bit(35)) ? threshold_and_mask_self; + + /** COREFIR[36] + * Forward Progress Error + */ + (rCOREFIR, bit(36)) ? self_th_1; + + /** COREFIR[37] + * LSU logic recoverable error + */ + (rCOREFIR, bit(37)) ? self_th_5perHour; + + /** COREFIR[38] + * LSU logic core checkstop error + */ + (rCOREFIR, bit(38)) ? self_th_1; + + /** COREFIR[39] + * LSU err, recov if not in mt window + */ + (rCOREFIR, bit(39)) ? self_th_5perHour; + + /** COREFIR[40] + * spare + */ + (rCOREFIR, bit(40)) ? defaultMaskedError; + + /** COREFIR[41] + * LSU system checkstop + */ + (rCOREFIR, bit(41)) ? self_th_1; + + /** COREFIR[42] + * spare + */ + (rCOREFIR, bit(42)) ? defaultMaskedError; + + /** COREFIR[43] + * Thread Hang caused recovery + */ + (rCOREFIR, bit(43)) ? self_level2_th_5perHour; + + /** COREFIR[44] + * spare + */ + (rCOREFIR, bit(44)) ? defaultMaskedError; + + /** COREFIR[45] + * PC core cs + */ + (rCOREFIR, bit(45)) ? self_th_1; + + /** COREFIR[46] + * spare + */ + (rCOREFIR, bit(46)) ? defaultMaskedError; + + /** COREFIR[47] + * Timebase facility unrecoverable error. + */ + (rCOREFIR, bit(47)) ? defaultMaskedError; + + /** COREFIR[48] + * Hypervisor resource parity error + */ + (rCOREFIR, bit(48)) ? self_th_1; + + /** COREFIR[49:51] + * spare + */ + (rCOREFIR, bit(49|50|51)) ? defaultMaskedError; + + /** COREFIR[52] + * Core Hang, recovery failed + */ + (rCOREFIR, bit(52)) ? self_th_1; + + /** COREFIR[53] + * Internal Core Hang, recovery attemped + */ + (rCOREFIR, bit(53)) ? defaultMaskedError; + + /** COREFIR[54] + * spare + */ + (rCOREFIR, bit(54)) ? defaultMaskedError; + + /** COREFIR[55] + * Nest hang detected, recovery attempted + */ + (rCOREFIR, bit(55)) ? self_M_level2_L_th_1; + + /** COREFIR[56] + * Other Core Recoverable error + */ + (rCOREFIR, bit(56)) ? defaultMaskedError; + + /** COREFIR[57] + * Other Core Core Checkstop + */ + (rCOREFIR, bit(57)) ? self_th_1; + + /** COREFIR[58] + * Other Core System Checkstop + */ + (rCOREFIR, bit(58)) ? defaultMaskedError; + + /** COREFIR[59] + * SCOM error handling + */ + (rCOREFIR, bit(59)) ? defaultMaskedError; + + /** COREFIR[60] + * debug checkstop on trigger + */ + (rCOREFIR, bit(60)) ? defaultMaskedError; + + /** COREFIR[61] + * SCOM or Recoverable error inject + */ + (rCOREFIR, bit(61)) ? defaultMaskedError; + + /** COREFIR[62] + * Firmware injected checkstop + */ + (rCOREFIR, bit(62)) ? defaultMaskedError; + + /** COREFIR[63] + * PHYP injected core checkstop + */ + (rCOREFIR, bit(63)) ? level2_th_1; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "p9_common_ec_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_eq.rule b/src/usr/diag/prdf/common/plat/axone/axone_eq.rule new file mode 100644 index 000000000..040cb1aac --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_eq.rule @@ -0,0 +1,367 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_eq.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_eq +{ + name "AXONE EQ target"; + targettype TYPE_EQ; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # EQ Chiplet FIR + ############################################################################ + + register EQ_CHIPLET_CS_FIR + { + name "EQ Chiplet Checkstop FIR"; + scomaddr 0x10040000; + capture group default; + }; + + register EQ_CHIPLET_RE_FIR + { + name "EQ Chiplet Recoverable FIR"; + scomaddr 0x10040001; + capture group default; + }; + + register EQ_CHIPLET_FIR_MASK + { + name "EQ Chiplet FIR MASK"; + scomaddr 0x10040002; + capture group default; + }; + + ############################################################################ + # P9 EQ target EQ_LFIR + ############################################################################ + + register EQ_LFIR + { + name "P9 EQ target EQ_LFIR"; + scomaddr 0x1004000a; + reset (&, 0x1004000b); + mask (|, 0x1004000f); + capture group default; + }; + + register EQ_LFIR_MASK + { + name "P9 EQ target EQ_LFIR MASK"; + scomaddr 0x1004000d; + capture group default; + }; + + register EQ_LFIR_ACT0 + { + name "P9 EQ target EQ_LFIR ACT0"; + scomaddr 0x10040010; + capture group default; + capture req nonzero("EQ_LFIR"); + }; + + register EQ_LFIR_ACT1 + { + name "P9 EQ target EQ_LFIR ACT1"; + scomaddr 0x10040011; + capture group default; + capture req nonzero("EQ_LFIR"); + }; + +# Include registers not defined by the xml +.include "p9_common_eq_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# EQ Chiplet FIR +################################################################################ + +rule rEQ_CHIPLET_FIR +{ + CHECK_STOP: + EQ_CHIPLET_CS_FIR & ~EQ_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (EQ_CHIPLET_RE_FIR >> 2) & ~EQ_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gEQ_CHIPLET_FIR attntype CHECK_STOP, RECOVERABLE + filter singlebit +{ + /** EQ_CHIPLET_FIR[3] + * Attention from EQ_LFIR + */ + (rEQ_CHIPLET_FIR, bit(3)) ? analyzeEQ_LFIR; + + /** EQ_CHIPLET_FIR[4] + * Attention from L3FIR 0 + */ + (rEQ_CHIPLET_FIR, bit(4)) ? analyzeConnectedEX0; + + /** EQ_CHIPLET_FIR[5] + * Attention from L3FIR 1 + */ + (rEQ_CHIPLET_FIR, bit(5)) ? analyzeConnectedEX1; + + /** EQ_CHIPLET_FIR[6] + * Attention from L2FIR 0 + */ + (rEQ_CHIPLET_FIR, bit(6)) ? analyzeConnectedEX0; + + /** EQ_CHIPLET_FIR[7] + * Attention from L2FIR 1 + */ + (rEQ_CHIPLET_FIR, bit(7)) ? analyzeConnectedEX1; + + /** EQ_CHIPLET_FIR[8] + * Attention from NCUFIR 0 + */ + (rEQ_CHIPLET_FIR, bit(8)) ? analyzeConnectedEX0; + + /** EQ_CHIPLET_FIR[9] + * Attention from NCUFIR 1 + */ + (rEQ_CHIPLET_FIR, bit(9)) ? analyzeConnectedEX1; + + /** EQ_CHIPLET_FIR[11] + * Attention from CMEFIR 0 + */ + (rEQ_CHIPLET_FIR, bit(11)) ? analyzeConnectedEX0; + + /** EQ_CHIPLET_FIR[12] + * Attention from CMEFIR 1 + */ + (rEQ_CHIPLET_FIR, bit(12)) ? analyzeConnectedEX1; + +}; + +################################################################################ +# P9 EQ target EQ_LFIR +################################################################################ + +rule rEQ_LFIR +{ + CHECK_STOP: + EQ_LFIR & ~EQ_LFIR_MASK & ~EQ_LFIR_ACT0 & ~EQ_LFIR_ACT1; + RECOVERABLE: + EQ_LFIR & ~EQ_LFIR_MASK & ~EQ_LFIR_ACT0 & EQ_LFIR_ACT1; +}; + +group gEQ_LFIR + filter singlebit, + cs_root_cause +{ + /** EQ_LFIR[0] + * CFIR internal parity error + */ + (rEQ_LFIR, bit(0)) ? self_th_32perDay; + + /** EQ_LFIR[1] + * Chiplet Control Reg: PCB Access Error + */ + (rEQ_LFIR, bit(1)) ? self_th_32perDay; + + /** EQ_LFIR[2] + * Clock Controller: PCB Access Error + */ + (rEQ_LFIR, bit(2)) ? self_th_32perDay; + + /** EQ_LFIR[3] + * Clock Controller: Summarized Error + */ + (rEQ_LFIR, bit(3)) ? self_th_32perDay; + + /** EQ_LFIR[4] + * PSCOM Logic: PCB Access Error + */ + (rEQ_LFIR, bit(4)) ? defaultMaskedError; + + /** EQ_LFIR[5] + * PSCOM Logic: Summarized internal errors + */ + (rEQ_LFIR, bit(5)) ? defaultMaskedError; + + /** EQ_LFIR[6] + * Therm Logic: Summarized internal errors + */ + (rEQ_LFIR, bit(6)) ? defaultMaskedError; + + /** EQ_LFIR[7] + * Therm Logic: PCB Access Error + */ + (rEQ_LFIR, bit(7)) ? defaultMaskedError; + + /** EQ_LFIR[8] + * Therm Logic: Temperature critical trip + */ + (rEQ_LFIR, bit(8)) ? defaultMaskedError; + + /** EQ_LFIR[9] + * Therm Logic: Temperature fatal trip + */ + (rEQ_LFIR, bit(9)) ? defaultMaskedError; + + /** EQ_LFIR[10] + * UNUSED in P9 + */ + (rEQ_LFIR, bit(10)) ? defaultMaskedError; + + /** EQ_LFIR[11] + * Debug Logic: Scom Satellite Error + */ + (rEQ_LFIR, bit(11)) ? defaultMaskedError; + + /** EQ_LFIR[12] + * Scom Satellite Error - L3 Trace0 + */ + (rEQ_LFIR, bit(12)) ? defaultMaskedError; + + /** EQ_LFIR[13] + * Scom Satellite Error - L3 Trace0 + */ + (rEQ_LFIR, bit(13)) ? defaultMaskedError; + + /** EQ_LFIR[14] + * Scom Satellite Error - L3 Trace1 + */ + (rEQ_LFIR, bit(14)) ? defaultMaskedError; + + /** EQ_LFIR[15] + * Scom Satellite Error - L3 Trace1 + */ + (rEQ_LFIR, bit(15)) ? defaultMaskedError; + + /** EQ_LFIR[16] + * Scom Satellite Error - L20 Trace0 + */ + (rEQ_LFIR, bit(16)) ? defaultMaskedError; + + /** EQ_LFIR[17] + * Scom Satellite Error - L20 Trace0 + */ + (rEQ_LFIR, bit(17)) ? defaultMaskedError; + + /** EQ_LFIR[18] + * Scom Satellite Error - L20 Trace1 + */ + (rEQ_LFIR, bit(18)) ? defaultMaskedError; + + /** EQ_LFIR[19] + * Scom Satellite Error - L20 Trace1 + */ + (rEQ_LFIR, bit(19)) ? defaultMaskedError; + + /** EQ_LFIR[20] + * Duty Cycle Adjust Logic error: cache clk + */ + (rEQ_LFIR, bit(20)) ? self_th_32perDay; + + /** EQ_LFIR[21] + * Duty Cycle Adjust Logic error: ex00_c0 + */ + (rEQ_LFIR, bit(21)) ? self_th_32perDay; + + /** EQ_LFIR[22] + * Duty Cycle Adjust error : ex00_c1 + */ + (rEQ_LFIR, bit(22)) ? self_th_32perDay; + + /** EQ_LFIR[23] + * Duty Cycle Adjust error : ex00_l2 + */ + (rEQ_LFIR, bit(23)) ? self_th_32perDay; + + /** EQ_LFIR[24] + * Duty Cycle Adjust Logic error : ex01_c0 + */ + (rEQ_LFIR, bit(24)) ? self_th_32perDay; + + /** EQ_LFIR[25] + * Duty Cycle Adjust Logic error : ex01_c1 + */ + (rEQ_LFIR, bit(25)) ? self_th_32perDay; + + /** EQ_LFIR[26] + * Duty Cycle Adjust Logic error : ex01_l2 + */ + (rEQ_LFIR, bit(26)) ? self_th_32perDay; + + /** EQ_LFIR[27] + * Skew Adjust Logic Data or deskew error + */ + (rEQ_LFIR, bit(27)) ? self_th_32perDay; + + /** EQ_LFIR[28:40] + * spare + */ + (rEQ_LFIR, bit(28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError; + + /** EQ_LFIR[41] + * Malfunction Alert or Local Checkstop + */ + (rEQ_LFIR, bit(41)) ? defaultMaskedError; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "p9_common_eq_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_ex.rule b/src/usr/diag/prdf/common/plat/axone/axone_ex.rule new file mode 100644 index 000000000..c943add56 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_ex.rule @@ -0,0 +1,904 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_ex.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_ex +{ + name "AXONE EX target"; + targettype TYPE_EX; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + +# Import signatures +.include "prdfP9ExExtraSig.H"; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # P9 EX target L2FIR + ############################################################################ + + register L2FIR + { + name "P9 EX target L2FIR"; + scomaddr 0x10010800; + reset (&, 0x10010801); + mask (|, 0x10010805); + capture group default; + }; + + register L2FIR_MASK + { + name "P9 EX target L2FIR MASK"; + scomaddr 0x10010803; + capture group default; + }; + + register L2FIR_ACT0 + { + name "P9 EX target L2FIR ACT0"; + scomaddr 0x10010806; + capture group default; + capture req nonzero("L2FIR"); + }; + + register L2FIR_ACT1 + { + name "P9 EX target L2FIR ACT1"; + scomaddr 0x10010807; + capture group default; + capture req nonzero("L2FIR"); + }; + + ############################################################################ + # P9 EX target NCUFIR + ############################################################################ + + register NCUFIR + { + name "P9 EX target NCUFIR"; + scomaddr 0x10011000; + reset (&, 0x10011001); + mask (|, 0x10011005); + capture group default; + }; + + register NCUFIR_MASK + { + name "P9 EX target NCUFIR MASK"; + scomaddr 0x10011003; + capture group default; + }; + + register NCUFIR_ACT0 + { + name "P9 EX target NCUFIR ACT0"; + scomaddr 0x10011006; + capture group default; + capture req nonzero("NCUFIR"); + }; + + register NCUFIR_ACT1 + { + name "P9 EX target NCUFIR ACT1"; + scomaddr 0x10011007; + capture group default; + capture req nonzero("NCUFIR"); + }; + + ############################################################################ + # P9 EX target L3FIR + ############################################################################ + + register L3FIR + { + name "P9 EX target L3FIR"; + scomaddr 0x10011800; + reset (&, 0x10011801); + mask (|, 0x10011805); + capture group default; + }; + + register L3FIR_MASK + { + name "P9 EX target L3FIR MASK"; + scomaddr 0x10011803; + capture group default; + }; + + register L3FIR_ACT0 + { + name "P9 EX target L3FIR ACT0"; + scomaddr 0x10011806; + capture group default; + capture req nonzero("L3FIR"); + }; + + register L3FIR_ACT1 + { + name "P9 EX target L3FIR ACT1"; + scomaddr 0x10011807; + capture group default; + capture req nonzero("L3FIR"); + }; + + ############################################################################ + # P9 EX target CMEFIR + ############################################################################ + + register CMEFIR + { + name "P9 EX target CMEFIR"; + scomaddr 0x10012000; + reset (&, 0x10012001); + mask (|, 0x10012005); + capture group default; + }; + + register CMEFIR_MASK + { + name "P9 EX target CMEFIR MASK"; + scomaddr 0x10012003; + capture group default; + }; + + register CMEFIR_ACT0 + { + name "P9 EX target CMEFIR ACT0"; + scomaddr 0x10012006; + capture group default; + capture req nonzero("CMEFIR"); + }; + + register CMEFIR_ACT1 + { + name "P9 EX target CMEFIR ACT1"; + scomaddr 0x10012007; + capture group default; + capture req nonzero("CMEFIR"); + }; + +# Include registers not defined by the xml +.include "p9_common_ex_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Summary for EX +################################################################################ + +rule rEX +{ + CHECK_STOP: + summary( 0, rL2FIR ) | + summary( 1, rNCUFIR ) | + summary( 2, rL3FIR ) | + summary( 3, rCMEFIR ); + + RECOVERABLE: + summary( 0, rL2FIR ) | + summary( 1, rNCUFIR ) | + summary( 2, rL3FIR ) | + summary( 3, rCMEFIR ); + +}; + +group gEX attntype CHECK_STOP, RECOVERABLE + filter singlebit +{ + (rEX, bit(0)) ? analyzeL2FIR; + (rEX, bit(1)) ? analyzeNCUFIR; + (rEX, bit(2)) ? analyzeL3FIR; + (rEX, bit(3)) ? analyzeCMEFIR; +}; + +################################################################################ +# P9 EX target L2FIR +################################################################################ + +rule rL2FIR +{ + CHECK_STOP: + L2FIR & ~L2FIR_MASK & ~L2FIR_ACT0 & ~L2FIR_ACT1; + RECOVERABLE: + L2FIR & ~L2FIR_MASK & ~L2FIR_ACT0 & L2FIR_ACT1; +}; + +group gL2FIR + filter singlebit, + cs_root_cause(1,17,18,20) +{ + /** L2FIR[0] + * L2 cache read CE + */ + (rL2FIR, bit(0)) ? l2_cache_ce; + + /** L2FIR[1] + * L2 cache read UE + */ + (rL2FIR, bit(1)) ? l2_cache_ue_UERE; + + /** L2FIR[2] + * L2 cache read SUE + */ + (rL2FIR, bit(2)) ? defaultMaskedError; + + /** L2FIR[3] + * Hw directory initiated line delete + */ + (rL2FIR, bit(3)) ? defaultMaskedError; + + /** L2FIR[4] + * ue or sue detected by on modified line + */ + (rL2FIR, bit(4)) ? defaultMaskedError; + + /** L2FIR[5] + * ue or sue detected on non-modified line + */ + (rL2FIR, bit(5)) ? defaultMaskedError; + + /** L2FIR[6] + * L2 directory read CE + */ + (rL2FIR, bit(6)) ? l2_dir_ce; + + /** L2FIR[7] + * L2 directory read UE + */ + (rL2FIR, bit(7)) ? self_th_1; + + /** L2FIR[8] + * L2 directory CE due to stuck bit + */ + (rL2FIR, bit(8)) ? self_th_1; + + /** L2FIR[9] + * L2 directory stuck bit CE repair failed + */ + (rL2FIR, bit(9)) ? self_th_1; + + /** L2FIR[10] + * Muliple l2 cache dir errors + */ + (rL2FIR, bit(10)) ? defaultMaskedError; + + /** L2FIR[11] + * LRU read error detected + */ + (rL2FIR, bit(11)) ? self_th_32perDay; + + /** L2FIR[12] + * RC Powerbus data timeout + */ + (rL2FIR, bit(12)) ? level2_th_1; + + /** L2FIR[13] + * NCU Powerbus data timeout + */ + (rL2FIR, bit(13)) ? level2_th_1; + + /** L2FIR[14] + * Hardware control error + */ + (rL2FIR, bit(14)) ? level2_M_proc_L_th_1; + + /** L2FIR[15] + * LRU all members in a class line deleted + */ + (rL2FIR, bit(15)) ? self_th_1; + + /** L2FIR[16] + * Cache line inhibited hit cacheable space + */ + (rL2FIR, bit(16)) ? self_th_1; + + /** L2FIR[17] + * (RC) load received pb cresp addr error + */ + (rL2FIR, bit(17)) ? self_M_level2_L_th_1; + + /** L2FIR[18] + * (RC) store received pb cresp addr error + */ + (rL2FIR, bit(18)) ? self_M_level2_L_th_1; + + /** L2FIR[19] + * Rc or NCU Pb data CE error + */ + (rL2FIR, bit(19)) ? l2_power_bus_ce; + + /** L2FIR[20] + * RC or NCU Pb data UE error + */ + (rL2FIR, bit(20)) ? self_th_1_UERE; + + /** L2FIR[21] + * RC or NCU PB data SUE detected + */ + (rL2FIR, bit(21)) ? defaultMaskedError; + + /** L2FIR[22] + * TGT_NODAL_REQ_DINC_ERR + */ + (rL2FIR, bit(22)) ? self_th_1; + + /** L2FIR[23] + * RC fabric op Ld cresp addr error for hyp + */ + (rL2FIR, bit(23)) ? defaultMaskedError; + + /** L2FIR[24] + * PE on data from RCDAT + */ + (rL2FIR, bit(24)) ? self_th_1; + + /** L2FIR[25] + * L2 castout or CN cresp addr err + */ + (rL2FIR, bit(25)) ? self_M_level2_L_th_1; + + /** L2FIR[26] + * LVDIR tracking PE + */ + (rL2FIR, bit(26)) ? self_th_32perDay; + + /** L2FIR[27] + * RC fabric op cresp=ack_dead error + */ + (rL2FIR, bit(27)) ? defaultMaskedError; + + /** L2FIR[28] + * Darn data timeout + */ + (rL2FIR, bit(28)) ? self_th_1; + + /** L2FIR[29] + * RC fabric op store cresp/misc error + */ + (rL2FIR, bit(29)) ? defaultMaskedError; + + /** L2FIR[30:35] + * spare + */ + (rL2FIR, bit(30|31|32|33|34|35)) ? defaultMaskedError; + + /** L2FIR[36] + * Cache CE and UE in short time period + */ + (rL2FIR, bit(36)) ? threshold_and_mask_self; + + /** L2FIR[37:38] + * spare + */ + (rL2FIR, bit(37|38)) ? defaultMaskedError; + + /** L2FIR[39] + * reserved + */ + (rL2FIR, bit(39)) ? defaultMaskedError; + + /** L2FIR[40] + * scom error + */ + (rL2FIR, bit(40)) ? defaultMaskedError; + + /** L2FIR[41] + * scom error + */ + (rL2FIR, bit(41)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 EX target NCUFIR +################################################################################ + +rule rNCUFIR +{ + CHECK_STOP: + NCUFIR & ~NCUFIR_MASK & ~NCUFIR_ACT0 & ~NCUFIR_ACT1; + RECOVERABLE: + NCUFIR & ~NCUFIR_MASK & ~NCUFIR_ACT0 & NCUFIR_ACT1; +}; + +group gNCUFIR + filter singlebit, + cs_root_cause(3,4,7,8) +{ + /** NCUFIR[0] + * NCU store queue control error + */ + (rNCUFIR, bit(0)) ? self_th_1; + + /** NCUFIR[1] + * TLBIE control error. + */ + (rNCUFIR, bit(1)) ? level2_M_self_L_th_1; + + /** NCUFIR[2] + * TL or SLBIEG illegal fields from core. + */ + (rNCUFIR, bit(2)) ? level2_M_self_L_th_1; + + /** NCUFIR[3] + * NCU Store Address Error + */ + (rNCUFIR, bit(3)) ? self_M_level2_L_th_1; + + /** NCUFIR[4] + * NCU load Address Error + */ + (rNCUFIR, bit(4)) ? self_M_level2_L_th_1; + + /** NCUFIR[5] + * Store received ack_dead. + */ + (rNCUFIR, bit(5)) ? defaultMaskedError; + + /** NCUFIR[6] + * Load received ack_dead. + */ + (rNCUFIR, bit(6)) ? defaultMaskedError; + + /** NCUFIR[7] + * MSGSND received addr_err + */ + (rNCUFIR, bit(7)) ? self_M_level2_L_th_1; + + /** NCUFIR[8] + * NCU Store Queue Data Parity Err + */ + (rNCUFIR, bit(8)) ? self_th_1_UERE; + + /** NCUFIR[9] + * store timed out on pb + */ + (rNCUFIR, bit(9)) ? threshold_and_mask_self; + + /** NCUFIR[10] + * tlbie master timeout + */ + (rNCUFIR, bit(10)) ? level2_M_self_L_th_1; + + /** NCUFIR[11] + * NCU no response to snooped TLBIE + */ + (rNCUFIR, bit(11)) ? level2_M_self_L_th_1; + + /** NCUFIR[12] + * ima cresp addr error + */ + (rNCUFIR, bit(12)) ? self_M_level2_L_th_1; + + /** NCUFIR[13] + * ima received ack_dead + */ + (rNCUFIR, bit(13)) ? defaultMaskedError; + + /** NCUFIR[14] + * pmisc cresp addr err + */ + (rNCUFIR, bit(14)) ? self_M_level2_L_th_1; + + /** NCUFIR[15] + * PPE read cresp address error + */ + (rNCUFIR, bit(15)) ? self_M_level2_L_th_1; + + /** NCUFIR[16] + * PPE write cresp address error + */ + (rNCUFIR, bit(16)) ? self_M_level2_L_th_1; + + /** NCUFIR[17] + * ppe read received ack dead + */ + (rNCUFIR, bit(17)) ? defaultMaskedError; + + /** NCUFIR[18] + * ppe write received ack dead + */ + (rNCUFIR, bit(18)) ? defaultMaskedError; + + /** NCUFIR[19] + * tgt nodal ppe write received ack dead + */ + (rNCUFIR, bit(19)) ? defaultMaskedError; + + /** NCUFIR[20] + * darn ttype while darn not enabled + */ + (rNCUFIR, bit(20)) ? level2_M_self_L_th_1; + + /** NCUFIR[21] + * Darn cresp address error + */ + (rNCUFIR, bit(21)) ? level2_M_self_L_th_1; + + /** NCUFIR[22:28] + * spare + */ + (rNCUFIR, bit(22|23|24|25|26|27|28)) ? defaultMaskedError; + + /** NCUFIR[29] + * scom error + */ + (rNCUFIR, bit(29)) ? defaultMaskedError; + + /** NCUFIR[30] + * scom error + */ + (rNCUFIR, bit(30)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 EX target L3FIR +################################################################################ + +rule rL3FIR +{ + CHECK_STOP: + L3FIR & ~L3FIR_MASK & ~L3FIR_ACT0 & ~L3FIR_ACT1; + RECOVERABLE: + L3FIR & ~L3FIR_MASK & ~L3FIR_ACT0 & L3FIR_ACT1; +}; + +group gL3FIR + filter singlebit, + cs_root_cause(5,8,11,17,21) +{ + /** L3FIR[0] + * L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR + */ + (rL3FIR, bit(0)) ? self_th_1; + + /** L3FIR[1:2] + * spare + */ + (rL3FIR, bit(1|2)) ? defaultMaskedError; + + /** L3FIR[3] + * L3 cache CE and UE within a short period + */ + (rL3FIR, bit(3)) ? threshold_and_mask_self; + + /** L3FIR[4] + * CE detected on L3 cache read + */ + (rL3FIR, bit(4)) ? l3_cache_ce; + + /** L3FIR[5] + * UE detected on L3 cache read + */ + (rL3FIR, bit(5)) ? l3_cache_ue_UERE; + + /** L3FIR[6] + * SUE detected on L3 cache read + */ + (rL3FIR, bit(6)) ? defaultMaskedError; + + /** L3FIR[7] + * L3 cache write data CE from Power Bus + */ + (rL3FIR, bit(7)) ? self_th_32perDay; + + /** L3FIR[8] + * L3 cache write data UE from Power Bus + */ + (rL3FIR, bit(8)) ? self_th_1_UERE; + + /** L3FIR[9] + * L3 cache write data sue from Power Bus + */ + (rL3FIR, bit(9)) ? defaultMaskedError; + + /** L3FIR[10] + * L3 cache write data CE from L2 + */ + (rL3FIR, bit(10)) ? self_th_32perDay; + + /** L3FIR[11] + * L3 cache write data UE from L2 + */ + (rL3FIR, bit(11)) ? l3_cache_ue_UERE; + + /** L3FIR[12] + * L3 cache write SUE from L2 + */ + (rL3FIR, bit(12)) ? defaultMaskedError; + + /** L3FIR[13] + * L3 DIR read CE + */ + (rL3FIR, bit(13)) ? l3_dir_ce; + + /** L3FIR[14] + * L3 Dir read UE + */ + (rL3FIR, bit(14)) ? self_th_1; + + /** L3FIR[15] + * Dir error not found during corr seq. + */ + (rL3FIR, bit(15)) ? defaultMaskedError; + + /** L3FIR[16] + * addr_error cresp for mem SN or CO + */ + (rL3FIR, bit(16)) ? self_M_level2_L_th_1; + + /** L3FIR[17] + * Received addr_error cresp for Prefetch + */ + (rL3FIR, bit(17)) ? self_M_level2_L_th_1; + + /** L3FIR[18] + * An L3 machine hung waiting for PB cresp + */ + (rL3FIR, bit(18)) ? defaultMaskedError; + + /** L3FIR[19] + * Invalid LRU count error + */ + (rL3FIR, bit(19)) ? defaultMaskedError; + + /** L3FIR[20] + * CE detected on PowerBus read for PPE + */ + (rL3FIR, bit(20)) ? self_th_32perDay; + + /** L3FIR[21] + * UE detected on PowerBus read for PPE + */ + (rL3FIR, bit(21)) ? self_th_1_UERE; + + /** L3FIR[22] + * L3 PPE SUE + */ + (rL3FIR, bit(22)) ? defaultMaskedError; + + /** L3FIR[23] + * L3 mach hang + */ + (rL3FIR, bit(23)) ? self_M_level2_L_th_1; + + /** L3FIR[24] + * L3 Hw control err + */ + (rL3FIR, bit(24)) ? self_th_1; + + /** L3FIR[25] + * Cache inhitited op in L3 directory + */ + (rL3FIR, bit(25)) ? self_M_level2_L_th_1; + + /** L3FIR[26] + * L3 line delete CE done + */ + (rL3FIR, bit(26)) ? defaultMaskedError; + + /** L3FIR[27] + * L3 DRAM logic error + */ + (rL3FIR, bit(27)) ? self_th_1; + + /** L3FIR[28] + * L3 LRU array parity error + */ + (rL3FIR, bit(28)) ? l3_lru_parity_error; + + /** L3FIR[29] + * L3 cache congruence class deleted + */ + (rL3FIR, bit(29)) ? self_th_1; + + /** L3FIR[30] + * L3 cache timer refresh error + */ + (rL3FIR, bit(30)) ? self_th_1; + + /** L3FIR[31] + * L3 PowerBus Master Write CRESP ack_dead + */ + (rL3FIR, bit(31)) ? defaultMaskedError; + + /** L3FIR[32] + * PB Master Read received ack_dead CRESP + */ + (rL3FIR, bit(32)) ? defaultMaskedError; + + /** L3FIR[33] + * scom error + */ + (rL3FIR, bit(33)) ? defaultMaskedError; + + /** L3FIR[34] + * scom error + */ + (rL3FIR, bit(34)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 EX target CMEFIR +################################################################################ + +rule rCMEFIR +{ + CHECK_STOP: + CMEFIR & ~CMEFIR_MASK & ~CMEFIR_ACT0 & ~CMEFIR_ACT1; + RECOVERABLE: + CMEFIR & ~CMEFIR_MASK & ~CMEFIR_ACT0 & CMEFIR_ACT1; +}; + +group gCMEFIR + filter singlebit, + cs_root_cause +{ + /** CMEFIR[0] + * PPE asserted an internal error + */ + (rCMEFIR, bit(0)) ? TBDDefaultCallout; + + /** CMEFIR[1] + * PPE external interface error + */ + (rCMEFIR, bit(1)) ? TBDDefaultCallout; + + /** CMEFIR[2] + * PPE lack of forward progress + */ + (rCMEFIR, bit(2)) ? TBDDefaultCallout; + + /** CMEFIR[3] + * PPE software-requested breakpoint event. + */ + (rCMEFIR, bit(3)) ? TBDDefaultCallout; + + /** CMEFIR[4] + * PPE watchdog timeout + */ + (rCMEFIR, bit(4)) ? TBDDefaultCallout; + + /** CMEFIR[5] + * PPE asserted a halt condition. + */ + (rCMEFIR, bit(5)) ? defaultMaskedError; + + /** CMEFIR[6] + * PPE asserted a debug trigger + */ + (rCMEFIR, bit(6)) ? defaultMaskedError; + + /** CMEFIR[7] + * PPE SRAM Uncorrectable Error. + */ + (rCMEFIR, bit(7)) ? self_th_1; + + /** CMEFIR[8] + * SRAM Correctable Error + */ + (rCMEFIR, bit(8)) ? threshold_and_mask_self; + + /** CMEFIR[9] + * Scrub timer tick, scrub still pending + */ + (rCMEFIR, bit(9)) ? threshold_and_mask_self; + + /** CMEFIR[10] + * Block Copy Engine Error + */ + (rCMEFIR, bit(10)) ? defaultMaskedError; + + /** CMEFIR[11:12] + * spare + */ + (rCMEFIR, bit(11|12)) ? defaultMaskedError; + + /** CMEFIR[13] + * Dropout detected on Core0 Chiplet iVRM + */ + (rCMEFIR, bit(13)) ? defaultMaskedError; + + /** CMEFIR[14] + * Dropout detected on Core1 Chiplet iVRM + */ + (rCMEFIR, bit(14)) ? defaultMaskedError; + + /** CMEFIR[15] + * CME Dropout Cache Chiplet iVRM. + */ + (rCMEFIR, bit(15)) ? defaultMaskedError; + + /** CMEFIR[16] + * CME Extreme Droop over time exceeded + */ + (rCMEFIR, bit(16)) ? defaultMaskedError; + + /** CMEFIR[17] + * CME Large Droop exceeded + */ + (rCMEFIR, bit(17)) ? defaultMaskedError; + + /** CMEFIR[18] + * CME Small Droop exceeded + */ + (rCMEFIR, bit(18)) ? defaultMaskedError; + + /** CMEFIR[19] + * Detected non-thermometer code + */ + (rCMEFIR, bit(19)) ? defaultMaskedError; + + /** CMEFIR[20] + * scom error + */ + (rCMEFIR, bit(20)) ? defaultMaskedError; + + /** CMEFIR[21] + * scom error + */ + (rCMEFIR, bit(21)) ? defaultMaskedError; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "p9_common_ex_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mc.rule b/src/usr/diag/prdf/common/plat/axone/axone_mc.rule new file mode 100644 index 000000000..4f63011fc --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_mc.rule @@ -0,0 +1,671 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_mc.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_mc +{ + name "AXONE MC target"; + targettype TYPE_MC; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # MC Chiplet FIR + ############################################################################ + + register MC_CHIPLET_CS_FIR + { + name "MC Chiplet Checkstop FIR"; + scomaddr 0x07040000; + capture group default; + }; + + register MC_CHIPLET_RE_FIR + { + name "MC Chiplet Recoverable FIR"; + scomaddr 0x07040001; + capture group default; + }; + + register MC_CHIPLET_FIR_MASK + { + name "MC Chiplet FIR MASK"; + scomaddr 0x07040002; + capture group default; + }; + + ############################################################################ + # MC Chiplet Unit Checkstop FIR + ############################################################################ + + register MC_CHIPLET_UCS_FIR + { + name "MC Chiplet Unit Checkstop FIR"; + scomaddr 0x07040018; + capture group default; + }; + + register MC_CHIPLET_UCS_FIR_MASK + { + name "MC Chiplet Unit Checkstop FIR MASK"; + scomaddr 0x07040019; + capture group default; + }; + + ############################################################################ + # MC Chiplet Host Attention FIR + ############################################################################ + + register MC_CHIPLET_HA_FIR + { + name "MC Chiplet Host Attention FIR"; + scomaddr 0x07040009; + capture group default; + }; + + register MC_CHIPLET_HA_FIR_MASK + { + name "MC Chiplet Host Attention FIR MASK"; + scomaddr 0x0704001a; + capture group default; + }; + + ############################################################################ + # P9 chip MC_LFIR + ############################################################################ + + register MC_LFIR + { + name "P9 chip MC_LFIR"; + scomaddr 0x0704000a; + reset (&, 0x0704000b); + mask (|, 0x0704000f); + capture group default; + }; + + register MC_LFIR_MASK + { + name "P9 chip MC_LFIR MASK"; + scomaddr 0x0704000d; + capture group default; + }; + + register MC_LFIR_ACT0 + { + name "P9 chip MC_LFIR ACT0"; + scomaddr 0x07040010; + capture group default; + capture req nonzero("MC_LFIR"); + }; + + register MC_LFIR_ACT1 + { + name "P9 chip MC_LFIR ACT1"; + scomaddr 0x07040011; + capture group default; + capture req nonzero("MC_LFIR"); + }; + + ############################################################################ + # P9 MC target MCBISTFIR + ############################################################################ + + register MCBISTFIR + { + name "P9 MC target MCBISTFIR"; + scomaddr 0x07012300; + reset (&, 0x07012301); + mask (|, 0x07012305); + capture group default; + }; + + register MCBISTFIR_MASK + { + name "P9 MC target MCBISTFIR MASK"; + scomaddr 0x07012303; + capture group default; + }; + + register MCBISTFIR_ACT0 + { + name "P9 MC target MCBISTFIR ACT0"; + scomaddr 0x07012306; + capture group default; + capture req nonzero("MCBISTFIR"); + }; + + register MCBISTFIR_ACT1 + { + name "P9 MC target MCBISTFIR ACT1"; + scomaddr 0x07012307; + capture group default; + capture req nonzero("MCBISTFIR"); + }; + +# Include registers not defined by the xml +.include "axone_mc_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# MC Chiplet FIR +################################################################################ + +rule rMC_CHIPLET_FIR +{ + CHECK_STOP: + MC_CHIPLET_CS_FIR & ~MC_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (MC_CHIPLET_RE_FIR >> 2) & ~MC_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gMC_CHIPLET_FIR attntype CHECK_STOP, RECOVERABLE + filter singlebit +{ + /** MC_CHIPLET_FIR[3] + * Attention from MC_LFIR + */ + (rMC_CHIPLET_FIR, bit(3)) ? analyzeMC_LFIR; + + /** MC_CHIPLET_FIR[4] + * Attention from DSTLFIR 0 + */ + (rMC_CHIPLET_FIR, bit(4)) ? analyzeConnectedMCC0; + + /** MC_CHIPLET_FIR[5] + * Attention from USTLFIR 0 + */ + (rMC_CHIPLET_FIR, bit(5)) ? analyzeConnectedMCC0; + + /** MC_CHIPLET_FIR[6] + * Attention from DSTLFIR 1 + */ + (rMC_CHIPLET_FIR, bit(6)) ? analyzeConnectedMCC1; + + /** MC_CHIPLET_FIR[7] + * Attention from USTLFIR 1 + */ + (rMC_CHIPLET_FIR, bit(7)) ? analyzeConnectedMCC1; + + /** MC_CHIPLET_FIR[8] + * Attention from DSTLFIR 2 + */ + (rMC_CHIPLET_FIR, bit(8)) ? analyzeConnectedMCC2; + + /** MC_CHIPLET_FIR[9] + * Attention from USTLFIR 2 + */ + (rMC_CHIPLET_FIR, bit(9)) ? analyzeConnectedMCC2; + + /** MC_CHIPLET_FIR[10] + * Attention from DSTLFIR 3 + */ + (rMC_CHIPLET_FIR, bit(10)) ? analyzeConnectedMCC3; + + /** MC_CHIPLET_FIR[11] + * Attention from USTLFIR 3 + */ + (rMC_CHIPLET_FIR, bit(11)) ? analyzeConnectedMCC3; + + /** MC_CHIPLET_FIR[12] + * Attention from MCBISTFIR + */ + (rMC_CHIPLET_FIR, bit(12)) ? analyzeMCBISTFIR; + + /** MC_CHIPLET_FIR[13] + * Attention from IOOMIFIR 0 + */ + (rMC_CHIPLET_FIR, bit(13)) ? analyzeConnectedOMIC0; + + /** MC_CHIPLET_FIR[14] + * Attention from IOOMIFIR 1 + */ + (rMC_CHIPLET_FIR, bit(14)) ? analyzeConnectedOMIC1; + + /** MC_CHIPLET_FIR[15] + * Attention from IOOMIFIR 2 + */ + (rMC_CHIPLET_FIR, bit(15)) ? analyzeConnectedOMIC2; + + /** MC_CHIPLET_FIR[16] + * Attention from MCPPEFIR 0 + */ + (rMC_CHIPLET_FIR, bit(16)) ? analyzeConnectedOMIC0; + + /** MC_CHIPLET_FIR[17] + * Attention from MCPPEFIR 1 + */ + (rMC_CHIPLET_FIR, bit(17)) ? analyzeConnectedOMIC1; + + /** MC_CHIPLET_FIR[18] + * Attention from MCPPEFIR 2 + */ + (rMC_CHIPLET_FIR, bit(18)) ? analyzeConnectedOMIC2; + + /** MC_CHIPLET_FIR[19] + * Attention from OMIDLFIR 0 + */ + (rMC_CHIPLET_FIR, bit(19)) ? analyzeConnectedOMIC0; + + /** MC_CHIPLET_FIR[20] + * Attention from OMIDLFIR 1 + */ + (rMC_CHIPLET_FIR, bit(20)) ? analyzeConnectedOMIC1; + + /** MC_CHIPLET_FIR[21] + * Attention from OMIDLFIR 2 + */ + (rMC_CHIPLET_FIR, bit(21)) ? analyzeConnectedOMIC2; + +}; + +################################################################################ +# MC Chiplet Unit Checkstop FIR +################################################################################ + +rule rMC_CHIPLET_UCS_FIR +{ + UNIT_CS: + MC_CHIPLET_UCS_FIR & ~(MC_CHIPLET_UCS_FIR_MASK >> 1) & `7fffffffffffffff`; +}; + +group gMC_CHIPLET_UCS_FIR attntype UNIT_CS + filter singlebit +{ + /** MC_CHIPLET_UCS_FIR[1] + * Attention from DSTLFIR 0 + */ + (rMC_CHIPLET_UCS_FIR, bit(1)) ? analyzeConnectedMCC0; + + /** MC_CHIPLET_UCS_FIR[2] + * Attention from USTLFIR 0 + */ + (rMC_CHIPLET_UCS_FIR, bit(2)) ? analyzeConnectedMCC0; + + /** MC_CHIPLET_UCS_FIR[3] + * Attention from DSTLFIR 1 + */ + (rMC_CHIPLET_UCS_FIR, bit(3)) ? analyzeConnectedMCC1; + + /** MC_CHIPLET_UCS_FIR[4] + * Attention from USTLFIR 1 + */ + (rMC_CHIPLET_UCS_FIR, bit(4)) ? analyzeConnectedMCC1; + + /** MC_CHIPLET_UCS_FIR[5] + * Attention from DSTLFIR 2 + */ + (rMC_CHIPLET_UCS_FIR, bit(5)) ? analyzeConnectedMCC2; + + /** MC_CHIPLET_UCS_FIR[6] + * Attention from USTLFIR 2 + */ + (rMC_CHIPLET_UCS_FIR, bit(6)) ? analyzeConnectedMCC2; + + /** MC_CHIPLET_UCS_FIR[7] + * Attention from DSTLFIR 3 + */ + (rMC_CHIPLET_UCS_FIR, bit(7)) ? analyzeConnectedMCC3; + + /** MC_CHIPLET_UCS_FIR[8] + * Attention from USTLFIR 3 + */ + (rMC_CHIPLET_UCS_FIR, bit(8)) ? analyzeConnectedMCC3; + + /** MC_CHIPLET_UCS_FIR[9] + * Attention from MCBISTFIR + */ + (rMC_CHIPLET_UCS_FIR, bit(9)) ? analyzeMCBISTFIR; + + /** MC_CHIPLET_UCS_FIR[10] + * Attention from IOOMIFIR 0 + */ + (rMC_CHIPLET_UCS_FIR, bit(10)) ? analyzeConnectedOMIC0; + + /** MC_CHIPLET_UCS_FIR[11] + * Attention from IOOMIFIR 1 + */ + (rMC_CHIPLET_UCS_FIR, bit(11)) ? analyzeConnectedOMIC1; + + /** MC_CHIPLET_UCS_FIR[12] + * Attention from IOOMIFIR 2 + */ + (rMC_CHIPLET_UCS_FIR, bit(12)) ? analyzeConnectedOMIC2; + + /** MC_CHIPLET_UCS_FIR[13] + * Attention from MCPPEFIR 0 + */ + (rMC_CHIPLET_UCS_FIR, bit(13)) ? analyzeConnectedOMIC0; + + /** MC_CHIPLET_UCS_FIR[14] + * Attention from MCPPEFIR 1 + */ + (rMC_CHIPLET_UCS_FIR, bit(14)) ? analyzeConnectedOMIC1; + + /** MC_CHIPLET_UCS_FIR[15] + * Attention from MCPPEFIR 2 + */ + (rMC_CHIPLET_UCS_FIR, bit(15)) ? analyzeConnectedOMIC2; + +}; + +################################################################################ +# MC Chiplet Host Attention FIR +################################################################################ + +rule rMC_CHIPLET_HA_FIR +{ + HOST_ATTN: + MC_CHIPLET_HA_FIR & ~(MC_CHIPLET_HA_FIR_MASK >> 1) & `7fffffffffffffff`; +}; + +group gMC_CHIPLET_HA_FIR attntype HOST_ATTN + filter singlebit +{ + /** MC_CHIPLET_HA_FIR[1] + * Attention from DSTLFIR 0 + */ + (rMC_CHIPLET_HA_FIR, bit(1)) ? analyzeConnectedMCC0; + + /** MC_CHIPLET_HA_FIR[2] + * Attention from USTLFIR 0 + */ + (rMC_CHIPLET_HA_FIR, bit(2)) ? analyzeConnectedMCC0; + + /** MC_CHIPLET_HA_FIR[3] + * Attention from DSTLFIR 1 + */ + (rMC_CHIPLET_HA_FIR, bit(3)) ? analyzeConnectedMCC1; + + /** MC_CHIPLET_HA_FIR[4] + * Attention from USTLFIR 1 + */ + (rMC_CHIPLET_HA_FIR, bit(4)) ? analyzeConnectedMCC1; + + /** MC_CHIPLET_HA_FIR[5] + * Attention from DSTLFIR 2 + */ + (rMC_CHIPLET_HA_FIR, bit(5)) ? analyzeConnectedMCC2; + + /** MC_CHIPLET_HA_FIR[6] + * Attention from USTLFIR 2 + */ + (rMC_CHIPLET_HA_FIR, bit(6)) ? analyzeConnectedMCC2; + + /** MC_CHIPLET_HA_FIR[7] + * Attention from DSTLFIR 3 + */ + (rMC_CHIPLET_HA_FIR, bit(7)) ? analyzeConnectedMCC3; + + /** MC_CHIPLET_HA_FIR[8] + * Attention from USTLFIR 3 + */ + (rMC_CHIPLET_HA_FIR, bit(8)) ? analyzeConnectedMCC3; + + /** MC_CHIPLET_HA_FIR[9] + * Attention from MCBISTFIR + */ + (rMC_CHIPLET_HA_FIR, bit(9)) ? analyzeMCBISTFIR; + +}; + +################################################################################ +# P9 chip MC_LFIR +################################################################################ + +rule rMC_LFIR +{ + CHECK_STOP: + MC_LFIR & ~MC_LFIR_MASK & ~MC_LFIR_ACT0 & ~MC_LFIR_ACT1; + RECOVERABLE: + MC_LFIR & ~MC_LFIR_MASK & ~MC_LFIR_ACT0 & MC_LFIR_ACT1; +}; + +group gMC_LFIR + filter singlebit, + cs_root_cause +{ + /** MC_LFIR[0] + * CFIR internal parity error + */ + (rMC_LFIR, bit(0)) ? self_th_32perDay; + + /** MC_LFIR[1] + * Chiplet Control Reg: PCB Access Error + */ + (rMC_LFIR, bit(1)) ? self_th_32perDay; + + /** MC_LFIR[2] + * Clock Controller: PCB Access Error + */ + (rMC_LFIR, bit(2)) ? self_th_32perDay; + + /** MC_LFIR[3] + * Clock Controller: Summarized Error + */ + (rMC_LFIR, bit(3)) ? self_th_32perDay; + + /** MC_LFIR[4] + * PSCOM Logic: PCB Access Error + */ + (rMC_LFIR, bit(4)) ? defaultMaskedError; + + /** MC_LFIR[5] + * PSCOM Logic: Summarized internal errors + */ + (rMC_LFIR, bit(5)) ? defaultMaskedError; + + /** MC_LFIR[6] + * Therm Logic: Summarized internal errors + */ + (rMC_LFIR, bit(6)) ? defaultMaskedError; + + /** MC_LFIR[7] + * Therm Logic: PCB Access Error + */ + (rMC_LFIR, bit(7)) ? defaultMaskedError; + + /** MC_LFIR[8] + * Therm Logic: Temperature critical trip + */ + (rMC_LFIR, bit(8)) ? defaultMaskedError; + + /** MC_LFIR[9] + * Therm Logic: Temperature fatal trip + */ + (rMC_LFIR, bit(9)) ? defaultMaskedError; + + /** MC_LFIR[10] + * UNUSED in P9 + */ + (rMC_LFIR, bit(10)) ? defaultMaskedError; + + /** MC_LFIR[11] + * Debug Logic: Scom Satellite Error + */ + (rMC_LFIR, bit(11)) ? defaultMaskedError; + + /** MC_LFIR[12] + * Scom Satellite Error - Trace0 + */ + (rMC_LFIR, bit(12)) ? defaultMaskedError; + + /** MC_LFIR[13] + * Scom Satellite Error - Trace0 + */ + (rMC_LFIR, bit(13)) ? defaultMaskedError; + + /** MC_LFIR[14] + * Scom Satellite Error - Trace1 + */ + (rMC_LFIR, bit(14)) ? defaultMaskedError; + + /** MC_LFIR[15] + * Scom Satellite Error - Trace1 + */ + (rMC_LFIR, bit(15)) ? defaultMaskedError; + + /** MC_LFIR[16:40] + * spare + */ + (rMC_LFIR, bit(16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError; + + /** MC_LFIR[41] + * Malfunction Alert or Local Checkstop + */ + (rMC_LFIR, bit(41)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 MC target MCBISTFIR +################################################################################ + +rule rMCBISTFIR +{ + CHECK_STOP: + MCBISTFIR & ~MCBISTFIR_MASK & ~MCBISTFIR_ACT0 & ~MCBISTFIR_ACT1; + RECOVERABLE: + MCBISTFIR & ~MCBISTFIR_MASK & ~MCBISTFIR_ACT0 & MCBISTFIR_ACT1; + HOST_ATTN: + MCBISTFIR & ~MCBISTFIR_MASK & MCBISTFIR_ACT0 & ~MCBISTFIR_ACT1; + UNIT_CS: + MCBISTFIR & ~MCBISTFIR_MASK & MCBISTFIR_ACT0 & MCBISTFIR_ACT1; +}; + +group gMCBISTFIR + filter singlebit, + cs_root_cause +{ + /** MCBISTFIR[0] + * WAT debug bus attn + */ + (rMCBISTFIR, bit(0)) ? defaultMaskedError; + + /** MCBISTFIR[1] + * WAT debug register parity error + */ + (rMCBISTFIR, bit(1)) ? defaultMaskedError; + + /** MCBISTFIR[2] + * SCOM recoverable register parity error + */ + (rMCBISTFIR, bit(2)) ? defaultMaskedError; + + /** MCBISTFIR[3] + * Spare + */ + (rMCBISTFIR, bit(3)) ? defaultMaskedError; + + /** MCBISTFIR[4] + * Chan 0A application interrupt + */ + (rMCBISTFIR, bit(4)) ? defaultMaskedError; + + /** MCBISTFIR[5] + * Chan 0B application interrupt + */ + (rMCBISTFIR, bit(5)) ? defaultMaskedError; + + /** MCBISTFIR[6] + * Chan 1A application interrupt + */ + (rMCBISTFIR, bit(6)) ? defaultMaskedError; + + /** MCBISTFIR[7] + * Chan 1B application interrupt + */ + (rMCBISTFIR, bit(7)) ? defaultMaskedError; + + /** MCBISTFIR[8] + * Chan 2A application interrupt + */ + (rMCBISTFIR, bit(8)) ? defaultMaskedError; + + /** MCBISTFIR[9] + * Chan 2B application interrupt + */ + (rMCBISTFIR, bit(9)) ? defaultMaskedError; + + /** MCBISTFIR[10] + * Chan 3A application interrupt + */ + (rMCBISTFIR, bit(10)) ? defaultMaskedError; + + /** MCBISTFIR[11] + * Chan 3B application interrupt + */ + (rMCBISTFIR, bit(11)) ? defaultMaskedError; + + /** MCBISTFIR[12] + * Internal SCOM error + */ + (rMCBISTFIR, bit(12)) ? defaultMaskedError; + + /** MCBISTFIR[13] + * Internal SCOM error clone + */ + (rMCBISTFIR, bit(13)) ? defaultMaskedError; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "axone_mc_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mc_actions.rule b/src/usr/diag/prdf/common/plat/axone/axone_mc_actions.rule new file mode 100644 index 000000000..aab2297ef --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_mc_actions.rule @@ -0,0 +1,45 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_mc_actions.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2017,2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +############################################################################### +# Analyze groups +############################################################################### + +actionclass analyzeMC_LFIR { analyze(gMC_LFIR); }; +actionclass analyzeMCBISTFIR { analyze(gMCBISTFIR); }; + +############################################################################### +# Analyze connected +############################################################################### + +actionclass analyzeConnectedMCC0 { analyze(connected(TYPE_MCC, 0)); }; +actionclass analyzeConnectedMCC1 { analyze(connected(TYPE_MCC, 1)); }; +actionclass analyzeConnectedMCC2 { analyze(connected(TYPE_MCC, 2)); }; +actionclass analyzeConnectedMCC3 { analyze(connected(TYPE_MCC, 3)); }; + +actionclass analyzeConnectedOMIC0 { analyze(connected(TYPE_OMIC, 0)); }; +actionclass analyzeConnectedOMIC1 { analyze(connected(TYPE_OMIC, 1)); }; +actionclass analyzeConnectedOMIC2 { analyze(connected(TYPE_OMIC, 2)); }; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mcc.rule b/src/usr/diag/prdf/common/plat/axone/axone_mcc.rule new file mode 100644 index 000000000..bf632abbb --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_mcc.rule @@ -0,0 +1,658 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_mcc.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_mcc +{ + name "AXONE MCC target"; + targettype TYPE_MCC; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # P9 MCC target DSTLFIR + ############################################################################ + + register DSTLFIR + { + name "P9 MCC target DSTLFIR"; + scomaddr 0x07010900; + reset (&, 0x07010901); + mask (|, 0x07010905); + capture group default; + }; + + register DSTLFIR_MASK + { + name "P9 MCC target DSTLFIR MASK"; + scomaddr 0x07010903; + capture group default; + }; + + register DSTLFIR_ACT0 + { + name "P9 MCC target DSTLFIR ACT0"; + scomaddr 0x07010906; + capture group default; + capture req nonzero("DSTLFIR"); + }; + + register DSTLFIR_ACT1 + { + name "P9 MCC target DSTLFIR ACT1"; + scomaddr 0x07010907; + capture group default; + capture req nonzero("DSTLFIR"); + }; + + ############################################################################ + # P9 MCC target USTLFIR + ############################################################################ + + register USTLFIR + { + name "P9 MCC target USTLFIR"; + scomaddr 0x07010a00; + reset (&, 0x07010a01); + mask (|, 0x07010a05); + capture group default; + }; + + register USTLFIR_MASK + { + name "P9 MCC target USTLFIR MASK"; + scomaddr 0x07010a03; + capture group default; + }; + + register USTLFIR_ACT0 + { + name "P9 MCC target USTLFIR ACT0"; + scomaddr 0x07010a06; + capture group default; + capture req nonzero("USTLFIR"); + }; + + register USTLFIR_ACT1 + { + name "P9 MCC target USTLFIR ACT1"; + scomaddr 0x07010a07; + capture group default; + capture req nonzero("USTLFIR"); + }; + +# Include registers not defined by the xml +.include "axone_mcc_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Summary for MCC +################################################################################ + +rule rMCC +{ + CHECK_STOP: + summary( 0, rDSTLFIR ) | + summary( 1, rUSTLFIR ); + + RECOVERABLE: + summary( 0, rDSTLFIR ) | + summary( 1, rUSTLFIR ); + + UNIT_CS: + summary( 0, rDSTLFIR ) | + summary( 1, rUSTLFIR ); + + HOST_ATTN: + summary( 0, rDSTLFIR ) | + summary( 1, rUSTLFIR ); + +}; + +group gMCC attntype CHECK_STOP, RECOVERABLE, UNIT_CS, HOST_ATTN + filter singlebit +{ + (rMCC, bit(0)) ? analyzeDSTLFIR; + (rMCC, bit(1)) ? analyzeUSTLFIR; +}; + +################################################################################ +# P9 MCC target DSTLFIR +################################################################################ + +rule rDSTLFIR +{ + CHECK_STOP: + DSTLFIR & ~DSTLFIR_MASK & ~DSTLFIR_ACT0 & ~DSTLFIR_ACT1; + RECOVERABLE: + DSTLFIR & ~DSTLFIR_MASK & ~DSTLFIR_ACT0 & DSTLFIR_ACT1; + HOST_ATTN: + DSTLFIR & ~DSTLFIR_MASK & DSTLFIR_ACT0 & ~DSTLFIR_ACT1; + UNIT_CS: + DSTLFIR & ~DSTLFIR_MASK & DSTLFIR_ACT0 & DSTLFIR_ACT1; +}; + +group gDSTLFIR + filter singlebit, + cs_root_cause +{ + /** DSTLFIR[0] + * AFU initiated Checkstop on Subchannel A + */ + (rDSTLFIR, bit(0)) ? defaultMaskedError; + + /** DSTLFIR[1] + * AFU initiated Recoverable Attn on Subchannel A + */ + (rDSTLFIR, bit(1)) ? defaultMaskedError; + + /** DSTLFIR[2] + * AFU initiated Special Attn on Subchannel A + */ + (rDSTLFIR, bit(2)) ? defaultMaskedError; + + /** DSTLFIR[3] + * AFU initiated Application Interrupt Attn on Subchannel A + */ + (rDSTLFIR, bit(3)) ? defaultMaskedError; + + /** DSTLFIR[4] + * AFU initiated Checkstop on Subchannel B + */ + (rDSTLFIR, bit(4)) ? defaultMaskedError; + + /** DSTLFIR[5] + * AFU initiated Recoverable Attn on Subchannel B + */ + (rDSTLFIR, bit(5)) ? defaultMaskedError; + + /** DSTLFIR[6] + * AFU initiated Special Attn on Subchannel B + */ + (rDSTLFIR, bit(6)) ? defaultMaskedError; + + /** DSTLFIR[7] + * AFU initiated Application Interrupt Attn on Subchannel B + */ + (rDSTLFIR, bit(7)) ? defaultMaskedError; + + /** DSTLFIR[8] + * Async crossing parity error + */ + (rDSTLFIR, bit(8)) ? defaultMaskedError; + + /** DSTLFIR[9] + * Async crossing sequence error + */ + (rDSTLFIR, bit(9)) ? defaultMaskedError; + + /** DSTLFIR[10] + * Config reg recoverable parity error + */ + (rDSTLFIR, bit(10)) ? defaultMaskedError; + + /** DSTLFIR[11] + * Config reg fatal parity error + */ + (rDSTLFIR, bit(11)) ? defaultMaskedError; + + /** DSTLFIR[12] + * Subchannel A counter error + */ + (rDSTLFIR, bit(12)) ? defaultMaskedError; + + /** DSTLFIR[13] + * Subchannel B counter error + */ + (rDSTLFIR, bit(13)) ? defaultMaskedError; + + /** DSTLFIR[14] + * Subchannel A timeout error + */ + (rDSTLFIR, bit(14)) ? defaultMaskedError; + + /** DSTLFIR[15] + * Subchannel B timeout error + */ + (rDSTLFIR, bit(15)) ? defaultMaskedError; + + /** DSTLFIR[16] + * Subchannel A buffer overuse error + */ + (rDSTLFIR, bit(16)) ? defaultMaskedError; + + /** DSTLFIR[17] + * Subchannel B buffer overuse error + */ + (rDSTLFIR, bit(17)) ? defaultMaskedError; + + /** DSTLFIR[18] + * Subchannel A DL link down + */ + (rDSTLFIR, bit(18)) ? defaultMaskedError; + + /** DSTLFIR[19] + * Subchannel B DL link down + */ + (rDSTLFIR, bit(19)) ? defaultMaskedError; + + /** DSTLFIR[20] + * Subchannel A fail action + */ + (rDSTLFIR, bit(20)) ? defaultMaskedError; + + /** DSTLFIR[21] + * Subchannel B fail action + */ + (rDSTLFIR, bit(21)) ? defaultMaskedError; + + /** DSTLFIR[22] + * Internal SCOM error + */ + (rDSTLFIR, bit(22)) ? defaultMaskedError; + + /** DSTLFIR[23] + * Internal SCOM error clone + */ + (rDSTLFIR, bit(23)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 MCC target USTLFIR +################################################################################ + +rule rUSTLFIR +{ + CHECK_STOP: + USTLFIR & ~USTLFIR_MASK & ~USTLFIR_ACT0 & ~USTLFIR_ACT1; + RECOVERABLE: + USTLFIR & ~USTLFIR_MASK & ~USTLFIR_ACT0 & USTLFIR_ACT1; + HOST_ATTN: + USTLFIR & ~USTLFIR_MASK & USTLFIR_ACT0 & ~USTLFIR_ACT1; + UNIT_CS: + USTLFIR & ~USTLFIR_MASK & USTLFIR_ACT0 & USTLFIR_ACT1; +}; + +group gUSTLFIR + filter singlebit, + cs_root_cause +{ + /** USTLFIR[0] + * Chan A unexpected data error + */ + (rUSTLFIR, bit(0)) ? defaultMaskedError; + + /** USTLFIR[1] + * Chan B unexpected data error + */ + (rUSTLFIR, bit(1)) ? defaultMaskedError; + + /** USTLFIR[2] + * Chan A invalid template error + */ + (rUSTLFIR, bit(2)) ? defaultMaskedError; + + /** USTLFIR[3] + * Chan B invalid template error + */ + (rUSTLFIR, bit(3)) ? defaultMaskedError; + + /** USTLFIR[4] + * Chan A half speed mode + */ + (rUSTLFIR, bit(4)) ? defaultMaskedError; + + /** USTLFIR[5] + * Chan B half speed mode + */ + (rUSTLFIR, bit(5)) ? defaultMaskedError; + + /** USTLFIR[6] + * WDF buffer CE + */ + (rUSTLFIR, bit(6)) ? defaultMaskedError; + + /** USTLFIR[7] + * WDF buffer UE + */ + (rUSTLFIR, bit(7)) ? defaultMaskedError; + + /** USTLFIR[8] + * WDF buffer SUE + */ + (rUSTLFIR, bit(8)) ? defaultMaskedError; + + /** USTLFIR[9] + * WDF buffer overrun + */ + (rUSTLFIR, bit(9)) ? defaultMaskedError; + + /** USTLFIR[10] + * WDF tag parity error + */ + (rUSTLFIR, bit(10)) ? defaultMaskedError; + + /** USTLFIR[11] + * WDF scom sequencer error + */ + (rUSTLFIR, bit(11)) ? defaultMaskedError; + + /** USTLFIR[12] + * WDF pwctl sequencer error + */ + (rUSTLFIR, bit(12)) ? defaultMaskedError; + + /** USTLFIR[13] + * WDF misc_reg parity error + */ + (rUSTLFIR, bit(13)) ? defaultMaskedError; + + /** USTLFIR[14] + * WDF MCA async error + */ + (rUSTLFIR, bit(14)) ? defaultMaskedError; + + /** USTLFIR[15] + * WDF Data Syndrome NE0 + */ + (rUSTLFIR, bit(15)) ? defaultMaskedError; + + /** USTLFIR[16] + * WDF CMT parity error + */ + (rUSTLFIR, bit(16)) ? defaultMaskedError; + + /** USTLFIR[17] + * TBD + */ + (rUSTLFIR, bit(17)) ? defaultMaskedError; + + /** USTLFIR[18] + * TBD + */ + (rUSTLFIR, bit(18)) ? defaultMaskedError; + + /** USTLFIR[19] + * TBD + */ + (rUSTLFIR, bit(19)) ? defaultMaskedError; + + /** USTLFIR[20] + * WRT Buffer CE + */ + (rUSTLFIR, bit(20)) ? defaultMaskedError; + + /** USTLFIR[21] + * WRT Buffer UE + */ + (rUSTLFIR, bit(21)) ? defaultMaskedError; + + /** USTLFIR[22] + * WRT Buffer SUE + */ + (rUSTLFIR, bit(22)) ? defaultMaskedError; + + /** USTLFIR[23] + * WRT scom sequencer error + */ + (rUSTLFIR, bit(23)) ? defaultMaskedError; + + /** USTLFIR[24] + * WRT misc_reg parity error + */ + (rUSTLFIR, bit(24)) ? defaultMaskedError; + + /** USTLFIR[25:26] + * WRT error information spares + */ + (rUSTLFIR, bit(25|26)) ? defaultMaskedError; + + /** USTLFIR[27] + * Chan A fail response checkstop + */ + (rUSTLFIR, bit(27)) ? defaultMaskedError; + + /** USTLFIR[28] + * Chan B fail response checkstop + */ + (rUSTLFIR, bit(28)) ? defaultMaskedError; + + /** USTLFIR[29] + * Chan A fail response recoverable + */ + (rUSTLFIR, bit(29)) ? defaultMaskedError; + + /** USTLFIR[30] + * Chan B fail response recoverable + */ + (rUSTLFIR, bit(30)) ? defaultMaskedError; + + /** USTLFIR[31] + * Chan A lol drop checkstop + */ + (rUSTLFIR, bit(31)) ? defaultMaskedError; + + /** USTLFIR[32] + * Chan B lol drop checkstop + */ + (rUSTLFIR, bit(32)) ? defaultMaskedError; + + /** USTLFIR[33] + * Chan A lol drop recoverable + */ + (rUSTLFIR, bit(33)) ? defaultMaskedError; + + /** USTLFIR[34] + * Chan B lol drop recoverable + */ + (rUSTLFIR, bit(34)) ? defaultMaskedError; + + /** USTLFIR[35] + * Chan A flit parity error + */ + (rUSTLFIR, bit(35)) ? defaultMaskedError; + + /** USTLFIR[36] + * Chan B flit parity error + */ + (rUSTLFIR, bit(36)) ? defaultMaskedError; + + /** USTLFIR[37] + * Chan A fatal parity error + */ + (rUSTLFIR, bit(37)) ? defaultMaskedError; + + /** USTLFIR[38] + * Chan B fatal parity error + */ + (rUSTLFIR, bit(38)) ? defaultMaskedError; + + /** USTLFIR[39] + * Chan A more than 2 data flits for template 9 + */ + (rUSTLFIR, bit(39)) ? defaultMaskedError; + + /** USTLFIR[40] + * Chan B more than 2 data flits for template 9 + */ + (rUSTLFIR, bit(40)) ? defaultMaskedError; + + /** USTLFIR[41] + * Chan A excess bad data bits + */ + (rUSTLFIR, bit(41)) ? defaultMaskedError; + + /** USTLFIR[42] + * Chan B excess bad data bits + */ + (rUSTLFIR, bit(42)) ? defaultMaskedError; + + /** USTLFIR[43] + * Chan A memory read data returned in template 0 + */ + (rUSTLFIR, bit(43)) ? defaultMaskedError; + + /** USTLFIR[44] + * Chan B memory read data returned in template 0 + */ + (rUSTLFIR, bit(44)) ? defaultMaskedError; + + /** USTLFIR[45] + * Chan A MMIO in lol mode + */ + (rUSTLFIR, bit(45)) ? defaultMaskedError; + + /** USTLFIR[46] + * Chan B MMIO in lol mode + */ + (rUSTLFIR, bit(46)) ? defaultMaskedError; + + /** USTLFIR[47] + * Chan A bad data + */ + (rUSTLFIR, bit(47)) ? defaultMaskedError; + + /** USTLFIR[48] + * Chan B bad data + */ + (rUSTLFIR, bit(48)) ? defaultMaskedError; + + /** USTLFIR[49] + * Chan A excess data error + */ + (rUSTLFIR, bit(49)) ? defaultMaskedError; + + /** USTLFIR[50] + * Chan B excess data error + */ + (rUSTLFIR, bit(50)) ? defaultMaskedError; + + /** USTLFIR[51] + * Chan A Bad CRC data not valid error + */ + (rUSTLFIR, bit(51)) ? defaultMaskedError; + + /** USTLFIR[52] + * Chan B Bad CRC data not valid error + */ + (rUSTLFIR, bit(52)) ? defaultMaskedError; + + /** USTLFIR[53] + * Chan A FIFO overflow error + */ + (rUSTLFIR, bit(53)) ? defaultMaskedError; + + /** USTLFIR[54] + * Chan B FIFO overflow error + */ + (rUSTLFIR, bit(54)) ? defaultMaskedError; + + /** USTLFIR[55] + * Chan A invalid cmd error + */ + (rUSTLFIR, bit(55)) ? defaultMaskedError; + + /** USTLFIR[56] + * Chan B invalid cmd error + */ + (rUSTLFIR, bit(56)) ? defaultMaskedError; + + /** USTLFIR[57] + * Fatal reg parity error + */ + (rUSTLFIR, bit(57)) ? defaultMaskedError; + + /** USTLFIR[58] + * Recoverable reg parity error + */ + (rUSTLFIR, bit(58)) ? defaultMaskedError; + + /** USTLFIR[59] + * Chan A invalid DL DP combo + */ + (rUSTLFIR, bit(59)) ? defaultMaskedError; + + /** USTLFIR[60] + * Chan B invalid DL DP combo + */ + (rUSTLFIR, bit(60)) ? defaultMaskedError; + + /** USTLFIR[61] + * spare + */ + (rUSTLFIR, bit(61)) ? defaultMaskedError; + + /** USTLFIR[62] + * Internal parity error + */ + (rUSTLFIR, bit(62)) ? defaultMaskedError; + + /** USTLFIR[63] + * Internal parity error copy + */ + (rUSTLFIR, bit(63)) ? defaultMaskedError; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "axone_mcc_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mcc_actions.rule b/src/usr/diag/prdf/common/plat/axone/axone_mcc_actions.rule new file mode 100644 index 000000000..38edbaaea --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_mcc_actions.rule @@ -0,0 +1,32 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_mcc_actions.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +################################################################################ +# Analyze groups +################################################################################ + +actionclass analyzeDSTLFIR { analyze(gDSTLFIR); }; +actionclass analyzeUSTLFIR { analyze(gUSTLFIR); }; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mi.rule b/src/usr/diag/prdf/common/plat/axone/axone_mi.rule new file mode 100644 index 000000000..3acae6371 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_mi.rule @@ -0,0 +1,260 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_mi.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_mi +{ + name "AXONE MI target"; + targettype TYPE_MI; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # P9 MI target MCFIR + ############################################################################ + + register MCFIR + { + name "P9 MI target MCFIR"; + scomaddr 0x05010800; + reset (&, 0x05010801); + mask (|, 0x05010805); + capture group default; + }; + + register MCFIR_MASK + { + name "P9 MI target MCFIR MASK"; + scomaddr 0x05010803; + capture group default; + }; + + register MCFIR_ACT0 + { + name "P9 MI target MCFIR ACT0"; + scomaddr 0x05010806; + capture group default; + capture req nonzero("MCFIR"); + }; + + register MCFIR_ACT1 + { + name "P9 MI target MCFIR ACT1"; + scomaddr 0x05010807; + capture group default; + capture req nonzero("MCFIR"); + }; + +# Include registers not defined by the xml +.include "axone_mi_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Summary for MI +################################################################################ + +rule rMI +{ + CHECK_STOP: + summary( 0, rMCFIR ); + + RECOVERABLE: + summary( 0, rMCFIR ); + + UNIT_CS: + summary( 0, rMCFIR ); + + HOST_ATTN: + summary( 0, rMCFIR ); + +}; + +group gMI attntype CHECK_STOP, RECOVERABLE, UNIT_CS, HOST_ATTN + filter singlebit +{ + (rMI, bit(0)) ? analyzeMCFIR; +}; + +################################################################################ +# P9 MI target MCFIR +################################################################################ + +rule rMCFIR +{ + CHECK_STOP: + MCFIR & ~MCFIR_MASK & ~MCFIR_ACT0 & ~MCFIR_ACT1; + RECOVERABLE: + MCFIR & ~MCFIR_MASK & ~MCFIR_ACT0 & MCFIR_ACT1; + HOST_ATTN: + MCFIR & ~MCFIR_MASK & MCFIR_ACT0 & ~MCFIR_ACT1; + UNIT_CS: + MCFIR & ~MCFIR_MASK & MCFIR_ACT0 & MCFIR_ACT1; +}; + +group gMCFIR + filter singlebit, + cs_root_cause +{ + /** MCFIR[0] + * MC internal recoverable error + */ + (rMCFIR, bit(0)) ? defaultMaskedError; + + /** MCFIR[1] + * MC internal non recoverable error + */ + (rMCFIR, bit(1)) ? defaultMaskedError; + + /** MCFIR[2] + * Powerbus protocol error + */ + (rMCFIR, bit(2)) ? defaultMaskedError; + + /** MCFIR[3] + * Inband bar hit with incorrect ttype + */ + (rMCFIR, bit(3)) ? defaultMaskedError; + + /** MCFIR[4] + * Multiple bar + */ + (rMCFIR, bit(4)) ? defaultMaskedError; + + /** MCFIR[5] + * PB write ECC syndrome NE0 + */ + (rMCFIR, bit(5)) ? defaultMaskedError; + + /** MCFIR[6:7] + * reserved + */ + (rMCFIR, bit(6|7)) ? defaultMaskedError; + + /** MCFIR[8] + * Command list timeout + */ + (rMCFIR, bit(8)) ? defaultMaskedError; + + /** MCFIR[9:10] + * reserved + */ + (rMCFIR, bit(9|10)) ? defaultMaskedError; + + /** MCFIR[11] + * MCS wat0 event + */ + (rMCFIR, bit(11)) ? defaultMaskedError; + + /** MCFIR[12] + * MCS wat1 event + */ + (rMCFIR, bit(12)) ? defaultMaskedError; + + /** MCFIR[13] + * MCS wat2 event + */ + (rMCFIR, bit(13)) ? defaultMaskedError; + + /** MCFIR[14] + * MCS wat3 event + */ + (rMCFIR, bit(14)) ? defaultMaskedError; + + /** MCFIR[15:16] + * reserved + */ + (rMCFIR, bit(15|16)) ? defaultMaskedError; + + /** MCFIR[17] + * WAT debug config reg error + */ + (rMCFIR, bit(17)) ? defaultMaskedError; + + /** MCFIR[18:21] + * reserved + */ + (rMCFIR, bit(18|19|20|21)) ? defaultMaskedError; + + /** MCFIR[22] + * Invalid SMF access + */ + (rMCFIR, bit(22)) ? defaultMaskedError; + + /** MCFIR[23] + * reserved + */ + (rMCFIR, bit(23)) ? defaultMaskedError; + + /** MCFIR[24] + * Internal SCOM error + */ + (rMCFIR, bit(24)) ? defaultMaskedError; + + /** MCFIR[25] + * Internal SCOM error clone + */ + (rMCFIR, bit(25)) ? defaultMaskedError; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "axone_mi_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mi_actions.rule b/src/usr/diag/prdf/common/plat/axone/axone_mi_actions.rule new file mode 100644 index 000000000..ca2eebcf3 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_mi_actions.rule @@ -0,0 +1,31 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_mi_actions.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +################################################################################ +# Analyze groups +################################################################################ + +actionclass analyzeMCFIR { analyze(gMCFIR); }; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_mi_regs.rule b/src/usr/diag/prdf/common/plat/axone/axone_mi_regs.rule new file mode 100644 index 000000000..7793c661f --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_mi_regs.rule @@ -0,0 +1,63 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_mi_regs.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + + ############################################################################ + # Additional regs for P9 MI target MCFIR + ############################################################################ + + register MCERPT0 + { + name "MCERPT0"; + scomaddr 0x0501081E; + capture group default; + }; + + register MCERPT1 + { + name "MCERPT1"; + scomaddr 0x0501081F; + capture group default; + }; + + register MCERPT2 + { + name "MCERPT2"; + scomaddr 0x0501081A; + capture group default; + }; + + register MCFGP + { + name "MCFGP"; + scomaddr 0x501080A; + capture group default; + }; + + register MCFGPM + { + name "MCFGPM"; + scomaddr 0x501080C; + capture group default; + }; diff --git a/src/usr/diag/prdf/common/plat/axone/axone_npu.rule b/src/usr/diag/prdf/common/plat/axone/axone_npu.rule new file mode 100644 index 000000000..ede5ef5cc --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_npu.rule @@ -0,0 +1,1105 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_npu.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_npu +{ + name "AXONE NPU target"; + targettype TYPE_NPU; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # P9 NPU target NPU0FIR + ############################################################################ + + register NPU0FIR + { + name "P9 NPU target NPU0FIR"; + scomaddr 0x05013c00; + reset (&, 0x05013c01); + mask (|, 0x05013c05); + capture group npu0fir_ffdc; + }; + + register NPU0FIR_MASK + { + name "P9 NPU target NPU0FIR MASK"; + scomaddr 0x05013c03; + capture group npu0fir_ffdc; + }; + + register NPU0FIR_ACT0 + { + name "P9 NPU target NPU0FIR ACT0"; + scomaddr 0x05013c06; + capture group npu0fir_ffdc; + capture req nonzero("NPU0FIR"); + }; + + register NPU0FIR_ACT1 + { + name "P9 NPU target NPU0FIR ACT1"; + scomaddr 0x05013c07; + capture group npu0fir_ffdc; + capture req nonzero("NPU0FIR"); + }; + + ############################################################################ + # P9 NPU target NPU1FIR + ############################################################################ + + register NPU1FIR + { + name "P9 NPU target NPU1FIR"; + scomaddr 0x05013c40; + reset (&, 0x05013c41); + mask (|, 0x05013c45); + capture group npu1fir_ffdc; + }; + + register NPU1FIR_MASK + { + name "P9 NPU target NPU1FIR MASK"; + scomaddr 0x05013c43; + capture group npu1fir_ffdc; + }; + + register NPU1FIR_ACT0 + { + name "P9 NPU target NPU1FIR ACT0"; + scomaddr 0x05013c46; + capture group npu1fir_ffdc; + capture req nonzero("NPU1FIR"); + }; + + register NPU1FIR_ACT1 + { + name "P9 NPU target NPU1FIR ACT1"; + scomaddr 0x05013c47; + capture group npu1fir_ffdc; + capture req nonzero("NPU1FIR"); + }; + + ############################################################################ + # P9 NPU target NPU2FIR + ############################################################################ + + register NPU2FIR + { + name "P9 NPU target NPU2FIR"; + scomaddr 0x05013c80; + reset (&, 0x05013c81); + mask (|, 0x05013c85); + capture group npu2fir_ffdc; + }; + + register NPU2FIR_MASK + { + name "P9 NPU target NPU2FIR MASK"; + scomaddr 0x05013c83; + capture group npu2fir_ffdc; + }; + + register NPU2FIR_ACT0 + { + name "P9 NPU target NPU2FIR ACT0"; + scomaddr 0x05013c86; + capture group npu2fir_ffdc; + capture req nonzero("NPU2FIR"); + }; + + register NPU2FIR_ACT1 + { + name "P9 NPU target NPU2FIR ACT1"; + scomaddr 0x05013c87; + capture group npu2fir_ffdc; + capture req nonzero("NPU2FIR"); + }; + +# Include registers not defined by the xml +.include "p9_common_npu_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Summary for NPU +################################################################################ + +rule rNPU +{ + CHECK_STOP: + summary( 0, rNPU0FIR ) | + summary( 1, rNPU1FIR ) | + summary( 2, rNPU2FIR ); + + RECOVERABLE: + summary( 0, rNPU0FIR ) | + summary( 1, rNPU1FIR ) | + summary( 2, rNPU2FIR ); + + UNIT_CS: + summary( 0, rNPU0FIR ) | + summary( 1, rNPU1FIR ) | + summary( 2, rNPU2FIR ); + +}; + +group gNPU attntype CHECK_STOP, RECOVERABLE, UNIT_CS + filter singlebit +{ + (rNPU, bit(0)) ? analyzeNPU0FIR; + (rNPU, bit(1)) ? analyzeNPU1FIR; + (rNPU, bit(2)) ? analyzeNPU2FIR; +}; + +################################################################################ +# P9 NPU target NPU0FIR +################################################################################ + +rule rNPU0FIR +{ + CHECK_STOP: + NPU0FIR & ~NPU0FIR_MASK & ~NPU0FIR_ACT0 & ~NPU0FIR_ACT1; + RECOVERABLE: + NPU0FIR & ~NPU0FIR_MASK & ~NPU0FIR_ACT0 & NPU0FIR_ACT1; + UNIT_CS: + NPU0FIR & ~NPU0FIR_MASK & NPU0FIR_ACT0 & NPU0FIR_ACT1; +}; + +group gNPU0FIR + filter singlebit, + cs_root_cause(1,2,3,4,5,6,7,9,10,16,18,29,31,42,44) +{ + /** NPU0FIR[0] + * NTL array CE + */ + (rNPU0FIR, bit(0)) ? self_th_32perDay; + + /** NPU0FIR[1] + * NTL header array UE + */ + (rNPU0FIR, bit(1)) ? self_th_1; + + /** NPU0FIR[2] + * NTL Data Array UE + */ + (rNPU0FIR, bit(2)) ? self_th_1; + + /** NPU0FIR[3] + * NTL NVLInk Control/Header/AE PE + */ + (rNPU0FIR, bit(3)) ? self_th_1; + + /** NPU0FIR[4] + * NTL NVLink Data Parity error + */ + (rNPU0FIR, bit(4)) ? self_th_1; + + /** NPU0FIR[5] + * NTL NVLink Malformed Packet + */ + (rNPU0FIR, bit(5)) ? self_th_1; + + /** NPU0FIR[6] + * NTL NVLink Unsupported Packet + */ + (rNPU0FIR, bit(6)) ? self_th_1; + + /** NPU0FIR[7] + * NTL NVLink Config errors + */ + (rNPU0FIR, bit(7)) ? self_th_1; + + /** NPU0FIR[8] + * NTL NVLink CRC errors or LMD=Stomp + */ + (rNPU0FIR, bit(8)) ? defaultMaskedError; + + /** NPU0FIR[9] + * NTL PRI errors + */ + (rNPU0FIR, bit(9)) ? self_th_1; + + /** NPU0FIR[10] + * NTL logic error + */ + (rNPU0FIR, bit(10)) ? self_th_1; + + /** NPU0FIR[11] + * NTL LMD=Data Posion + */ + (rNPU0FIR, bit(11)) ? defaultMaskedError; + + /** NPU0FIR[12] + * NTL data array SUE + */ + (rNPU0FIR, bit(12)) ? defaultMaskedError; + + /** NPU0FIR[13] + * CQ CTL/SM ASBE Array single-bit CE + */ + (rNPU0FIR, bit(13)) ? self_th_32perDay; + + /** NPU0FIR[14] + * CQ CTL/SM PBR PowerBus Recoverable err + */ + (rNPU0FIR, bit(14)) ? defaultMaskedError; + + /** NPU0FIR[15] + * CQ CTL/SM REG Register ring error + */ + (rNPU0FIR, bit(15)) ? self_th_32perDay; + + /** NPU0FIR[16] + * Data UE for MMIO store data + */ + (rNPU0FIR, bit(16)) ? self_th_1; + + /** NPU0FIR[17] + * spare + */ + (rNPU0FIR, bit(17)) ? defaultMaskedError; + + /** NPU0FIR[18] + * CQ CTL/SM NCF NVLink config error + */ + (rNPU0FIR, bit(18)) ? self_th_1; + + /** NPU0FIR[19] + * CQ CTL/SM NVF NVLink fatal error + */ + (rNPU0FIR, bit(19)) ? self_th_1; + + /** NPU0FIR[20] + * spare + */ + (rNPU0FIR, bit(20)) ? defaultMaskedError; + + /** NPU0FIR[21] + * CQ CTL/SM AUE Array UE + */ + (rNPU0FIR, bit(21)) ? self_th_1; + + /** NPU0FIR[22] + * CQ CTL/SM PBP PowerBus parity error + */ + (rNPU0FIR, bit(22)) ? self_th_1; + + /** NPU0FIR[23] + * CQ CTL/SM PBF PowerBus Fatal Error + */ + (rNPU0FIR, bit(23)) ? self_M_level2_L_th_1; + + /** NPU0FIR[24] + * PowerBus configuration error + */ + (rNPU0FIR, bit(24)) ? level2_M_self_L_th_1; + + /** NPU0FIR[25] + * CQ CTL/SM FWD Forward-Progress error + */ + (rNPU0FIR, bit(25)) ? self_th_1; + + /** NPU0FIR[26] + * CQ CTL/SM NLG NPU Logic error + */ + (rNPU0FIR, bit(26)) ? self_th_1; + + /** NPU0FIR[27] + * Invalid access to secure memory attempted + */ + (rNPU0FIR, bit(27)) ? defaultMaskedError; + + /** NPU0FIR[28] + * spare + */ + (rNPU0FIR, bit(28)) ? defaultMaskedError; + + /** NPU0FIR[29] + * CQ DAT ECC UE/SUE on data/BE arrays + */ + (rNPU0FIR, bit(29)) ? self_th_1; + + /** NPU0FIR[30] + * CQ DAT ECC CE on data/BE arrays + */ + (rNPU0FIR, bit(30)) ? self_M_level2_L_th_32perDay; + + /** NPU0FIR[31] + * CQ DAT parity error on data/BE latches + */ + (rNPU0FIR, bit(31)) ? self_th_1; + + /** NPU0FIR[32] + * CQ DAT parity errs on config regs + */ + (rNPU0FIR, bit(32)) ? self_th_1; + + /** NPU0FIR[33] + * CQ DAT parity errs/PowerBus rtag + */ + (rNPU0FIR, bit(33)) ? self_th_1; + + /** NPU0FIR[34] + * CQ DAT parity errs nternal state latches + */ + (rNPU0FIR, bit(34)) ? self_th_1; + + /** NPU0FIR[35] + * CQ DAT logic error + */ + (rNPU0FIR, bit(35)) ? self_th_1; + + /** NPU0FIR[36] + * Future SUE + */ + (rNPU0FIR, bit(36)) ? defaultMaskedError; + + /** NPU0FIR[37] + * ECC SUE on PB received data + */ + (rNPU0FIR, bit(37)) ? defaultMaskedError; + + /** NPU0FIR[38:39] + * spare + */ + (rNPU0FIR, bit(38|39)) ? defaultMaskedError; + + /** NPU0FIR[40] + * XTS internal logic error + */ + (rNPU0FIR, bit(40)) ? self_th_1; + + /** NPU0FIR[41] + * XTS correctable errs in XTS SRAM + */ + (rNPU0FIR, bit(41)) ? self_M_level2_L_th_32perDay; + + /** NPU0FIR[42] + * XTS Ues in XTS internal SRAM + */ + (rNPU0FIR, bit(42)) ? self_th_1; + + /** NPU0FIR[43] + * XTS CE on incoming stack transactions + */ + (rNPU0FIR, bit(43)) ? self_M_level2_L_th_32perDay; + + /** NPU0FIR[44] + * XTS errs incoming stack transaction + */ + (rNPU0FIR, bit(44)) ? self_th_1; + + /** NPU0FIR[45] + * XTS errs on incoming PBUS transaction + */ + (rNPU0FIR, bit(45)) ? self_th_1; + + /** NPU0FIR[46] + * XTS Translate Request Fail + */ + (rNPU0FIR, bit(46)) ? defaultMaskedError; + + /** NPU0FIR[47:59] + * spare + */ + (rNPU0FIR, bit(47|48|49|50|51|52|53|54|55|56|57|58|59)) ? defaultMaskedError; + + /** NPU0FIR[60] + * MISC Pervasive SCOM satellite err + */ + (rNPU0FIR, bit(60)) ? defaultMaskedError; + + /** NPU0FIR[61] + * MISC Pervasive SCOM satellite err + */ + (rNPU0FIR, bit(61)) ? defaultMaskedError; + + /** NPU0FIR[62] + * Local FIR Parity Error RAS duplicate + */ + (rNPU0FIR, bit(62)) ? defaultMaskedError; + + /** NPU0FIR[63] + * Local FIR Parity Err + */ + (rNPU0FIR, bit(63)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 NPU target NPU1FIR +################################################################################ + +rule rNPU1FIR +{ + CHECK_STOP: + NPU1FIR & ~NPU1FIR_MASK & ~NPU1FIR_ACT0 & ~NPU1FIR_ACT1; + RECOVERABLE: + NPU1FIR & ~NPU1FIR_MASK & ~NPU1FIR_ACT0 & NPU1FIR_ACT1; + UNIT_CS: + NPU1FIR & ~NPU1FIR_MASK & NPU1FIR_ACT0 & NPU1FIR_ACT1; +}; + +group gNPU1FIR + filter singlebit, + cs_root_cause +{ + /** NPU1FIR[0] + * NDL Brick0 stall + */ + (rNPU1FIR, bit(0)) ? defaultMaskedError; + + /** NPU1FIR[1] + * NDL Brick0 nostall + */ + (rNPU1FIR, bit(1)) ? defaultMaskedError; + + /** NPU1FIR[2] + * NDL Brick1 stall + */ + (rNPU1FIR, bit(2)) ? defaultMaskedError; + + /** NPU1FIR[3] + * NDL Brick1 nostall + */ + (rNPU1FIR, bit(3)) ? defaultMaskedError; + + /** NPU1FIR[4] + * NDL Brick2 stall + */ + (rNPU1FIR, bit(4)) ? defaultMaskedError; + + /** NPU1FIR[5] + * NDL Brick2 nostall + */ + (rNPU1FIR, bit(5)) ? defaultMaskedError; + + /** NPU1FIR[6] + * NDL Brick3 stall + */ + (rNPU1FIR, bit(6)) ? defaultMaskedError; + + /** NPU1FIR[7] + * NDL Brick3 nostall + */ + (rNPU1FIR, bit(7)) ? defaultMaskedError; + + /** NPU1FIR[8] + * NDL Brick4 stall + */ + (rNPU1FIR, bit(8)) ? defaultMaskedError; + + /** NPU1FIR[9] + * NDL Brick4 nostall + */ + (rNPU1FIR, bit(9)) ? defaultMaskedError; + + /** NPU1FIR[10] + * NDL Brick5 stall + */ + (rNPU1FIR, bit(10)) ? defaultMaskedError; + + /** NPU1FIR[11] + * NDL Brick5 nostall + */ + (rNPU1FIR, bit(11)) ? defaultMaskedError; + + /** NPU1FIR[12] + * MISC Register ring error (ie noack) + */ + (rNPU1FIR, bit(12)) ? defaultMaskedError; + + /** NPU1FIR[13] + * MISC Parity error from ibr addr regi + */ + (rNPU1FIR, bit(13)) ? defaultMaskedError; + + /** NPU1FIR[14] + * MISC Parity error on SCOM D/A addr reg + */ + (rNPU1FIR, bit(14)) ? defaultMaskedError; + + /** NPU1FIR[15] + * MISC Parity error on MISC Cntrl reg + */ + (rNPU1FIR, bit(15)) ? defaultMaskedError; + + /** NPU1FIR[16] + * Reserved + */ + (rNPU1FIR, bit(16)) ? defaultMaskedError; + + /** NPU1FIR[17] + * ATS Invalid TVT entry + */ + (rNPU1FIR, bit(17)) ? defaultMaskedError; + + /** NPU1FIR[18] + * ATS TVT Address range error + */ + (rNPU1FIR, bit(18)) ? defaultMaskedError; + + /** NPU1FIR[19] + * ATS TCE Page access error + */ + (rNPU1FIR, bit(19)) ? defaultMaskedError; + + /** NPU1FIR[20] + * ATS Effective Address hit multiple TCE + */ + (rNPU1FIR, bit(20)) ? defaultMaskedError; + + /** NPU1FIR[21] + * ATS TCE Page access error + */ + (rNPU1FIR, bit(21)) ? defaultMaskedError; + + /** NPU1FIR[22] + * ATS Timeout on TCE tree walk + */ + (rNPU1FIR, bit(22)) ? defaultMaskedError; + + /** NPU1FIR[23] + * ATS Parity error on TCE cache dir array + */ + (rNPU1FIR, bit(23)) ? defaultMaskedError; + + /** NPU1FIR[24] + * ATS Parity error on TCE cache data array + */ + (rNPU1FIR, bit(24)) ? defaultMaskedError; + + /** NPU1FIR[25] + * ATS ECC UE on Effective Address array + */ + (rNPU1FIR, bit(25)) ? defaultMaskedError; + + /** NPU1FIR[26] + * ATS ECC CE on Effective Address array + */ + (rNPU1FIR, bit(26)) ? defaultMaskedError; + + /** NPU1FIR[27] + * ATS ECC UE on TDRmem array + */ + (rNPU1FIR, bit(27)) ? defaultMaskedError; + + /** NPU1FIR[28] + * ATS ECC CE on TDRmem array + */ + (rNPU1FIR, bit(28)) ? defaultMaskedError; + + /** NPU1FIR[29] + * ATS ECC UE on CQ CTL DMA Read + */ + (rNPU1FIR, bit(29)) ? defaultMaskedError; + + /** NPU1FIR[30] + * ATS ECC CE on CQ CTL DMA Read + */ + (rNPU1FIR, bit(30)) ? defaultMaskedError; + + /** NPU1FIR[31] + * ATS Parity error on TVT entry + */ + (rNPU1FIR, bit(31)) ? defaultMaskedError; + + /** NPU1FIR[32] + * ATS Parity err on IODA Address Reg + */ + (rNPU1FIR, bit(32)) ? defaultMaskedError; + + /** NPU1FIR[33] + * ATS Parity error on ATS Control Register + */ + (rNPU1FIR, bit(33)) ? defaultMaskedError; + + /** NPU1FIR[34] + * ATS Parity error on ATS Timeout Control Register + */ + (rNPU1FIR, bit(34)) ? defaultMaskedError; + + /** NPU1FIR[35] + * ATS Invalid IODA Table Select entry + */ + (rNPU1FIR, bit(35)) ? defaultMaskedError; + + /** NPU1FIR[36] + * Reserved + */ + (rNPU1FIR, bit(36)) ? defaultMaskedError; + + /** NPU1FIR[37] + * Kill xlate epoch timeout + */ + (rNPU1FIR, bit(37)) ? defaultMaskedError; + + /** NPU1FIR[38] + * PEE secure SMF not secure + */ + (rNPU1FIR, bit(38)) ? defaultMaskedError; + + /** NPU1FIR[39] + * XSL in suspend mode when OTL sends cmd + */ + (rNPU1FIR, bit(39)) ? defaultMaskedError; + + /** NPU1FIR[40:46] + * Reserved + */ + (rNPU1FIR, bit(40|41|42|43|44|45|46)) ? defaultMaskedError; + + /** NPU1FIR[47] + * NDL Brick6 stall + */ + (rNPU1FIR, bit(47)) ? defaultMaskedError; + + /** NPU1FIR[48] + * NDL Brick6 nostall + */ + (rNPU1FIR, bit(48)) ? defaultMaskedError; + + /** NPU1FIR[49] + * NDL Brick7 stall + */ + (rNPU1FIR, bit(49)) ? defaultMaskedError; + + /** NPU1FIR[50] + * NDL Brick7 nostall + */ + (rNPU1FIR, bit(50)) ? defaultMaskedError; + + /** NPU1FIR[51] + * NDL Brick8 stall + */ + (rNPU1FIR, bit(51)) ? defaultMaskedError; + + /** NPU1FIR[52] + * NDL Brick8 nostall + */ + (rNPU1FIR, bit(52)) ? defaultMaskedError; + + /** NPU1FIR[53] + * NDL Brick9 stall + */ + (rNPU1FIR, bit(53)) ? defaultMaskedError; + + /** NPU1FIR[54] + * NDL Brick9 nostall + */ + (rNPU1FIR, bit(54)) ? defaultMaskedError; + + /** NPU1FIR[55] + * NDL Brick10 stall + */ + (rNPU1FIR, bit(55)) ? defaultMaskedError; + + /** NPU1FIR[56] + * NDL Brick10 nostall + */ + (rNPU1FIR, bit(56)) ? defaultMaskedError; + + /** NPU1FIR[57] + * NDL Brick11 stall + */ + (rNPU1FIR, bit(57)) ? defaultMaskedError; + + /** NPU1FIR[58] + * NDL Brick11 nostall + */ + (rNPU1FIR, bit(58)) ? defaultMaskedError; + + /** NPU1FIR[59] + * Reserved + */ + (rNPU1FIR, bit(59)) ? defaultMaskedError; + + /** NPU1FIR[60] + * MISC SCOM ring 0 sat 0 signaled internal FSM err + */ + (rNPU1FIR, bit(60)) ? defaultMaskedError; + + /** NPU1FIR[61] + * MISC SCOM ring 0 sat 1 signaled internal FSM err + */ + (rNPU1FIR, bit(61)) ? defaultMaskedError; + + /** NPU1FIR[62] + * Scom Error + */ + (rNPU1FIR, bit(62)) ? defaultMaskedError; + + /** NPU1FIR[63] + * Scom Error + */ + (rNPU1FIR, bit(63)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 NPU target NPU2FIR +################################################################################ + +rule rNPU2FIR +{ + CHECK_STOP: + NPU2FIR & ~NPU2FIR_MASK & ~NPU2FIR_ACT0 & ~NPU2FIR_ACT1; + RECOVERABLE: + NPU2FIR & ~NPU2FIR_MASK & ~NPU2FIR_ACT0 & NPU2FIR_ACT1; + UNIT_CS: + NPU2FIR & ~NPU2FIR_MASK & NPU2FIR_ACT0 & NPU2FIR_ACT1; +}; + +group gNPU2FIR + filter singlebit, + cs_root_cause +{ + /** NPU2FIR[0] + * OTL Brick2 translation fault + */ + (rNPU2FIR, bit(0)) ? defaultMaskedError; + + /** NPU2FIR[1] + * OTL Brick3 translation fault + */ + (rNPU2FIR, bit(1)) ? defaultMaskedError; + + /** NPU2FIR[2] + * OTL Brick4 translation fault + */ + (rNPU2FIR, bit(2)) ? defaultMaskedError; + + /** NPU2FIR[3] + * OTL Brick5 translation fault + */ + (rNPU2FIR, bit(3)) ? defaultMaskedError; + + /** NPU2FIR[4] + * OTL TL credit ctr overflow + */ + (rNPU2FIR, bit(4)) ? defaultMaskedError; + + /** NPU2FIR[5] + * OTL RX acTag invalid + */ + (rNPU2FIR, bit(5)) ? defaultMaskedError; + + /** NPU2FIR[6] + * OTL RX acTag points to an invalid entry. + */ + (rNPU2FIR, bit(6)) ? defaultMaskedError; + + /** NPU2FIR[7] + * OTL RX reserved opcode used. + */ + (rNPU2FIR, bit(7)) ? defaultMaskedError; + + /** NPU2FIR[8] + * OTL RX rtn_tl_credit cmd outside slot0. + */ + (rNPU2FIR, bit(8)) ? defaultMaskedError; + + /** NPU2FIR[9] + * OTL RX bad opcode and template combo + */ + (rNPU2FIR, bit(9)) ? defaultMaskedError; + + /** NPU2FIR[10] + * OTL RX unsupported template format. + */ + (rNPU2FIR, bit(10)) ? defaultMaskedError; + + /** NPU2FIR[11] + * OTL RX bad template x00 format. + */ + (rNPU2FIR, bit(11)) ? defaultMaskedError; + + /** NPU2FIR[12] + * OTL RX control flit overrun. + */ + (rNPU2FIR, bit(12)) ? defaultMaskedError; + + /** NPU2FIR[13] + * OTL RX unexpected data flit. + */ + (rNPU2FIR, bit(13)) ? defaultMaskedError; + + /** NPU2FIR[14] + * OTL RX DL link down. + */ + (rNPU2FIR, bit(14)) ? defaultMaskedError; + + /** NPU2FIR[15] + * OTL RX bad data received on command. + */ + (rNPU2FIR, bit(15)) ? defaultMaskedError; + + /** NPU2FIR[16] + * OTL RX bad data received on response. + */ + (rNPU2FIR, bit(16)) ? defaultMaskedError; + + /** NPU2FIR[17] + * OTL RX AP response not allowed + */ + (rNPU2FIR, bit(17)) ? defaultMaskedError; + + /** NPU2FIR[18] + * OR of all OTL parity errors. + */ + (rNPU2FIR, bit(18)) ? defaultMaskedError; + + /** NPU2FIR[19] + * OR of all OTL ECC CE errors. + */ + (rNPU2FIR, bit(19)) ? defaultMaskedError; + + /** NPU2FIR[20] + * OR of all OTL ECC UE errors. + */ + (rNPU2FIR, bit(20)) ? defaultMaskedError; + + /** NPU2FIR[21] + * RXO OP Errors. + */ + (rNPU2FIR, bit(21)) ? defaultMaskedError; + + /** NPU2FIR[22] + * RXO Internal Errors. + */ + (rNPU2FIR, bit(22)) ? defaultMaskedError; + + /** NPU2FIR[23] + * OTL RXI fifo overrun. + */ + (rNPU2FIR, bit(23)) ? defaultMaskedError; + + /** NPU2FIR[24] + * OTL RXI ctrl flit data run len invalid. + */ + (rNPU2FIR, bit(24)) ? defaultMaskedError; + + /** NPU2FIR[25] + * OTL RXI opcode specifies dL=0b00. + */ + (rNPU2FIR, bit(25)) ? defaultMaskedError; + + /** NPU2FIR[26] + * OTL RXI bad data received vc2 + */ + (rNPU2FIR, bit(26)) ? defaultMaskedError; + + /** NPU2FIR[27] + * OTL RXI dcp2 fifo overrun + */ + (rNPU2FIR, bit(27)) ? defaultMaskedError; + + /** NPU2FIR[28] + * OTL RXI vc1 fifo overrun + */ + (rNPU2FIR, bit(28)) ? defaultMaskedError; + + /** NPU2FIR[29] + * OTL RXI vc2 fifo overrun + */ + (rNPU2FIR, bit(29)) ? defaultMaskedError; + + /** NPU2FIR[30] + * Reserved + */ + (rNPU2FIR, bit(30)) ? defaultMaskedError; + + /** NPU2FIR[31] + * OTL TXI opcode error + */ + (rNPU2FIR, bit(31)) ? defaultMaskedError; + + /** NPU2FIR[32] + * Malformed packet error type 4 + */ + (rNPU2FIR, bit(32)) ? defaultMaskedError; + + /** NPU2FIR[33:35] + * Reserved + */ + (rNPU2FIR, bit(33|34|35)) ? defaultMaskedError; + + /** NPU2FIR[36] + * MMIO invalidate while one in progress. + */ + (rNPU2FIR, bit(36)) ? defaultMaskedError; + + /** NPU2FIR[37] + * Unexpected ITAG on itag completion pt 0 + */ + (rNPU2FIR, bit(37)) ? defaultMaskedError; + + /** NPU2FIR[38] + * Unexpected ITAG on itag completion pt 1 + */ + (rNPU2FIR, bit(38)) ? defaultMaskedError; + + /** NPU2FIR[39] + * Unexpected Read PEE completion. + */ + (rNPU2FIR, bit(39)) ? defaultMaskedError; + + /** NPU2FIR[40] + * Unexpected Checkout response. + */ + (rNPU2FIR, bit(40)) ? defaultMaskedError; + + /** NPU2FIR[41] + * Translation request but SPAP is invalid. + */ + (rNPU2FIR, bit(41)) ? defaultMaskedError; + + /** NPU2FIR[42] + * Read a PEE which was not valid. + */ + (rNPU2FIR, bit(42)) ? defaultMaskedError; + + /** NPU2FIR[43] + * Bloom filter protection error. + */ + (rNPU2FIR, bit(43)) ? defaultMaskedError; + + /** NPU2FIR[44] + * Translation request to non-valid TA + */ + (rNPU2FIR, bit(44)) ? defaultMaskedError; + + /** NPU2FIR[45] + * TA Translation request to an invalid TA + */ + (rNPU2FIR, bit(45)) ? defaultMaskedError; + + /** NPU2FIR[46] + * correctable array error (SBE). + */ + (rNPU2FIR, bit(46)) ? defaultMaskedError; + + /** NPU2FIR[47] + * array error (UE or parity). + */ + (rNPU2FIR, bit(47)) ? defaultMaskedError; + + /** NPU2FIR[48] + * S/TLBI buffer overflow. + */ + (rNPU2FIR, bit(48)) ? defaultMaskedError; + + /** NPU2FIR[49] + * SBE CE on Pb cout rsp or PEE read data. + */ + (rNPU2FIR, bit(49)) ? defaultMaskedError; + + /** NPU2FIR[50] + * UE on Pb cut rsp or PEE read data. + */ + (rNPU2FIR, bit(50)) ? defaultMaskedError; + + /** NPU2FIR[51] + * SUE on Pb chkout rsp or Pb PEE rd data. + */ + (rNPU2FIR, bit(51)) ? defaultMaskedError; + + /** NPU2FIR[52] + * PA mem_hit when bar mode is nonzero + */ + (rNPU2FIR, bit(52)) ? defaultMaskedError; + + /** NPU2FIR[53] + * XSL Reserved, macro bit 17. + */ + (rNPU2FIR, bit(53)) ? defaultMaskedError; + + /** NPU2FIR[54] + * OTL Brick0 translation fault + */ + (rNPU2FIR, bit(54)) ? defaultMaskedError; + + /** NPU2FIR[55] + * OTL Brick1 translation fault + */ + (rNPU2FIR, bit(55)) ? defaultMaskedError; + + /** NPU2FIR[56:61] + * Reserved + */ + (rNPU2FIR, bit(56|57|58|59|60|61)) ? defaultMaskedError; + + /** NPU2FIR[62] + * Local FIR PE RAS dup (ring 2, sat 2) + */ + (rNPU2FIR, bit(62)) ? defaultMaskedError; + + /** NPU2FIR[63] + * Lcl PE ACTION/MASK regs (ring 2, sat 2) + */ + (rNPU2FIR, bit(63)) ? defaultMaskedError; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "p9_common_npu_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_obus.rule b/src/usr/diag/prdf/common/plat/axone/axone_obus.rule new file mode 100644 index 000000000..1e90ada6f --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_obus.rule @@ -0,0 +1,885 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_obus.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_obus +{ + name "AXONE OBUS target"; + targettype TYPE_OBUS; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + +# Import signatures +.include "prdfLaneRepairExtraSig.H"; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # OB Chiplet FIR + ############################################################################ + + register OB_CHIPLET_CS_FIR + { + name "OB Chiplet Checkstop FIR"; + scomaddr 0x09040000; + capture group default; + }; + + register OB_CHIPLET_RE_FIR + { + name "OB Chiplet Recoverable FIR"; + scomaddr 0x09040001; + capture group default; + }; + + register OB_CHIPLET_FIR_MASK + { + name "OB Chiplet FIR MASK"; + scomaddr 0x09040002; + capture group default; + }; + + ############################################################################ + # OB Chiplet Unit Checkstop FIR + ############################################################################ + + register OB_CHIPLET_UCS_FIR + { + name "OB Chiplet Unit Checkstop FIR"; + scomaddr 0x09040018; + capture group default; + }; + + register OB_CHIPLET_UCS_FIR_MASK + { + name "OB Chiplet Unit Checkstop FIR MASK"; + scomaddr 0x09040019; + capture group default; + }; + + ############################################################################ + # P9 OBUS target OB_LFIR + ############################################################################ + + register OB_LFIR + { + name "P9 OBUS target OB_LFIR"; + scomaddr 0x0904000a; + reset (&, 0x0904000b); + mask (|, 0x0904000f); + capture group default; + }; + + register OB_LFIR_MASK + { + name "P9 OBUS target OB_LFIR MASK"; + scomaddr 0x0904000d; + capture group default; + }; + + register OB_LFIR_ACT0 + { + name "P9 OBUS target OB_LFIR ACT0"; + scomaddr 0x09040010; + capture group default; + capture req nonzero("OB_LFIR"); + }; + + register OB_LFIR_ACT1 + { + name "P9 OBUS target OB_LFIR ACT1"; + scomaddr 0x09040011; + capture group default; + capture req nonzero("OB_LFIR"); + }; + + ############################################################################ + # P9 OBUS target IOOLFIR + ############################################################################ + + register IOOLFIR + { + name "P9 OBUS target IOOLFIR"; + scomaddr 0x09010800; + reset (&, 0x09010801); + mask (|, 0x09010805); + capture group default; + capture group smpCableFFDC; + }; + + register IOOLFIR_MASK + { + name "P9 OBUS target IOOLFIR MASK"; + scomaddr 0x09010803; + capture group default; + }; + + register IOOLFIR_ACT0 + { + name "P9 OBUS target IOOLFIR ACT0"; + scomaddr 0x09010806; + capture group default; + capture req nonzero("IOOLFIR"); + }; + + register IOOLFIR_ACT1 + { + name "P9 OBUS target IOOLFIR ACT1"; + scomaddr 0x09010807; + capture group default; + capture req nonzero("IOOLFIR"); + }; + + ############################################################################ + # P9 OBUS target IOOBFIR + ############################################################################ + + register IOOBFIR + { + name "P9 OBUS target IOOBFIR"; + scomaddr 0x09010c00; + reset (&, 0x09010c01); + mask (|, 0x09010c05); + capture group default; + }; + + register IOOBFIR_MASK + { + name "P9 OBUS target IOOBFIR MASK"; + scomaddr 0x09010c03; + capture group default; + }; + + register IOOBFIR_ACT0 + { + name "P9 OBUS target IOOBFIR ACT0"; + scomaddr 0x09010c06; + capture group default; + capture req nonzero("IOOBFIR"); + }; + + register IOOBFIR_ACT1 + { + name "P9 OBUS target IOOBFIR ACT1"; + scomaddr 0x09010c07; + capture group default; + capture req nonzero("IOOBFIR"); + }; + + ############################################################################ + # P9 OBUS target OBPPEFIR + ############################################################################ + + register OBPPEFIR + { + name "P9 OBUS target OBPPEFIR"; + scomaddr 0x09011040; + reset (&, 0x09011041); + mask (|, 0x09011045); + capture group default; + }; + + register OBPPEFIR_MASK + { + name "P9 OBUS target OBPPEFIR MASK"; + scomaddr 0x09011043; + capture group default; + }; + + register OBPPEFIR_ACT0 + { + name "P9 OBUS target OBPPEFIR ACT0"; + scomaddr 0x09011046; + capture group default; + capture req nonzero("OBPPEFIR"); + }; + + register OBPPEFIR_ACT1 + { + name "P9 OBUS target OBPPEFIR ACT1"; + scomaddr 0x09011047; + capture group default; + capture req nonzero("OBPPEFIR"); + }; + +# Include registers not defined by the xml +.include "p9_common_obus_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# OB Chiplet FIR +################################################################################ + +rule rOB_CHIPLET_FIR +{ + CHECK_STOP: + OB_CHIPLET_CS_FIR & ~OB_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (OB_CHIPLET_RE_FIR >> 2) & ~OB_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gOB_CHIPLET_FIR attntype CHECK_STOP, RECOVERABLE + filter singlebit +{ + /** OB_CHIPLET_FIR[3] + * Attention from OB_LFIR + */ + (rOB_CHIPLET_FIR, bit(3)) ? analyzeOB_LFIR; + + /** OB_CHIPLET_FIR[4] + * Attention from IOOLFIR + */ + (rOB_CHIPLET_FIR, bit(4)) ? analyzeIOOLFIR; + + /** OB_CHIPLET_FIR[5] + * Attention from IOOBFIR + */ + (rOB_CHIPLET_FIR, bit(5)) ? analyzeIOOBFIR; + + /** OB_CHIPLET_FIR[6] + * Attention from OBPPEFIR + */ + (rOB_CHIPLET_FIR, bit(6)) ? analyzeOBPPEFIR; + +}; + +################################################################################ +# OB Chiplet Unit Checkstop FIR +################################################################################ + +rule rOB_CHIPLET_UCS_FIR +{ + UNIT_CS: + OB_CHIPLET_UCS_FIR & ~(OB_CHIPLET_UCS_FIR_MASK >> 1) & `7fffffffffffffff`; +}; + +group gOB_CHIPLET_UCS_FIR attntype UNIT_CS + filter singlebit +{ + /** OB_CHIPLET_UCS_FIR[2] + * Attention from IOOBFIR + */ + (rOB_CHIPLET_UCS_FIR, bit(2)) ? analyzeIOOBFIR; + + /** OB_CHIPLET_UCS_FIR[3] + * Attention from OBPPEFIR + */ + (rOB_CHIPLET_UCS_FIR, bit(3)) ? analyzeOBPPEFIR; + +}; + +################################################################################ +# P9 OBUS target OB_LFIR +################################################################################ + +rule rOB_LFIR +{ + CHECK_STOP: + OB_LFIR & ~OB_LFIR_MASK & ~OB_LFIR_ACT0 & ~OB_LFIR_ACT1; + RECOVERABLE: + OB_LFIR & ~OB_LFIR_MASK & ~OB_LFIR_ACT0 & OB_LFIR_ACT1; +}; + +group gOB_LFIR + filter singlebit, + cs_root_cause +{ + /** OB_LFIR[0] + * CFIR internal parity error + */ + (rOB_LFIR, bit(0)) ? self_th_32perDay; + + /** OB_LFIR[1] + * Chiplet Control Reg: PCB Access Error + */ + (rOB_LFIR, bit(1)) ? self_th_32perDay; + + /** OB_LFIR[2] + * Clock Controller: PCB Access Error + */ + (rOB_LFIR, bit(2)) ? self_th_32perDay; + + /** OB_LFIR[3] + * Clock Controller: Summarized Error + */ + (rOB_LFIR, bit(3)) ? self_th_32perDay; + + /** OB_LFIR[4] + * PSCOM Logic: PCB Access Error + */ + (rOB_LFIR, bit(4)) ? defaultMaskedError; + + /** OB_LFIR[5] + * PSCOM Logic: Summarized internal errors + */ + (rOB_LFIR, bit(5)) ? defaultMaskedError; + + /** OB_LFIR[6] + * Therm Logic: Summarized internal errors + */ + (rOB_LFIR, bit(6)) ? defaultMaskedError; + + /** OB_LFIR[7] + * Therm Logic: PCB Access Error + */ + (rOB_LFIR, bit(7)) ? defaultMaskedError; + + /** OB_LFIR[8] + * Therm Logic: Temperature critical trip + */ + (rOB_LFIR, bit(8)) ? defaultMaskedError; + + /** OB_LFIR[9] + * Therm Logic: Temperature fatal trip + */ + (rOB_LFIR, bit(9)) ? defaultMaskedError; + + /** OB_LFIR[10] + * UNUSED in P9 + */ + (rOB_LFIR, bit(10)) ? defaultMaskedError; + + /** OB_LFIR[11] + * Debug Logic: Scom Satellite Error + */ + (rOB_LFIR, bit(11)) ? defaultMaskedError; + + /** OB_LFIR[12] + * Scom Satellite Error - L3 Trace0 + */ + (rOB_LFIR, bit(12)) ? defaultMaskedError; + + /** OB_LFIR[13] + * Scom Satellite Error - L3 Trace0 + */ + (rOB_LFIR, bit(13)) ? defaultMaskedError; + + /** OB_LFIR[14:40] + * unused + */ + (rOB_LFIR, bit(14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError; + + /** OB_LFIR[41] + * Malfunction Alert or Local Checkstop + */ + (rOB_LFIR, bit(41)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 OBUS target IOOLFIR +################################################################################ + +rule rIOOLFIR +{ + CHECK_STOP: + IOOLFIR & ~IOOLFIR_MASK & ~IOOLFIR_ACT0 & ~IOOLFIR_ACT1; + RECOVERABLE: + IOOLFIR & ~IOOLFIR_MASK & ~IOOLFIR_ACT0 & IOOLFIR_ACT1; +}; + +group gIOOLFIR + filter singlebit, + cs_root_cause(54,55,56,57,58,59) +{ + /** IOOLFIR[0] + * link0 trained + */ + (rIOOLFIR, bit(0)) ? defaultMaskedError; + + /** IOOLFIR[1] + * link1 trained + */ + (rIOOLFIR, bit(1)) ? defaultMaskedError; + + /** IOOLFIR[2] + * link0 op irq + */ + (rIOOLFIR, bit(2)) ? defaultMaskedError; + + /** IOOLFIR[3] + * link1 op irq + */ + (rIOOLFIR, bit(3)) ? defaultMaskedError; + + /** IOOLFIR[4] + * link0 replay threshold + */ + (rIOOLFIR, bit(4)) ? defaultMaskedError; + + /** IOOLFIR[5] + * link1 replay threshold + */ + (rIOOLFIR, bit(5)) ? defaultMaskedError; + + /** IOOLFIR[6] + * link0 crc error + */ + (rIOOLFIR, bit(6)) ? threshold_and_mask_self; + + /** IOOLFIR[7] + * link1 crc error + */ + (rIOOLFIR, bit(7)) ? threshold_and_mask_self; + + /** IOOLFIR[8] + * link0 nak received + */ + (rIOOLFIR, bit(8)) ? defaultMaskedError; + + /** IOOLFIR[9] + * link1 nak received + */ + (rIOOLFIR, bit(9)) ? defaultMaskedError; + + /** IOOLFIR[10] + * link0 replay buffer full + */ + (rIOOLFIR, bit(10)) ? defaultMaskedError; + + /** IOOLFIR[11] + * link1 replay buffer full + */ + (rIOOLFIR, bit(11)) ? defaultMaskedError; + + /** IOOLFIR[12] + * link0 sl ecc threshold + */ + (rIOOLFIR, bit(12)) ? defaultMaskedError; + + /** IOOLFIR[13] + * link1 sl ecc threshold + */ + (rIOOLFIR, bit(13)) ? defaultMaskedError; + + /** IOOLFIR[14] + * link0 sl ecc correctable + */ + (rIOOLFIR, bit(14)) ? threshold_and_mask_self; + + /** IOOLFIR[15] + * link1 sl ecc correctable + */ + (rIOOLFIR, bit(15)) ? threshold_and_mask_self; + + /** IOOLFIR[16] + * link0 sl ecc ue + */ + (rIOOLFIR, bit(16)) ? threshold_and_mask_self; + + /** IOOLFIR[17] + * link1 sl ecc ue + */ + (rIOOLFIR, bit(17)) ? threshold_and_mask_self; + + /** IOOLFIR[18] + * link0 retrain threshold + */ + (rIOOLFIR, bit(18)) ? defaultMaskedError; + + /** IOOLFIR[19] + * link1 retrain threshold + */ + (rIOOLFIR, bit(19)) ? defaultMaskedError; + + /** IOOLFIR[20] + * link0 loss block align + */ + (rIOOLFIR, bit(20)) ? defaultMaskedError; + + /** IOOLFIR[21] + * link1 loss block align + */ + (rIOOLFIR, bit(21)) ? defaultMaskedError; + + /** IOOLFIR[22] + * link0 invalid block + */ + (rIOOLFIR, bit(22)) ? defaultMaskedError; + + /** IOOLFIR[23] + * link1 invalid block + */ + (rIOOLFIR, bit(23)) ? defaultMaskedError; + + /** IOOLFIR[24] + * link0 deskew error + */ + (rIOOLFIR, bit(24)) ? defaultMaskedError; + + /** IOOLFIR[25] + * link1 deskew error + */ + (rIOOLFIR, bit(25)) ? defaultMaskedError; + + /** IOOLFIR[26] + * link0 deskew overflow + */ + (rIOOLFIR, bit(26)) ? defaultMaskedError; + + /** IOOLFIR[27] + * link1 deskew overflow + */ + (rIOOLFIR, bit(27)) ? defaultMaskedError; + + /** IOOLFIR[28] + * link0 sw retrain + */ + (rIOOLFIR, bit(28)) ? defaultMaskedError; + + /** IOOLFIR[29] + * link1 sw retrain + */ + (rIOOLFIR, bit(29)) ? defaultMaskedError; + + /** IOOLFIR[30] + * link0 ack queue overflow + */ + (rIOOLFIR, bit(30)) ? defaultMaskedError; + + /** IOOLFIR[31] + * link1 ack queue overflow + */ + (rIOOLFIR, bit(31)) ? defaultMaskedError; + + /** IOOLFIR[32] + * link0 ack queue underflow + */ + (rIOOLFIR, bit(32)) ? defaultMaskedError; + + /** IOOLFIR[33] + * link1 ack queue underflow + */ + (rIOOLFIR, bit(33)) ? defaultMaskedError; + + /** IOOLFIR[34] + * link0 num replay + */ + (rIOOLFIR, bit(34)) ? defaultMaskedError; + + /** IOOLFIR[35] + * link1 num replay + */ + (rIOOLFIR, bit(35)) ? defaultMaskedError; + + /** IOOLFIR[36] + * link0 training set received + */ + (rIOOLFIR, bit(36)) ? defaultMaskedError; + + /** IOOLFIR[37] + * link1 training set received + */ + (rIOOLFIR, bit(37)) ? defaultMaskedError; + + /** IOOLFIR[38] + * link0 prbs select error + */ + (rIOOLFIR, bit(38)) ? threshold_and_mask_self; + + /** IOOLFIR[39] + * link1 prbs select error + */ + (rIOOLFIR, bit(39)) ? threshold_and_mask_self; + + /** IOOLFIR[40] + * link0 tcomplete bad + */ + (rIOOLFIR, bit(40)) ? defaultMaskedError; + + /** IOOLFIR[41] + * link1 tcomplete bad + */ + (rIOOLFIR, bit(41)) ? defaultMaskedError; + + /** IOOLFIR[42] + * link0 no spare lane available + */ + (rIOOLFIR, bit(42)) ? obusSmpCallout_L0; + + /** IOOLFIR[43] + * link1 no spare lane available + */ + (rIOOLFIR, bit(43)) ? obusSmpCallout_L1; + + /** IOOLFIR[44] + * link0 spare done + */ + (rIOOLFIR, bit(44)) ? obusSmpCallout_th32_L0; + + /** IOOLFIR[45] + * link1 spare done + */ + (rIOOLFIR, bit(45)) ? obusSmpCallout_th32_L1; + + /** IOOLFIR[46] + * link0 too many crc errors + */ + (rIOOLFIR, bit(46)) ? obusSmpCallout_L0; + + /** IOOLFIR[47] + * link1 too many crc errors + */ + (rIOOLFIR, bit(47)) ? obusSmpCallout_L1; + + /** IOOLFIR[48] + * link0 npu error + */ + (rIOOLFIR, bit(48)) ? threshold_and_mask_self; + + /** IOOLFIR[49] + * link1 npu error + */ + (rIOOLFIR, bit(49)) ? threshold_and_mask_self; + + /** IOOLFIR[50] + * linkx npu error + */ + (rIOOLFIR, bit(50)) ? threshold_and_mask_self; + + /** IOOLFIR[51] + * osc switch + */ + (rIOOLFIR, bit(51)) ? threshold_and_mask_self; + + /** IOOLFIR[52] + * link0 correctable array error + */ + (rIOOLFIR, bit(52)) ? obusSmpCallout_th32_L0; + + /** IOOLFIR[53] + * link1 correctable array error + */ + (rIOOLFIR, bit(53)) ? obusSmpCallout_th32_L1; + + /** IOOLFIR[54] + * link0 uncorrectable array error + */ + (rIOOLFIR, bit(54)) ? obusSmpCallout_th32_L0; + + /** IOOLFIR[55] + * link1 uncorrectable array error + */ + (rIOOLFIR, bit(55)) ? obusSmpCallout_th32_L1; + + /** IOOLFIR[56] + * link0 training failed + */ + (rIOOLFIR, bit(56)) ? obusSmpFailure_L0; + + /** IOOLFIR[57] + * link1 training failed + */ + (rIOOLFIR, bit(57)) ? obusSmpFailure_L1; + + /** IOOLFIR[58] + * link0 unrecoverable error + */ + (rIOOLFIR, bit(58)) ? obusSmpCallout_th32_L0; + + /** IOOLFIR[59] + * link1 unrecoverable error + */ + (rIOOLFIR, bit(59)) ? obusSmpCallout_th32_L1; + + /** IOOLFIR[60] + * link0 internal error + */ + (rIOOLFIR, bit(60)) ? self_th_32perDay; + + /** IOOLFIR[61] + * link1 internal error + */ + (rIOOLFIR, bit(61)) ? self_th_32perDay; + + /** IOOLFIR[62] + * fir scom err dup + */ + (rIOOLFIR, bit(62)) ? defaultMaskedError; + + /** IOOLFIR[63] + * fir scom err + */ + (rIOOLFIR, bit(63)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 OBUS target IOOBFIR +################################################################################ + +rule rIOOBFIR +{ + CHECK_STOP: + IOOBFIR & ~IOOBFIR_MASK & ~IOOBFIR_ACT0 & ~IOOBFIR_ACT1; + RECOVERABLE: + IOOBFIR & ~IOOBFIR_MASK & ~IOOBFIR_ACT0 & IOOBFIR_ACT1; + UNIT_CS: + IOOBFIR & ~IOOBFIR_MASK & IOOBFIR_ACT0 & IOOBFIR_ACT1; +}; + +group gIOOBFIR + filter singlebit, + cs_root_cause +{ + /** IOOBFIR[0] + * A RX state machine error + */ + (rIOOBFIR, bit(0)) ? defaultMaskedError; + + /** IOOBFIR[1] + * A TX state machine error + */ + (rIOOBFIR, bit(1)) ? defaultMaskedError; + + /** IOOBFIR[2] + * The per-bus GCR ring hang detector error + */ + (rIOOBFIR, bit(2)) ? self_th_1; + + /** IOOBFIR[3:47] + * spare + */ + (rIOOBFIR, bit(3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47)) ? defaultMaskedError; + + /** IOOBFIR[48] + * scom error + */ + (rIOOBFIR, bit(48)) ? defaultMaskedError; + + /** IOOBFIR[49] + * scom error + */ + (rIOOBFIR, bit(49)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 OBUS target OBPPEFIR +################################################################################ + +rule rOBPPEFIR +{ + CHECK_STOP: + OBPPEFIR & ~OBPPEFIR_MASK & ~OBPPEFIR_ACT0 & ~OBPPEFIR_ACT1; + RECOVERABLE: + OBPPEFIR & ~OBPPEFIR_MASK & ~OBPPEFIR_ACT0 & OBPPEFIR_ACT1; + UNIT_CS: + OBPPEFIR & ~OBPPEFIR_MASK & OBPPEFIR_ACT0 & OBPPEFIR_ACT1; +}; + +group gOBPPEFIR + filter singlebit, + cs_root_cause +{ + /** OBPPEFIR[0:3] + * PPE general error. + */ + (rOBPPEFIR, bit(0|1|2|3)) ? threshold_and_mask_self; + + /** OBPPEFIR[4] + * PPE halted. + */ + (rOBPPEFIR, bit(4)) ? defaultMaskedError; + + /** OBPPEFIR[5] + * PPE watchdog timer timed out. + */ + (rOBPPEFIR, bit(5)) ? defaultMaskedError; + + /** OBPPEFIR[6] + * PPE MMIO data in error. + */ + (rOBPPEFIR, bit(6)) ? defaultMaskedError; + + /** OBPPEFIR[7] + * PPE Arb missed scrub tick. + */ + (rOBPPEFIR, bit(7)) ? threshold_and_mask_self; + + /** OBPPEFIR[8] + * PPE Arb ary ue error. + */ + (rOBPPEFIR, bit(8)) ? self_th_1; + + /** OBPPEFIR[9] + * PPE Arb ary ce error. + */ + (rOBPPEFIR, bit(9)) ? threshold_and_mask_self; + + /** OBPPEFIR[10] + * spare + */ + (rOBPPEFIR, bit(10)) ? defaultMaskedError; + + /** OBPPEFIR[11] + * scom error + */ + (rOBPPEFIR, bit(11)) ? defaultMaskedError; + + /** OBPPEFIR[12] + * scom error + */ + (rOBPPEFIR, bit(12)) ? defaultMaskedError; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "p9_common_obus_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_omic.rule b/src/usr/diag/prdf/common/plat/axone/axone_omic.rule new file mode 100644 index 000000000..09ed59f2d --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_omic.rule @@ -0,0 +1,686 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_omic.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_omic +{ + name "AXONE OMIC target"; + targettype TYPE_OMIC; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # P9 OMIC target IOOMIFIR + ############################################################################ + + register IOOMIFIR + { + name "P9 OMIC target IOOMIFIR"; + scomaddr 0x07011000; + reset (&, 0x07011001); + mask (|, 0x07011005); + capture group default; + }; + + register IOOMIFIR_MASK + { + name "P9 OMIC target IOOMIFIR MASK"; + scomaddr 0x07011003; + capture group default; + }; + + register IOOMIFIR_ACT0 + { + name "P9 OMIC target IOOMIFIR ACT0"; + scomaddr 0x07011006; + capture group default; + capture req nonzero("IOOMIFIR"); + }; + + register IOOMIFIR_ACT1 + { + name "P9 OMIC target IOOMIFIR ACT1"; + scomaddr 0x07011007; + capture group default; + capture req nonzero("IOOMIFIR"); + }; + + ############################################################################ + # P9 OMIC target MCPPEFIR + ############################################################################ + + register MCPPEFIR + { + name "P9 OMIC target MCPPEFIR"; + scomaddr 0x07012440; + reset (&, 0x07012441); + mask (|, 0x07012445); + capture group default; + }; + + register MCPPEFIR_MASK + { + name "P9 OMIC target MCPPEFIR MASK"; + scomaddr 0x07012443; + capture group default; + }; + + register MCPPEFIR_ACT0 + { + name "P9 OMIC target MCPPEFIR ACT0"; + scomaddr 0x07012446; + capture group default; + capture req nonzero("MCPPEFIR"); + }; + + register MCPPEFIR_ACT1 + { + name "P9 OMIC target MCPPEFIR ACT1"; + scomaddr 0x07012447; + capture group default; + capture req nonzero("MCPPEFIR"); + }; + + ############################################################################ + # P9 OMIC target OMIDLFIR + ############################################################################ + + register OMIDLFIR + { + name "P9 OMIC target OMIDLFIR"; + scomaddr 0x07013340; + reset (&, 0x07013341); + mask (|, 0x07013345); + capture group default; + }; + + register OMIDLFIR_MASK + { + name "P9 OMIC target OMIDLFIR MASK"; + scomaddr 0x07013343; + capture group default; + }; + + register OMIDLFIR_ACT0 + { + name "P9 OMIC target OMIDLFIR ACT0"; + scomaddr 0x07013346; + capture group default; + capture req nonzero("OMIDLFIR"); + }; + + register OMIDLFIR_ACT1 + { + name "P9 OMIC target OMIDLFIR ACT1"; + scomaddr 0x07013347; + capture group default; + capture req nonzero("OMIDLFIR"); + }; + +# Include registers not defined by the xml +.include "axone_omic_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Summary for OMIC +################################################################################ + +rule rOMIC +{ + CHECK_STOP: + summary( 0, rIOOMIFIR ) | + summary( 1, rMCPPEFIR ) | + summary( 2, rOMIDLFIR ); + + RECOVERABLE: + summary( 0, rIOOMIFIR ) | + summary( 1, rMCPPEFIR ) | + summary( 2, rOMIDLFIR ); + + UNIT_CS: + summary( 0, rIOOMIFIR ) | + summary( 1, rMCPPEFIR ) | + summary( 2, rOMIDLFIR ); + + HOST_ATTN: + summary( 0, rIOOMIFIR ) | + summary( 1, rMCPPEFIR ) | + summary( 2, rOMIDLFIR ); + +}; + +group gOMIC attntype CHECK_STOP, RECOVERABLE, UNIT_CS, HOST_ATTN + filter singlebit +{ + (rOMIC, bit(0)) ? analyzeIOOMIFIR; + (rOMIC, bit(1)) ? analyzeMCPPEFIR; + (rOMIC, bit(2)) ? analyzeOMIDLFIR; +}; + +################################################################################ +# P9 OMIC target IOOMIFIR +################################################################################ + +rule rIOOMIFIR +{ + CHECK_STOP: + IOOMIFIR & ~IOOMIFIR_MASK & ~IOOMIFIR_ACT0 & ~IOOMIFIR_ACT1; + RECOVERABLE: + IOOMIFIR & ~IOOMIFIR_MASK & ~IOOMIFIR_ACT0 & IOOMIFIR_ACT1; + HOST_ATTN: + IOOMIFIR & ~IOOMIFIR_MASK & IOOMIFIR_ACT0 & ~IOOMIFIR_ACT1; + UNIT_CS: + IOOMIFIR & ~IOOMIFIR_MASK & IOOMIFIR_ACT0 & IOOMIFIR_ACT1; +}; + +group gIOOMIFIR + filter singlebit, + cs_root_cause +{ + /** IOOMIFIR[0] + * RX invalid state or parity error + */ + (rIOOMIFIR, bit(0)) ? defaultMaskedError; + + /** IOOMIFIR[1] + * TX invalid state or parity error + */ + (rIOOMIFIR, bit(1)) ? defaultMaskedError; + + /** IOOMIFIR[2] + * GCR hang error + */ + (rIOOMIFIR, bit(2)) ? defaultMaskedError; + + /** IOOMIFIR[3:47] + * Unused + */ + (rIOOMIFIR, bit(3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47)) ? defaultMaskedError; + + /** IOOMIFIR[48] + * SCOM FSM or FIR register parity error + */ + (rIOOMIFIR, bit(48)) ? defaultMaskedError; + + /** IOOMIFIR[49] + * SCOM FSM or FIR register parity error clone + */ + (rIOOMIFIR, bit(49)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 OMIC target MCPPEFIR +################################################################################ + +rule rMCPPEFIR +{ + CHECK_STOP: + MCPPEFIR & ~MCPPEFIR_MASK & ~MCPPEFIR_ACT0 & ~MCPPEFIR_ACT1; + RECOVERABLE: + MCPPEFIR & ~MCPPEFIR_MASK & ~MCPPEFIR_ACT0 & MCPPEFIR_ACT1; + HOST_ATTN: + MCPPEFIR & ~MCPPEFIR_MASK & MCPPEFIR_ACT0 & ~MCPPEFIR_ACT1; + UNIT_CS: + MCPPEFIR & ~MCPPEFIR_MASK & MCPPEFIR_ACT0 & MCPPEFIR_ACT1; +}; + +group gMCPPEFIR + filter singlebit, + cs_root_cause +{ + /** MCPPEFIR[0] + * PPE general error. + */ + (rMCPPEFIR, bit(0)) ? defaultMaskedError; + + /** MCPPEFIR[1] + * PPE general error. + */ + (rMCPPEFIR, bit(1)) ? defaultMaskedError; + + /** MCPPEFIR[2] + * PPE general error. + */ + (rMCPPEFIR, bit(2)) ? defaultMaskedError; + + /** MCPPEFIR[3] + * PPE general error. + */ + (rMCPPEFIR, bit(3)) ? defaultMaskedError; + + /** MCPPEFIR[4] + * PPE halted. + */ + (rMCPPEFIR, bit(4)) ? defaultMaskedError; + + /** MCPPEFIR[5] + * PPE watchdog timer timed out + */ + (rMCPPEFIR, bit(5)) ? defaultMaskedError; + + /** MCPPEFIR[6] + * MMIO data in error. + */ + (rMCPPEFIR, bit(6)) ? defaultMaskedError; + + /** MCPPEFIR[7] + * Arb missed scrub tick. + */ + (rMCPPEFIR, bit(7)) ? defaultMaskedError; + + /** MCPPEFIR[8] + * Arb ary ue error. + */ + (rMCPPEFIR, bit(8)) ? defaultMaskedError; + + /** MCPPEFIR[9] + * Arb ary ce error. + */ + (rMCPPEFIR, bit(9)) ? defaultMaskedError; + + /** MCPPEFIR[10] + * spare + */ + (rMCPPEFIR, bit(10)) ? defaultMaskedError; + + /** MCPPEFIR[11] + * FIR_SCOMFIR_ERROR + */ + (rMCPPEFIR, bit(11)) ? defaultMaskedError; + + /** MCPPEFIR[12] + * FIR_SCOMFIR_ERROR + */ + (rMCPPEFIR, bit(12)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 OMIC target OMIDLFIR +################################################################################ + +rule rOMIDLFIR +{ + CHECK_STOP: + OMIDLFIR & ~OMIDLFIR_MASK & ~OMIDLFIR_ACT0 & ~OMIDLFIR_ACT1; + RECOVERABLE: + OMIDLFIR & ~OMIDLFIR_MASK & ~OMIDLFIR_ACT0 & OMIDLFIR_ACT1; + HOST_ATTN: + OMIDLFIR & ~OMIDLFIR_MASK & OMIDLFIR_ACT0 & ~OMIDLFIR_ACT1; + UNIT_CS: + OMIDLFIR & ~OMIDLFIR_MASK & OMIDLFIR_ACT0 & OMIDLFIR_ACT1; +}; + +group gOMIDLFIR + filter singlebit, + cs_root_cause +{ + /** OMIDLFIR[0] + * DL0 fatal error + */ + (rOMIDLFIR, bit(0)) ? defaultMaskedError; + + /** OMIDLFIR[1] + * DL0 data UE + */ + (rOMIDLFIR, bit(1)) ? defaultMaskedError; + + /** OMIDLFIR[2] + * DL0 flit CE + */ + (rOMIDLFIR, bit(2)) ? defaultMaskedError; + + /** OMIDLFIR[3] + * DL0 CRC error + */ + (rOMIDLFIR, bit(3)) ? defaultMaskedError; + + /** OMIDLFIR[4] + * DL0 nack + */ + (rOMIDLFIR, bit(4)) ? defaultMaskedError; + + /** OMIDLFIR[5] + * DL0 X4 mode + */ + (rOMIDLFIR, bit(5)) ? defaultMaskedError; + + /** OMIDLFIR[6] + * DL0 EDPL + */ + (rOMIDLFIR, bit(6)) ? defaultMaskedError; + + /** OMIDLFIR[7] + * DL0 timeout + */ + (rOMIDLFIR, bit(7)) ? defaultMaskedError; + + /** OMIDLFIR[8] + * DL0 remote retrain + */ + (rOMIDLFIR, bit(8)) ? defaultMaskedError; + + /** OMIDLFIR[9] + * DL0 error retrain + */ + (rOMIDLFIR, bit(9)) ? defaultMaskedError; + + /** OMIDLFIR[10] + * DL0 EDPL retrain + */ + (rOMIDLFIR, bit(10)) ? defaultMaskedError; + + /** OMIDLFIR[11] + * DL0 trained + */ + (rOMIDLFIR, bit(11)) ? defaultMaskedError; + + /** OMIDLFIR[12] + * DL0 endpoint bit 0 + */ + (rOMIDLFIR, bit(12)) ? defaultMaskedError; + + /** OMIDLFIR[13] + * DL0 endpoint bit 1 + */ + (rOMIDLFIR, bit(13)) ? defaultMaskedError; + + /** OMIDLFIR[14] + * DL0 endpoint bit 2 + */ + (rOMIDLFIR, bit(14)) ? defaultMaskedError; + + /** OMIDLFIR[15] + * DL0 endpoint bit 3 + */ + (rOMIDLFIR, bit(15)) ? defaultMaskedError; + + /** OMIDLFIR[16] + * DL0 endpoint bit 4 + */ + (rOMIDLFIR, bit(16)) ? defaultMaskedError; + + /** OMIDLFIR[17] + * DL0 endpoint bit 5 + */ + (rOMIDLFIR, bit(17)) ? defaultMaskedError; + + /** OMIDLFIR[18] + * DL0 endpoint bit 6 + */ + (rOMIDLFIR, bit(18)) ? defaultMaskedError; + + /** OMIDLFIR[19] + * DL0 endpoint bit 7 + */ + (rOMIDLFIR, bit(19)) ? defaultMaskedError; + + /** OMIDLFIR[20] + * DL1 fatal error + */ + (rOMIDLFIR, bit(20)) ? defaultMaskedError; + + /** OMIDLFIR[21] + * DL1 data UE + */ + (rOMIDLFIR, bit(21)) ? defaultMaskedError; + + /** OMIDLFIR[22] + * DL1 flit CE + */ + (rOMIDLFIR, bit(22)) ? defaultMaskedError; + + /** OMIDLFIR[23] + * DL1 CRC error + */ + (rOMIDLFIR, bit(23)) ? defaultMaskedError; + + /** OMIDLFIR[24] + * DL1 nack + */ + (rOMIDLFIR, bit(24)) ? defaultMaskedError; + + /** OMIDLFIR[25] + * DL1 X4 mode + */ + (rOMIDLFIR, bit(25)) ? defaultMaskedError; + + /** OMIDLFIR[26] + * DL1 EDPL + */ + (rOMIDLFIR, bit(26)) ? defaultMaskedError; + + /** OMIDLFIR[27] + * DL1 timeout + */ + (rOMIDLFIR, bit(27)) ? defaultMaskedError; + + /** OMIDLFIR[28] + * DL1 remote retrain + */ + (rOMIDLFIR, bit(28)) ? defaultMaskedError; + + /** OMIDLFIR[29] + * DL1 error retrain + */ + (rOMIDLFIR, bit(29)) ? defaultMaskedError; + + /** OMIDLFIR[30] + * DL1 EDPL retrain + */ + (rOMIDLFIR, bit(30)) ? defaultMaskedError; + + /** OMIDLFIR[31] + * DL1 trained + */ + (rOMIDLFIR, bit(31)) ? defaultMaskedError; + + /** OMIDLFIR[32] + * DL1 endpoint bit 0 + */ + (rOMIDLFIR, bit(32)) ? defaultMaskedError; + + /** OMIDLFIR[33] + * DL1 endpoint bit 1 + */ + (rOMIDLFIR, bit(33)) ? defaultMaskedError; + + /** OMIDLFIR[34] + * DL1 endpoint bit 2 + */ + (rOMIDLFIR, bit(34)) ? defaultMaskedError; + + /** OMIDLFIR[35] + * DL1 endpoint bit 3 + */ + (rOMIDLFIR, bit(35)) ? defaultMaskedError; + + /** OMIDLFIR[36] + * DL1 endpoint bit 4 + */ + (rOMIDLFIR, bit(36)) ? defaultMaskedError; + + /** OMIDLFIR[37] + * DL1 endpoint bit 5 + */ + (rOMIDLFIR, bit(37)) ? defaultMaskedError; + + /** OMIDLFIR[38] + * DL1 endpoint bit 6 + */ + (rOMIDLFIR, bit(38)) ? defaultMaskedError; + + /** OMIDLFIR[39] + * DL1 endpoint bit 7 + */ + (rOMIDLFIR, bit(39)) ? defaultMaskedError; + + /** OMIDLFIR[40] + * DL2 fatal error + */ + (rOMIDLFIR, bit(40)) ? defaultMaskedError; + + /** OMIDLFIR[41] + * DL2 data UE + */ + (rOMIDLFIR, bit(41)) ? defaultMaskedError; + + /** OMIDLFIR[42] + * DL2 flit CE + */ + (rOMIDLFIR, bit(42)) ? defaultMaskedError; + + /** OMIDLFIR[43] + * DL2 CRC error + */ + (rOMIDLFIR, bit(43)) ? defaultMaskedError; + + /** OMIDLFIR[44] + * DL2 nack + */ + (rOMIDLFIR, bit(44)) ? defaultMaskedError; + + /** OMIDLFIR[45] + * DL2 X4 mode + */ + (rOMIDLFIR, bit(45)) ? defaultMaskedError; + + /** OMIDLFIR[46] + * DL2 EDPL + */ + (rOMIDLFIR, bit(46)) ? defaultMaskedError; + + /** OMIDLFIR[47] + * DL2 timeout + */ + (rOMIDLFIR, bit(47)) ? defaultMaskedError; + + /** OMIDLFIR[48] + * DL2 remote retrain + */ + (rOMIDLFIR, bit(48)) ? defaultMaskedError; + + /** OMIDLFIR[49] + * DL2 error retrain + */ + (rOMIDLFIR, bit(49)) ? defaultMaskedError; + + /** OMIDLFIR[50] + * DL2 EDPL retrain + */ + (rOMIDLFIR, bit(50)) ? defaultMaskedError; + + /** OMIDLFIR[51] + * DL2 trained + */ + (rOMIDLFIR, bit(51)) ? defaultMaskedError; + + /** OMIDLFIR[52] + * DL2 endpoint bit 0 + */ + (rOMIDLFIR, bit(52)) ? defaultMaskedError; + + /** OMIDLFIR[53] + * DL2 endpoint bit 1 + */ + (rOMIDLFIR, bit(53)) ? defaultMaskedError; + + /** OMIDLFIR[54] + * DL2 endpoint bit 2 + */ + (rOMIDLFIR, bit(54)) ? defaultMaskedError; + + /** OMIDLFIR[55] + * DL2 endpoint bit 3 + */ + (rOMIDLFIR, bit(55)) ? defaultMaskedError; + + /** OMIDLFIR[56] + * DL2 endpoint bit 4 + */ + (rOMIDLFIR, bit(56)) ? defaultMaskedError; + + /** OMIDLFIR[57] + * DL2 endpoint bit 5 + */ + (rOMIDLFIR, bit(57)) ? defaultMaskedError; + + /** OMIDLFIR[58] + * DL2 endpoint bit 6 + */ + (rOMIDLFIR, bit(58)) ? defaultMaskedError; + + /** OMIDLFIR[59] + * DL2 endpoint bit 7 + */ + (rOMIDLFIR, bit(59)) ? defaultMaskedError; + + /** OMIDLFIR[60] + * Performance monitor wrapped + */ + (rOMIDLFIR, bit(60)) ? defaultMaskedError; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "axone_omic_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_omic_actions.rule b/src/usr/diag/prdf/common/plat/axone/axone_omic_actions.rule new file mode 100644 index 000000000..ecb6626a8 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_omic_actions.rule @@ -0,0 +1,33 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_omic_actions.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +################################################################################ +# Analyze groups +################################################################################ + +actionclass analyzeIOOMIFIR { analyze(gIOOMIFIR); }; +actionclass analyzeMCPPEFIR { analyze(gMCPPEFIR); }; +actionclass analyzeOMIDLFIR { analyze(gOMIDLFIR); }; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_pec.rule b/src/usr/diag/prdf/common/plat/axone/axone_pec.rule new file mode 100644 index 000000000..ec728cb3b --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_pec.rule @@ -0,0 +1,472 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_pec.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_pec +{ + name "AXONE PEC target"; + targettype TYPE_PEC; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # P9 PEC target PCI_LFIR + ############################################################################ + + register PCI_LFIR + { + name "P9 PEC target PCI_LFIR"; + scomaddr 0x0d04000a; + reset (&, 0x0d04000b); + mask (|, 0x0d04000f); + capture group default; + }; + + register PCI_LFIR_MASK + { + name "P9 PEC target PCI_LFIR MASK"; + scomaddr 0x0d04000d; + capture group default; + }; + + register PCI_LFIR_ACT0 + { + name "P9 PEC target PCI_LFIR ACT0"; + scomaddr 0x0d040010; + capture group default; + capture req nonzero("PCI_LFIR"); + }; + + register PCI_LFIR_ACT1 + { + name "P9 PEC target PCI_LFIR ACT1"; + scomaddr 0x0d040011; + capture group default; + capture req nonzero("PCI_LFIR"); + }; + + ############################################################################ + # P9 PEC target IOPCIFIR + ############################################################################ + + register IOPCIFIR + { + name "P9 PEC target IOPCIFIR"; + scomaddr 0x0d010c00; + reset (&, 0x0d010c01); + mask (|, 0x0d010c05); + capture group default; + }; + + register IOPCIFIR_MASK + { + name "P9 PEC target IOPCIFIR MASK"; + scomaddr 0x0d010c03; + capture group default; + }; + + register IOPCIFIR_ACT0 + { + name "P9 PEC target IOPCIFIR ACT0"; + scomaddr 0x0d010c06; + capture group default; + capture req nonzero("IOPCIFIR"); + }; + + register IOPCIFIR_ACT1 + { + name "P9 PEC target IOPCIFIR ACT1"; + scomaddr 0x0d010c07; + capture group default; + capture req nonzero("IOPCIFIR"); + }; + +# Include registers not defined by the xml +.include "p9_common_pec_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Summary for PEC +################################################################################ + +rule rPEC +{ + CHECK_STOP: + summary( 0, rPCI_LFIR ) | + summary( 1, rIOPCIFIR ); + + RECOVERABLE: + summary( 0, rPCI_LFIR ) | + summary( 1, rIOPCIFIR ); + +}; + +group gPEC attntype CHECK_STOP, RECOVERABLE + filter singlebit +{ + (rPEC, bit(0)) ? analyzePCI_LFIR; + (rPEC, bit(1)) ? analyzeIOPCIFIR; +}; + +################################################################################ +# P9 PEC target PCI_LFIR +################################################################################ + +rule rPCI_LFIR +{ + CHECK_STOP: + PCI_LFIR & ~PCI_LFIR_MASK & ~PCI_LFIR_ACT0 & ~PCI_LFIR_ACT1; + RECOVERABLE: + PCI_LFIR & ~PCI_LFIR_MASK & ~PCI_LFIR_ACT0 & PCI_LFIR_ACT1; +}; + +group gPCI_LFIR + filter singlebit, + cs_root_cause +{ + /** PCI_LFIR[0] + * CFIR internal parity error + */ + (rPCI_LFIR, bit(0)) ? self_th_32perDay; + + /** PCI_LFIR[1] + * Chiplet Control Reg: PCB Access Error + */ + (rPCI_LFIR, bit(1)) ? self_th_32perDay; + + /** PCI_LFIR[2] + * Clock Controller: PCB Access Error + */ + (rPCI_LFIR, bit(2)) ? self_th_32perDay; + + /** PCI_LFIR[3] + * Clock Controller: Summarized Error + */ + (rPCI_LFIR, bit(3)) ? self_th_32perDay; + + /** PCI_LFIR[4] + * PSCOM Logic: PCB Access Error + */ + (rPCI_LFIR, bit(4)) ? defaultMaskedError; + + /** PCI_LFIR[5] + * PSCOM Logic: Summarized internal errors + */ + (rPCI_LFIR, bit(5)) ? defaultMaskedError; + + /** PCI_LFIR[6] + * Therm Logic: Summarized internal errors + */ + (rPCI_LFIR, bit(6)) ? defaultMaskedError; + + /** PCI_LFIR[7] + * Therm Logic: PCB Access Error + */ + (rPCI_LFIR, bit(7)) ? defaultMaskedError; + + /** PCI_LFIR[8] + * Therm Logic: Temperature critical trip + */ + (rPCI_LFIR, bit(8)) ? defaultMaskedError; + + /** PCI_LFIR[9] + * Therm Logic: Temperature fatal trip + */ + (rPCI_LFIR, bit(9)) ? defaultMaskedError; + + /** PCI_LFIR[10] + * UNUSED in P9 + */ + (rPCI_LFIR, bit(10)) ? defaultMaskedError; + + /** PCI_LFIR[11] + * Debug Logic: Scom Satellite Error + */ + (rPCI_LFIR, bit(11)) ? defaultMaskedError; + + /** PCI_LFIR[12] + * Scom Satellite Error - L3 Trace0 + */ + (rPCI_LFIR, bit(12)) ? defaultMaskedError; + + /** PCI_LFIR[13] + * Scom Satellite Error - L3 Trace0 + */ + (rPCI_LFIR, bit(13)) ? defaultMaskedError; + + /** PCI_LFIR[14:40] + * unused + */ + (rPCI_LFIR, bit(14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError; + + /** PCI_LFIR[41] + * Malfunction Alert or Local Checkstop + */ + (rPCI_LFIR, bit(41)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 PEC target IOPCIFIR +################################################################################ + +rule rIOPCIFIR +{ + CHECK_STOP: + IOPCIFIR & ~IOPCIFIR_MASK & ~IOPCIFIR_ACT0 & ~IOPCIFIR_ACT1; + RECOVERABLE: + IOPCIFIR & ~IOPCIFIR_MASK & ~IOPCIFIR_ACT0 & IOPCIFIR_ACT1; +}; + +group gIOPCIFIR + filter singlebit, + cs_root_cause +{ + /** IOPCIFIR[0] + * HSS ZCAL Calibration Error + */ + (rIOPCIFIR, bit(0)) ? parent_proc_th_1; + + /** IOPCIFIR[1] + * HSS CAL PLL A Calibration error + */ + (rIOPCIFIR, bit(1)) ? parent_proc_th_1; + + /** IOPCIFIR[2] + * HSS CAL PLL B Calibration error + */ + (rIOPCIFIR, bit(2)) ? parent_proc_th_1; + + /** IOPCIFIR[3] + * TX Lane A Calibration Error + */ + (rIOPCIFIR, bit(3)) ? defaultMaskedError; + + /** IOPCIFIR[4] + * TX Lane B Calibration Error + */ + (rIOPCIFIR, bit(4)) ? defaultMaskedError; + + /** IOPCIFIR[5] + * TX Lane C Calibration Error + */ + (rIOPCIFIR, bit(5)) ? defaultMaskedError; + + /** IOPCIFIR[6] + * TX Lane D Calibration Error + */ + (rIOPCIFIR, bit(6)) ? defaultMaskedError; + + /** IOPCIFIR[7] + * TX Lane E Calibration Error + */ + (rIOPCIFIR, bit(7)) ? defaultMaskedError; + + /** IOPCIFIR[8] + * TX Lane F Calibration Error + */ + (rIOPCIFIR, bit(8)) ? defaultMaskedError; + + /** IOPCIFIR[9] + * TX Lane G Calibration Error + */ + (rIOPCIFIR, bit(9)) ? defaultMaskedError; + + /** IOPCIFIR[10] + * TX Lane H Calibration Error + */ + (rIOPCIFIR, bit(10)) ? defaultMaskedError; + + /** IOPCIFIR[11] + * TX Lane I Calibration Error + */ + (rIOPCIFIR, bit(11)) ? defaultMaskedError; + + /** IOPCIFIR[12] + * TX Lane J Calibration Error + */ + (rIOPCIFIR, bit(12)) ? defaultMaskedError; + + /** IOPCIFIR[13] + * TX Lane K Calibration Error + */ + (rIOPCIFIR, bit(13)) ? defaultMaskedError; + + /** IOPCIFIR[14] + * TX Lane L Calibration Error + */ + (rIOPCIFIR, bit(14)) ? defaultMaskedError; + + /** IOPCIFIR[15] + * TX Lane M Calibration Error + */ + (rIOPCIFIR, bit(15)) ? defaultMaskedError; + + /** IOPCIFIR[16] + * TX Lane N Calibration Error + */ + (rIOPCIFIR, bit(16)) ? defaultMaskedError; + + /** IOPCIFIR[17] + * TX Lane O Calibration Error + */ + (rIOPCIFIR, bit(17)) ? defaultMaskedError; + + /** IOPCIFIR[18] + * TX Lane P Calibration Error + */ + (rIOPCIFIR, bit(18)) ? defaultMaskedError; + + /** IOPCIFIR[19] + * RX Lane A Calibration Error + */ + (rIOPCIFIR, bit(19)) ? defaultMaskedError; + + /** IOPCIFIR[20] + * RX Lane B Calibration Error + */ + (rIOPCIFIR, bit(20)) ? defaultMaskedError; + + /** IOPCIFIR[21] + * RX Lane C Calibration Error + */ + (rIOPCIFIR, bit(21)) ? defaultMaskedError; + + /** IOPCIFIR[22] + * RX Lane D Calibration Error + */ + (rIOPCIFIR, bit(22)) ? defaultMaskedError; + + /** IOPCIFIR[23] + * RX Lane E Calibration Error + */ + (rIOPCIFIR, bit(23)) ? defaultMaskedError; + + /** IOPCIFIR[24] + * RX Lane F Calibration Error + */ + (rIOPCIFIR, bit(24)) ? defaultMaskedError; + + /** IOPCIFIR[25] + * RX Lane G Calibration Error + */ + (rIOPCIFIR, bit(25)) ? defaultMaskedError; + + /** IOPCIFIR[26] + * RX Lane H Calibration Error + */ + (rIOPCIFIR, bit(26)) ? defaultMaskedError; + + /** IOPCIFIR[27] + * RX Lane I Calibration Error + */ + (rIOPCIFIR, bit(27)) ? defaultMaskedError; + + /** IOPCIFIR[28] + * RX Lane J Calibration Error + */ + (rIOPCIFIR, bit(28)) ? defaultMaskedError; + + /** IOPCIFIR[29] + * RX Lane K Calibration Error + */ + (rIOPCIFIR, bit(29)) ? defaultMaskedError; + + /** IOPCIFIR[30] + * RX Lane L Calibration Error + */ + (rIOPCIFIR, bit(30)) ? defaultMaskedError; + + /** IOPCIFIR[31] + * RX Lane M Calibration Error + */ + (rIOPCIFIR, bit(31)) ? defaultMaskedError; + + /** IOPCIFIR[32] + * RX Lane N Calibration Error + */ + (rIOPCIFIR, bit(32)) ? defaultMaskedError; + + /** IOPCIFIR[33] + * RX Lane O Calibration Error + */ + (rIOPCIFIR, bit(33)) ? defaultMaskedError; + + /** IOPCIFIR[34] + * RX Lane P Calibration Error + */ + (rIOPCIFIR, bit(34)) ? defaultMaskedError; + + /** IOPCIFIR[35] + * SCOM FIR Parity Error 0 + */ + (rIOPCIFIR, bit(35)) ? defaultMaskedError; + + /** IOPCIFIR[36] + * SCOM FIR Parity Error 1 + */ + (rIOPCIFIR, bit(36)) ? defaultMaskedError; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "p9_common_pec_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_phb.rule b/src/usr/diag/prdf/common/plat/axone/axone_phb.rule new file mode 100644 index 000000000..844739ee2 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_phb.rule @@ -0,0 +1,764 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_phb.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_phb +{ + name "AXONE PHB target"; + targettype TYPE_PHB; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # P9 PHB target PHBNFIR + ############################################################################ + + register PHBNFIR + { + name "P9 PHB target PHBNFIR"; + scomaddr 0x04010c40; + reset (&, 0x04010c41); + mask (|, 0x04010c45); + capture group default; + }; + + register PHBNFIR_MASK + { + name "P9 PHB target PHBNFIR MASK"; + scomaddr 0x04010c43; + capture group default; + }; + + register PHBNFIR_ACT0 + { + name "P9 PHB target PHBNFIR ACT0"; + scomaddr 0x04010c46; + capture group default; + capture req nonzero("PHBNFIR"); + }; + + register PHBNFIR_ACT1 + { + name "P9 PHB target PHBNFIR ACT1"; + scomaddr 0x04010c47; + capture group default; + capture req nonzero("PHBNFIR"); + }; + + ############################################################################ + # P9 PHB target PCIFIR + ############################################################################ + + register PCIFIR + { + name "P9 PHB target PCIFIR"; + scomaddr 0x0d010840; + reset (&, 0x0d010841); + mask (|, 0x0d010845); + capture group default; + }; + + register PCIFIR_MASK + { + name "P9 PHB target PCIFIR MASK"; + scomaddr 0x0d010843; + capture group default; + }; + + register PCIFIR_ACT0 + { + name "P9 PHB target PCIFIR ACT0"; + scomaddr 0x0d010846; + capture group default; + capture req nonzero("PCIFIR"); + }; + + register PCIFIR_ACT1 + { + name "P9 PHB target PCIFIR ACT1"; + scomaddr 0x0d010847; + capture group default; + capture req nonzero("PCIFIR"); + }; + + ############################################################################ + # P9 PHB target ETUFIR + ############################################################################ + + register ETUFIR + { + name "P9 PHB target ETUFIR"; + scomaddr 0x0d010908; + reset (&, 0x0d010909); + mask (|, 0x0d01090d); + capture group default; + }; + + register ETUFIR_MASK + { + name "P9 PHB target ETUFIR MASK"; + scomaddr 0x0d01090b; + capture group default; + }; + + register ETUFIR_ACT0 + { + name "P9 PHB target ETUFIR ACT0"; + scomaddr 0x0d01090e; + capture group default; + capture req nonzero("ETUFIR"); + }; + + register ETUFIR_ACT1 + { + name "P9 PHB target ETUFIR ACT1"; + scomaddr 0x0d01090f; + capture group default; + capture req nonzero("ETUFIR"); + }; + +# Include registers not defined by the xml +.include "p9_common_phb_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Summary for PHB +################################################################################ + +rule rPHB +{ + CHECK_STOP: + summary( 0, rPHBNFIR ) | + summary( 1, rPCIFIR ) | + summary( 2, rETUFIR ); + + RECOVERABLE: + summary( 0, rPHBNFIR ) | + summary( 1, rPCIFIR ) | + summary( 2, rETUFIR ); + +}; + +group gPHB attntype CHECK_STOP, RECOVERABLE + filter singlebit +{ + (rPHB, bit(0)) ? analyzePHBNFIR; + (rPHB, bit(1)) ? analyzePCIFIR; + (rPHB, bit(2)) ? analyzeETUFIR; +}; + +################################################################################ +# P9 PHB target PHBNFIR +################################################################################ + +rule rPHBNFIR +{ + CHECK_STOP: + PHBNFIR & ~PHBNFIR_MASK & ~PHBNFIR_ACT0 & ~PHBNFIR_ACT1; + RECOVERABLE: + PHBNFIR & ~PHBNFIR_MASK & ~PHBNFIR_ACT0 & PHBNFIR_ACT1; +}; + +group gPHBNFIR + filter singlebit, + cs_root_cause +{ + /** PHBNFIR[0] + * BAR Parity Error + */ + (rPHBNFIR, bit(0)) ? self_th_1; + + /** PHBNFIR[1] + * Parity Errors on Registers besides BAR + */ + (rPHBNFIR, bit(1)) ? externalAttention; + + /** PHBNFIR[2] + * Power Bus to PEC CE + */ + (rPHBNFIR, bit(2)) ? self_th_32perDay; + + /** PHBNFIR[3] + * Power Bus to PEC UE + */ + (rPHBNFIR, bit(3)) ? externalAttention; + + /** PHBNFIR[4] + * Power Bus to PEC SUE + */ + (rPHBNFIR, bit(4)) ? externalAttention; + + /** PHBNFIR[5] + * Array CE + */ + (rPHBNFIR, bit(5)) ? self_th_32perDay; + + /** PHBNFIR[6] + * Array UE + */ + (rPHBNFIR, bit(6)) ? externalAttention; + + /** PHBNFIR[7] + * Array SUE + */ + (rPHBNFIR, bit(7)) ? externalAttention; + + /** PHBNFIR[8] + * Register Array Parity Error + */ + (rPHBNFIR, bit(8)) ? self_th_1; + + /** PHBNFIR[9] + * Power Bus Interface Parity Error + */ + (rPHBNFIR, bit(9)) ? self_th_1; + + /** PHBNFIR[10] + * Power Bus Data Hang + */ + (rPHBNFIR, bit(10)) ? defaultMaskedError; + + /** PHBNFIR[11] + * Power Bus Hang + */ + (rPHBNFIR, bit(11)) ? defaultMaskedError; + + /** PHBNFIR[12] + * RD ARE Error + */ + (rPHBNFIR, bit(12)) ? externalAttention; + + /** PHBNFIR[13] + * NonRd ARE Error + */ + (rPHBNFIR, bit(13)) ? externalAttention; + + /** PHBNFIR[14] + * PCI Hang + */ + (rPHBNFIR, bit(14)) ? externalAttention; + + /** PHBNFIR[15] + * PCI Clock Error + */ + (rPHBNFIR, bit(15)) ? externalAttention; + + /** PHBNFIR[16] + * AIB Fence + */ + (rPHBNFIR, bit(16)) ? externalAttention; + + /** PHBNFIR[17] + * Hardware Error + */ + (rPHBNFIR, bit(17)) ? self_th_1; + + /** PHBNFIR[18] + * Unsolicited Power Bus Data + */ + (rPHBNFIR, bit(18)) ? level2_th_1; + + /** PHBNFIR[19] + * UnExpected Combined Response + */ + (rPHBNFIR, bit(19)) ? level2_th_1; + + /** PHBNFIR[20] + * Invalid Combined Response + */ + (rPHBNFIR, bit(20)) ? level2_M_proc_L_th_1; + + /** PHBNFIR[21] + * Power Bus Unsupported Size + */ + (rPHBNFIR, bit(21)) ? level2_M_proc_L_th_1; + + /** PHBNFIR[22] + * Power Bus Unsupported Command + */ + (rPHBNFIR, bit(22)) ? level2_M_proc_L_th_1; + + /** PHBNFIR[23] + * PBAIB error + */ + (rPHBNFIR, bit(23)) ? externalAttention; + + /** PHBNFIR[24] + * CAPP Error + */ + (rPHBNFIR, bit(24)) ? externalAttention; + + /** PHBNFIR[25] + * NMMU Error + */ + (rPHBNFIR, bit(25)) ? externalAttention; + + /** PHBNFIR[26] + * Software Defined + */ + (rPHBNFIR, bit(26)) ? externalAttention; + + /** PHBNFIR[27] + * PEC SCOM Engine Error + */ + (rPHBNFIR, bit(27)) ? defaultMaskedError; + + /** PHBNFIR[28] + * scom error + */ + (rPHBNFIR, bit(28)) ? defaultMaskedError; + + /** PHBNFIR[29] + * scom error + */ + (rPHBNFIR, bit(29)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 PHB target PCIFIR +################################################################################ + +rule rPCIFIR +{ + CHECK_STOP: + PCIFIR & ~PCIFIR_MASK & ~PCIFIR_ACT0 & ~PCIFIR_ACT1; + RECOVERABLE: + PCIFIR & ~PCIFIR_MASK & ~PCIFIR_ACT0 & PCIFIR_ACT1; +}; + +group gPCIFIR + filter singlebit, + cs_root_cause +{ + /** PCIFIR[0] + * PBAIB register parity error + */ + (rPCIFIR, bit(0)) ? externalAttention; + + /** PCIFIR[1] + * Hardware error + */ + (rPCIFIR, bit(1)) ? self_th_1; + + /** PCIFIR[2] + * AIB interface error + */ + (rPCIFIR, bit(2)) ? externalAttention; + + /** PCIFIR[3] + * ETU reset error + */ + (rPCIFIR, bit(3)) ? externalAttention; + + /** PCIFIR[4] + * PEC scom error + */ + (rPCIFIR, bit(4)) ? defaultMaskedError; + + /** PCIFIR[5] + * scom error + */ + (rPCIFIR, bit(5)) ? defaultMaskedError; + + /** PCIFIR[6] + * scom error + */ + (rPCIFIR, bit(6)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 PHB target ETUFIR +################################################################################ + +rule rETUFIR +{ + CHECK_STOP: + ETUFIR & ~ETUFIR_MASK & ~ETUFIR_ACT0 & ~ETUFIR_ACT1; + RECOVERABLE: + ETUFIR & ~ETUFIR_MASK & ~ETUFIR_ACT0 & ETUFIR_ACT1; +}; + +group gETUFIR + filter singlebit, + cs_root_cause +{ + /** ETUFIR[0] + * AIB_COMMAND_INVALID + */ + (rETUFIR, bit(0)) ? defaultMaskedError; + + /** ETUFIR[1] + * AIB_ADDRESS_INVALID + */ + (rETUFIR, bit(1)) ? defaultMaskedError; + + /** ETUFIR[2] + * AIB_ACCESS_ERROR + */ + (rETUFIR, bit(2)) ? defaultMaskedError; + + /** ETUFIR[3] + * PAPR_OUTBOUND_INJECT_ERROR + */ + (rETUFIR, bit(3)) ? defaultMaskedError; + + /** ETUFIR[4] + * AIB_FATAL_CLASS_ERROR + */ + (rETUFIR, bit(4)) ? defaultMaskedError; + + /** ETUFIR[5] + * AIB_INF_CLASS_ERROR + */ + (rETUFIR, bit(5)) ? defaultMaskedError; + + /** ETUFIR[6] + * spare + */ + (rETUFIR, bit(6)) ? defaultMaskedError; + + /** ETUFIR[7] + * PE_STOP_STATE_SIGNALED + */ + (rETUFIR, bit(7)) ? defaultMaskedError; + + /** ETUFIR[8] + * OUT_COMMON_ARRAY_FATAL_ERROR + */ + (rETUFIR, bit(8)) ? defaultMaskedError; + + /** ETUFIR[9] + * OUT_COMMON_LATCH_FATAL_ERROR + */ + (rETUFIR, bit(9)) ? defaultMaskedError; + + /** ETUFIR[10] + * OUT_COMMON_LOGIC_FATAL_ERROR + */ + (rETUFIR, bit(10)) ? defaultMaskedError; + + /** ETUFIR[11] + * BLIF_OUT_INTERFACE_PARITY_ERROR + */ + (rETUFIR, bit(11)) ? defaultMaskedError; + + /** ETUFIR[12] + * CFG_WRITE_CA_OR_UR_RESPONSE + */ + (rETUFIR, bit(12)) ? defaultMaskedError; + + /** ETUFIR[13] + * MMIO_REQUEST_TIMEOUT + */ + (rETUFIR, bit(13)) ? defaultMaskedError; + + /** ETUFIR[14] + * OUT_RRB_SOURCED_ERROR + */ + (rETUFIR, bit(14)) ? defaultMaskedError; + + /** ETUFIR[15] + * CFG_LOGIC_SIGNALED_ERROR + */ + (rETUFIR, bit(15)) ? defaultMaskedError; + + /** ETUFIR[16] + * RSB_REG_REQUEST_ADDRESS_ERROR + */ + (rETUFIR, bit(16)) ? defaultMaskedError; + + /** ETUFIR[17] + * RSB_FDA_FATAL_ERROR + */ + (rETUFIR, bit(17)) ? defaultMaskedError; + + /** ETUFIR[18] + * RSB_FDA_INF_ERROR + */ + (rETUFIR, bit(18)) ? defaultMaskedError; + + /** ETUFIR[19] + * RSB_FDB_FATAL_ERROR + */ + (rETUFIR, bit(19)) ? defaultMaskedError; + + /** ETUFIR[20] + * RSB_FDB_INF_ERROR + */ + (rETUFIR, bit(20)) ? defaultMaskedError; + + /** ETUFIR[21] + * RSB_ERR_FATAL_ERROR + */ + (rETUFIR, bit(21)) ? defaultMaskedError; + + /** ETUFIR[22] + * RSB_ERR_INF_ERROR + */ + (rETUFIR, bit(22)) ? defaultMaskedError; + + /** ETUFIR[23] + * RSB_DBG_FATAL_ERROR + */ + (rETUFIR, bit(23)) ? defaultMaskedError; + + /** ETUFIR[24] + * RSB_DBG_INF_ERROR + */ + (rETUFIR, bit(24)) ? defaultMaskedError; + + /** ETUFIR[25] + * PCIE_REQUEST_ACCESS_ERROR + */ + (rETUFIR, bit(25)) ? defaultMaskedError; + + /** ETUFIR[26] + * RSB_BUS_LOGIC_ERROR + */ + (rETUFIR, bit(26)) ? defaultMaskedError; + + /** ETUFIR[27] + * RSB_UVI_FATAL_ERROR + */ + (rETUFIR, bit(27)) ? defaultMaskedError; + + /** ETUFIR[28] + * RSB_UVI_INF_ERROR + */ + (rETUFIR, bit(28)) ? defaultMaskedError; + + /** ETUFIR[29] + * SCOM_FATAL_ERROR + */ + (rETUFIR, bit(29)) ? defaultMaskedError; + + /** ETUFIR[30] + * SCOM_INF_ERROR + */ + (rETUFIR, bit(30)) ? defaultMaskedError; + + /** ETUFIR[31] + * PCIE_MACRO_ERROR_ACTIVE_STATUS + */ + (rETUFIR, bit(31)) ? defaultMaskedError; + + /** ETUFIR[32] + * ARB_IODA_FATAL_ERROR + */ + (rETUFIR, bit(32)) ? defaultMaskedError; + + /** ETUFIR[33] + * ARB_MSI_PE_MATCH_ERROR + */ + (rETUFIR, bit(33)) ? defaultMaskedError; + + /** ETUFIR[34] + * ARB_MSI_ADDRESS_ERROR + */ + (rETUFIR, bit(34)) ? defaultMaskedError; + + /** ETUFIR[35] + * ARB_TVT_ERROR + */ + (rETUFIR, bit(35)) ? defaultMaskedError; + + /** ETUFIR[36] + * ARB_RCVD_FATAL_ERROR_MSG + */ + (rETUFIR, bit(36)) ? defaultMaskedError; + + /** ETUFIR[37] + * ARB_RCVD_NONFATAL_ERROR_MSG + */ + (rETUFIR, bit(37)) ? defaultMaskedError; + + /** ETUFIR[38] + * ARB_RCVD_CORRECTIBLE_ERROR_MSG + */ + (rETUFIR, bit(38)) ? defaultMaskedError; + + /** ETUFIR[39] + * PAPR_INBOUND_INJECT_ERROR + */ + (rETUFIR, bit(39)) ? defaultMaskedError; + + /** ETUFIR[40] + * ARB_COMMON_FATAL_ERROR + */ + (rETUFIR, bit(40)) ? defaultMaskedError; + + /** ETUFIR[41] + * ARB_TABLE_BAR_DISABLED_ERROR + */ + (rETUFIR, bit(41)) ? defaultMaskedError; + + /** ETUFIR[42] + * ARB_BLIF_COMPLETION_ERROR + */ + (rETUFIR, bit(42)) ? defaultMaskedError; + + /** ETUFIR[43] + * ARB_PCT_TIMEOUT_ERROR + */ + (rETUFIR, bit(43)) ? defaultMaskedError; + + /** ETUFIR[44] + * ARB_ECC_CORRECTABLE_ERROR + */ + (rETUFIR, bit(44)) ? defaultMaskedError; + + /** ETUFIR[45] + * ARB_ECC_UNCORRECTABLE_ERROR + */ + (rETUFIR, bit(45)) ? defaultMaskedError; + + /** ETUFIR[46] + * ARB_TLP_POISON_SIGNALED + */ + (rETUFIR, bit(46)) ? defaultMaskedError; + + /** ETUFIR[47] + * ARB_RTT_PENUM_INVALID_ERROR + */ + (rETUFIR, bit(47)) ? defaultMaskedError; + + /** ETUFIR[48] + * MRG_COMMON_FATAL_ERROR + */ + (rETUFIR, bit(48)) ? defaultMaskedError; + + /** ETUFIR[49] + * MRG_TABLE_BAR_DISABLED_ERROR + */ + (rETUFIR, bit(49)) ? defaultMaskedError; + + /** ETUFIR[50] + * MRG_ECC_CORRECTABLE_ERROR + */ + (rETUFIR, bit(50)) ? defaultMaskedError; + + /** ETUFIR[51] + * MRG_ECC_UNCORRECTABLE_ERROR + */ + (rETUFIR, bit(51)) ? defaultMaskedError; + + /** ETUFIR[52] + * MRG_AIB2_TX_TIMEOUT_ERROR + */ + (rETUFIR, bit(52)) ? defaultMaskedError; + + /** ETUFIR[53] + * MRG_MRT_ERROR + */ + (rETUFIR, bit(53)) ? defaultMaskedError; + + /** ETUFIR[54:55] + * spare + */ + (rETUFIR, bit(54|55)) ? defaultMaskedError; + + /** ETUFIR[56] + * TCE_IODA_PAGE_ACCESS_ERROR + */ + (rETUFIR, bit(56)) ? defaultMaskedError; + + /** ETUFIR[57] + * TCE_REQUEST_TIMEOUT_ERROR + */ + (rETUFIR, bit(57)) ? defaultMaskedError; + + /** ETUFIR[58] + * TCE_UNEXPECTED_RESPONSE_ERROR + */ + (rETUFIR, bit(58)) ? defaultMaskedError; + + /** ETUFIR[59] + * TCE_COMMON_FATAL_ERROR + */ + (rETUFIR, bit(59)) ? defaultMaskedError; + + /** ETUFIR[60] + * TCE_ECC_CORRECTABLE_ERROR + */ + (rETUFIR, bit(60)) ? defaultMaskedError; + + /** ETUFIR[61] + * TCE_ECC_UNCORRECTABLE_ERROR + */ + (rETUFIR, bit(61)) ? defaultMaskedError; + + /** ETUFIR[62] + * spare + */ + (rETUFIR, bit(62)) ? defaultMaskedError; + + /** ETUFIR[63] + * FIR_INTERNAL_PARITY_ERROR + */ + (rETUFIR, bit(63)) ? defaultMaskedError; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "p9_common_phb_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_proc.rule b/src/usr/diag/prdf/common/plat/axone/axone_proc.rule new file mode 100644 index 000000000..c37c103be --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_proc.rule @@ -0,0 +1,7128 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_proc.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_proc +{ + name "AXONE PROC target"; + targettype TYPE_PROC; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + +# Import signatures +.include "prdfP9ProcMbCommonExtraSig.H"; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # Global Attention FIR + ############################################################################ + + register GLOBAL_CS_FIR + { + name "Global Checkstop Attention FIR"; + scomaddr 0x500F001C; + capture group default; + }; + + register GLOBAL_RE_FIR + { + name "Global Recoverable Attention FIR"; + scomaddr 0x500F001B; + capture group default; + }; + + ############################################################################ + # Global Unit Checkstop FIR + ############################################################################ + + register GLOBAL_UCS_FIR + { + name "Global Unit Checkstop FIR"; + scomaddr 0x50040018; + capture group default; + }; + + ############################################################################ + # Global Host Attention FIR + ############################################################################ + + register GLOBAL_HA_FIR + { + name "Global Host Attention FIR"; + scomaddr 0x50040009; + capture group default; + }; + + ############################################################################ + # TP Chiplet FIR + ############################################################################ + + register TP_CHIPLET_CS_FIR + { + name "TP Chiplet Checkstop FIR"; + scomaddr 0x01040000; + capture group default; + }; + + register TP_CHIPLET_RE_FIR + { + name "TP Chiplet Recoverable FIR"; + scomaddr 0x01040001; + capture group default; + }; + + register TP_CHIPLET_FIR_MASK + { + name "TP Chiplet FIR MASK"; + scomaddr 0x01040002; + capture group default; + }; + + ############################################################################ + # P9 chip TP_LFIR + ############################################################################ + + register TP_LFIR + { + name "P9 chip TP_LFIR"; + scomaddr 0x0104000a; + reset (&, 0x0104000b); + mask (|, 0x0104000f); + capture group default; + }; + + register TP_LFIR_MASK + { + name "P9 chip TP_LFIR MASK"; + scomaddr 0x0104000d; + capture group default; + }; + + register TP_LFIR_ACT0 + { + name "P9 chip TP_LFIR ACT0"; + scomaddr 0x01040010; + capture group default; + capture req nonzero("TP_LFIR"); + }; + + register TP_LFIR_ACT1 + { + name "P9 chip TP_LFIR ACT1"; + scomaddr 0x01040011; + capture group default; + capture req nonzero("TP_LFIR"); + }; + + ############################################################################ + # P9 chip OCCFIR + ############################################################################ + + register OCCFIR + { + name "P9 chip OCCFIR"; + scomaddr 0x01010800; + reset (&, 0x01010801); + mask (|, 0x01010805); + capture group default; + }; + + register OCCFIR_MASK + { + name "P9 chip OCCFIR MASK"; + scomaddr 0x01010803; + capture group default; + }; + + register OCCFIR_ACT0 + { + name "P9 chip OCCFIR ACT0"; + scomaddr 0x01010806; + capture group default; + capture req nonzero("OCCFIR"); + }; + + register OCCFIR_ACT1 + { + name "P9 chip OCCFIR ACT1"; + scomaddr 0x01010807; + capture group default; + capture req nonzero("OCCFIR"); + }; + + ############################################################################ + # N0 Chiplet FIR + ############################################################################ + + register N0_CHIPLET_CS_FIR + { + name "N0 Chiplet Checkstop FIR"; + scomaddr 0x02040000; + capture group default; + }; + + register N0_CHIPLET_RE_FIR + { + name "N0 Chiplet Recoverable FIR"; + scomaddr 0x02040001; + capture group default; + }; + + register N0_CHIPLET_FIR_MASK + { + name "N0 Chiplet FIR MASK"; + scomaddr 0x02040002; + capture group default; + }; + + ############################################################################ + # N0 Chiplet Unit Checkstop FIR + ############################################################################ + + register N0_CHIPLET_UCS_FIR + { + name "N0 Chiplet Unit Checkstop FIR"; + scomaddr 0x02040018; + capture group default; + }; + + register N0_CHIPLET_UCS_FIR_MASK + { + name "N0 Chiplet Unit Checkstop FIR MASK"; + scomaddr 0x02040019; + capture group default; + }; + + ############################################################################ + # P9 chip N0_LFIR + ############################################################################ + + register N0_LFIR + { + name "P9 chip N0_LFIR"; + scomaddr 0x0204000a; + reset (&, 0x0204000b); + mask (|, 0x0204000f); + capture group default; + }; + + register N0_LFIR_MASK + { + name "P9 chip N0_LFIR MASK"; + scomaddr 0x0204000d; + capture group default; + }; + + register N0_LFIR_ACT0 + { + name "P9 chip N0_LFIR ACT0"; + scomaddr 0x02040010; + capture group default; + capture req nonzero("N0_LFIR"); + }; + + register N0_LFIR_ACT1 + { + name "P9 chip N0_LFIR ACT1"; + scomaddr 0x02040011; + capture group default; + capture req nonzero("N0_LFIR"); + }; + + ############################################################################ + # P9 chip NXCQFIR + ############################################################################ + + register NXCQFIR + { + name "P9 chip NXCQFIR"; + scomaddr 0x02011080; + reset (&, 0x02011081); + mask (|, 0x02011085); + capture group default; + }; + + register NXCQFIR_MASK + { + name "P9 chip NXCQFIR MASK"; + scomaddr 0x02011083; + capture group default; + }; + + register NXCQFIR_ACT0 + { + name "P9 chip NXCQFIR ACT0"; + scomaddr 0x02011086; + capture group default; + capture req nonzero("NXCQFIR"); + }; + + register NXCQFIR_ACT1 + { + name "P9 chip NXCQFIR ACT1"; + scomaddr 0x02011087; + capture group default; + capture req nonzero("NXCQFIR"); + }; + + ############################################################################ + # P9 chip NXDMAENGFIR + ############################################################################ + + register NXDMAENGFIR + { + name "P9 chip NXDMAENGFIR"; + scomaddr 0x02011100; + reset (&, 0x02011101); + mask (|, 0x02011105); + capture group default; + }; + + register NXDMAENGFIR_MASK + { + name "P9 chip NXDMAENGFIR MASK"; + scomaddr 0x02011103; + capture group default; + }; + + register NXDMAENGFIR_ACT0 + { + name "P9 chip NXDMAENGFIR ACT0"; + scomaddr 0x02011106; + capture group default; + capture req nonzero("NXDMAENGFIR"); + }; + + register NXDMAENGFIR_ACT1 + { + name "P9 chip NXDMAENGFIR ACT1"; + scomaddr 0x02011107; + capture group default; + capture req nonzero("NXDMAENGFIR"); + }; + + ############################################################################ + # N1 Chiplet FIR + ############################################################################ + + register N1_CHIPLET_CS_FIR + { + name "N1 Chiplet Checkstop FIR"; + scomaddr 0x03040000; + capture group default; + }; + + register N1_CHIPLET_RE_FIR + { + name "N1 Chiplet Recoverable FIR"; + scomaddr 0x03040001; + capture group default; + }; + + register N1_CHIPLET_FIR_MASK + { + name "N1 Chiplet FIR MASK"; + scomaddr 0x03040002; + capture group default; + }; + + ############################################################################ + # N1 Chiplet Unit Checkstop FIR + ############################################################################ + + register N1_CHIPLET_UCS_FIR + { + name "N1 Chiplet Unit Checkstop FIR"; + scomaddr 0x03040018; + capture group default; + }; + + register N1_CHIPLET_UCS_FIR_MASK + { + name "N1 Chiplet Unit Checkstop FIR MASK"; + scomaddr 0x03040019; + capture group default; + }; + + ############################################################################ + # N1 Chiplet Host Attention FIR + ############################################################################ + + register N1_CHIPLET_HA_FIR + { + name "N1 Chiplet Host Attention FIR"; + scomaddr 0x03040009; + capture group default; + }; + + register N1_CHIPLET_HA_FIR_MASK + { + name "N1 Chiplet Host Attention FIR MASK"; + scomaddr 0x0304001a; + capture group default; + }; + + ############################################################################ + # P9 chip N1_LFIR + ############################################################################ + + register N1_LFIR + { + name "P9 chip N1_LFIR"; + scomaddr 0x0304000a; + reset (&, 0x0304000b); + mask (|, 0x0304000f); + capture group default; + }; + + register N1_LFIR_MASK + { + name "P9 chip N1_LFIR MASK"; + scomaddr 0x0304000d; + capture group default; + }; + + register N1_LFIR_ACT0 + { + name "P9 chip N1_LFIR ACT0"; + scomaddr 0x03040010; + capture group default; + capture req nonzero("N1_LFIR"); + }; + + register N1_LFIR_ACT1 + { + name "P9 chip N1_LFIR ACT1"; + scomaddr 0x03040011; + capture group default; + capture req nonzero("N1_LFIR"); + }; + + ############################################################################ + # P9 chip MCDFIR 0 + ############################################################################ + + register MCDFIR_0 + { + name "P9 chip MCDFIR 0"; + scomaddr 0x03011000; + reset (&, 0x03011001); + mask (|, 0x03011005); + capture group default; + }; + + register MCDFIR_0_MASK + { + name "P9 chip MCDFIR 0 MASK"; + scomaddr 0x03011003; + capture group default; + }; + + register MCDFIR_0_ACT0 + { + name "P9 chip MCDFIR 0 ACT0"; + scomaddr 0x03011006; + capture group default; + capture req nonzero("MCDFIR_0"); + }; + + register MCDFIR_0_ACT1 + { + name "P9 chip MCDFIR 0 ACT1"; + scomaddr 0x03011007; + capture group default; + capture req nonzero("MCDFIR_0"); + }; + + ############################################################################ + # P9 chip MCDFIR 1 + ############################################################################ + + register MCDFIR_1 + { + name "P9 chip MCDFIR 1"; + scomaddr 0x03011400; + reset (&, 0x03011401); + mask (|, 0x03011405); + capture group default; + }; + + register MCDFIR_1_MASK + { + name "P9 chip MCDFIR 1 MASK"; + scomaddr 0x03011403; + capture group default; + }; + + register MCDFIR_1_ACT0 + { + name "P9 chip MCDFIR 1 ACT0"; + scomaddr 0x03011406; + capture group default; + capture req nonzero("MCDFIR_1"); + }; + + register MCDFIR_1_ACT1 + { + name "P9 chip MCDFIR 1 ACT1"; + scomaddr 0x03011407; + capture group default; + capture req nonzero("MCDFIR_1"); + }; + + ############################################################################ + # P9 chip VASFIR + ############################################################################ + + register VASFIR + { + name "P9 chip VASFIR"; + scomaddr 0x03011800; + reset (&, 0x03011801); + mask (|, 0x03011805); + capture group default; + }; + + register VASFIR_MASK + { + name "P9 chip VASFIR MASK"; + scomaddr 0x03011803; + capture group default; + }; + + register VASFIR_ACT0 + { + name "P9 chip VASFIR ACT0"; + scomaddr 0x03011806; + capture group default; + capture req nonzero("VASFIR"); + }; + + register VASFIR_ACT1 + { + name "P9 chip VASFIR ACT1"; + scomaddr 0x03011807; + capture group default; + capture req nonzero("VASFIR"); + }; + + ############################################################################ + # N2 Chiplet FIR + ############################################################################ + + register N2_CHIPLET_CS_FIR + { + name "N2 Chiplet Checkstop FIR"; + scomaddr 0x04040000; + capture group default; + }; + + register N2_CHIPLET_RE_FIR + { + name "N2 Chiplet Recoverable FIR"; + scomaddr 0x04040001; + capture group default; + }; + + register N2_CHIPLET_FIR_MASK + { + name "N2 Chiplet FIR MASK"; + scomaddr 0x04040002; + capture group default; + }; + + ############################################################################ + # P9 chip N2_LFIR + ############################################################################ + + register N2_LFIR + { + name "P9 chip N2_LFIR"; + scomaddr 0x0404000a; + reset (&, 0x0404000b); + mask (|, 0x0404000f); + capture group default; + }; + + register N2_LFIR_MASK + { + name "P9 chip N2_LFIR MASK"; + scomaddr 0x0404000d; + capture group default; + }; + + register N2_LFIR_ACT0 + { + name "P9 chip N2_LFIR ACT0"; + scomaddr 0x04040010; + capture group default; + capture req nonzero("N2_LFIR"); + }; + + register N2_LFIR_ACT1 + { + name "P9 chip N2_LFIR ACT1"; + scomaddr 0x04040011; + capture group default; + capture req nonzero("N2_LFIR"); + }; + + ############################################################################ + # P9 chip PSIFIR + ############################################################################ + + register PSIFIR + { + name "P9 chip PSIFIR"; + scomaddr 0x04011800; + reset (&, 0x04011801); + mask (|, 0x04011805); + capture group default; + }; + + register PSIFIR_MASK + { + name "P9 chip PSIFIR MASK"; + scomaddr 0x04011803; + capture group default; + }; + + register PSIFIR_ACT0 + { + name "P9 chip PSIFIR ACT0"; + scomaddr 0x04011806; + capture group default; + capture req nonzero("PSIFIR"); + }; + + register PSIFIR_ACT1 + { + name "P9 chip PSIFIR ACT1"; + scomaddr 0x04011807; + capture group default; + capture req nonzero("PSIFIR"); + }; + + ############################################################################ + # N3 Chiplet FIR + ############################################################################ + + register N3_CHIPLET_CS_FIR + { + name "N3 Chiplet Checkstop FIR"; + scomaddr 0x05040000; + capture group default; + }; + + register N3_CHIPLET_RE_FIR + { + name "N3 Chiplet Recoverable FIR"; + scomaddr 0x05040001; + capture group default; + }; + + register N3_CHIPLET_FIR_MASK + { + name "N3 Chiplet FIR MASK"; + scomaddr 0x05040002; + capture group default; + }; + + ############################################################################ + # N3 Chiplet Unit Checkstop FIR + ############################################################################ + + register N3_CHIPLET_UCS_FIR + { + name "N3 Chiplet Unit Checkstop FIR"; + scomaddr 0x05040018; + capture group default; + }; + + register N3_CHIPLET_UCS_FIR_MASK + { + name "N3 Chiplet Unit Checkstop FIR MASK"; + scomaddr 0x05040019; + capture group default; + }; + + ############################################################################ + # N3 Chiplet Host Attention FIR + ############################################################################ + + register N3_CHIPLET_HA_FIR + { + name "N3 Chiplet Host Attention FIR"; + scomaddr 0x05040009; + capture group default; + }; + + register N3_CHIPLET_HA_FIR_MASK + { + name "N3 Chiplet Host Attention FIR MASK"; + scomaddr 0x0504001a; + capture group default; + }; + + ############################################################################ + # P9 chip N3_LFIR + ############################################################################ + + register N3_LFIR + { + name "P9 chip N3_LFIR"; + scomaddr 0x0504000a; + reset (&, 0x0504000b); + mask (|, 0x0504000f); + capture group default; + }; + + register N3_LFIR_MASK + { + name "P9 chip N3_LFIR MASK"; + scomaddr 0x0504000d; + capture group default; + }; + + register N3_LFIR_ACT0 + { + name "P9 chip N3_LFIR ACT0"; + scomaddr 0x05040010; + capture group default; + capture req nonzero("N3_LFIR"); + }; + + register N3_LFIR_ACT1 + { + name "P9 chip N3_LFIR ACT1"; + scomaddr 0x05040011; + capture group default; + capture req nonzero("N3_LFIR"); + }; + + ############################################################################ + # P9 chip PBWESTFIR + ############################################################################ + + register PBWESTFIR + { + name "P9 chip PBWESTFIR"; + scomaddr 0x05011800; + reset (&, 0x05011801); + mask (|, 0x05011805); + capture group default; + }; + + register PBWESTFIR_MASK + { + name "P9 chip PBWESTFIR MASK"; + scomaddr 0x05011803; + capture group default; + }; + + register PBWESTFIR_ACT0 + { + name "P9 chip PBWESTFIR ACT0"; + scomaddr 0x05011806; + capture group default; + capture req nonzero("PBWESTFIR"); + }; + + register PBWESTFIR_ACT1 + { + name "P9 chip PBWESTFIR ACT1"; + scomaddr 0x05011807; + capture group default; + capture req nonzero("PBWESTFIR"); + }; + + ############################################################################ + # P9 chip PBCENTFIR + ############################################################################ + + register PBCENTFIR + { + name "P9 chip PBCENTFIR"; + scomaddr 0x05011c00; + reset (&, 0x05011c01); + mask (|, 0x05011c05); + capture group default; + }; + + register PBCENTFIR_MASK + { + name "P9 chip PBCENTFIR MASK"; + scomaddr 0x05011c03; + capture group default; + }; + + register PBCENTFIR_ACT0 + { + name "P9 chip PBCENTFIR ACT0"; + scomaddr 0x05011c06; + capture group default; + capture req nonzero("PBCENTFIR"); + }; + + register PBCENTFIR_ACT1 + { + name "P9 chip PBCENTFIR ACT1"; + scomaddr 0x05011c07; + capture group default; + capture req nonzero("PBCENTFIR"); + }; + + ############################################################################ + # P9 chip PBEASTFIR + ############################################################################ + + register PBEASTFIR + { + name "P9 chip PBEASTFIR"; + scomaddr 0x05012000; + reset (&, 0x05012001); + mask (|, 0x05012005); + capture group default; + }; + + register PBEASTFIR_MASK + { + name "P9 chip PBEASTFIR MASK"; + scomaddr 0x05012003; + capture group default; + }; + + register PBEASTFIR_ACT0 + { + name "P9 chip PBEASTFIR ACT0"; + scomaddr 0x05012006; + capture group default; + capture req nonzero("PBEASTFIR"); + }; + + register PBEASTFIR_ACT1 + { + name "P9 chip PBEASTFIR ACT1"; + scomaddr 0x05012007; + capture group default; + capture req nonzero("PBEASTFIR"); + }; + + ############################################################################ + # P9 chip PBPPEFIR + ############################################################################ + + register PBPPEFIR + { + name "P9 chip PBPPEFIR"; + scomaddr 0x05012400; + reset (&, 0x05012401); + mask (|, 0x05012405); + capture group default; + }; + + register PBPPEFIR_MASK + { + name "P9 chip PBPPEFIR MASK"; + scomaddr 0x05012403; + capture group default; + }; + + register PBPPEFIR_ACT0 + { + name "P9 chip PBPPEFIR ACT0"; + scomaddr 0x05012406; + capture group default; + capture req nonzero("PBPPEFIR"); + }; + + register PBPPEFIR_ACT1 + { + name "P9 chip PBPPEFIR ACT1"; + scomaddr 0x05012407; + capture group default; + capture req nonzero("PBPPEFIR"); + }; + + ############################################################################ + # P9 chip PBAFIR + ############################################################################ + + register PBAFIR + { + name "P9 chip PBAFIR"; + scomaddr 0x05012840; + reset (&, 0x05012841); + mask (|, 0x05012845); + capture group default; + }; + + register PBAFIR_MASK + { + name "P9 chip PBAFIR MASK"; + scomaddr 0x05012843; + capture group default; + }; + + register PBAFIR_ACT0 + { + name "P9 chip PBAFIR ACT0"; + scomaddr 0x05012846; + capture group default; + capture req nonzero("PBAFIR"); + }; + + register PBAFIR_ACT1 + { + name "P9 chip PBAFIR ACT1"; + scomaddr 0x05012847; + capture group default; + capture req nonzero("PBAFIR"); + }; + + ############################################################################ + # P9 chip PSIHBFIR + ############################################################################ + + register PSIHBFIR + { + name "P9 chip PSIHBFIR"; + scomaddr 0x05012900; + reset (&, 0x05012901); + mask (|, 0x05012905); + capture group default; + }; + + register PSIHBFIR_MASK + { + name "P9 chip PSIHBFIR MASK"; + scomaddr 0x05012903; + capture group default; + }; + + register PSIHBFIR_ACT0 + { + name "P9 chip PSIHBFIR ACT0"; + scomaddr 0x05012906; + capture group default; + capture req nonzero("PSIHBFIR"); + }; + + register PSIHBFIR_ACT1 + { + name "P9 chip PSIHBFIR ACT1"; + scomaddr 0x05012907; + capture group default; + capture req nonzero("PSIHBFIR"); + }; + + ############################################################################ + # P9 chip ENHCAFIR + ############################################################################ + + register ENHCAFIR + { + name "P9 chip ENHCAFIR"; + scomaddr 0x05012940; + reset (&, 0x05012941); + mask (|, 0x05012945); + capture group default; + }; + + register ENHCAFIR_MASK + { + name "P9 chip ENHCAFIR MASK"; + scomaddr 0x05012943; + capture group default; + }; + + register ENHCAFIR_ACT0 + { + name "P9 chip ENHCAFIR ACT0"; + scomaddr 0x05012946; + capture group default; + capture req nonzero("ENHCAFIR"); + }; + + register ENHCAFIR_ACT1 + { + name "P9 chip ENHCAFIR ACT1"; + scomaddr 0x05012947; + capture group default; + capture req nonzero("ENHCAFIR"); + }; + + ############################################################################ + # P9 chip PBAMFIR + ############################################################################ + + register PBAMFIR + { + name "P9 chip PBAMFIR"; + scomaddr 0x050129c0; + reset (&, 0x050129c1); + mask (|, 0x050129c5); + capture group default; + }; + + register PBAMFIR_MASK + { + name "P9 chip PBAMFIR MASK"; + scomaddr 0x050129c3; + capture group default; + }; + + register PBAMFIR_ACT0 + { + name "P9 chip PBAMFIR ACT0"; + scomaddr 0x050129c6; + capture group default; + capture req nonzero("PBAMFIR"); + }; + + register PBAMFIR_ACT1 + { + name "P9 chip PBAMFIR ACT1"; + scomaddr 0x050129c7; + capture group default; + capture req nonzero("PBAMFIR"); + }; + + ############################################################################ + # P9 chip NMMUCQFIR + ############################################################################ + + register NMMUCQFIR + { + name "P9 chip NMMUCQFIR"; + scomaddr 0x05012c00; + reset (&, 0x05012c01); + mask (|, 0x05012c05); + capture group default; + }; + + register NMMUCQFIR_MASK + { + name "P9 chip NMMUCQFIR MASK"; + scomaddr 0x05012c03; + capture group default; + }; + + register NMMUCQFIR_ACT0 + { + name "P9 chip NMMUCQFIR ACT0"; + scomaddr 0x05012c06; + capture group default; + capture req nonzero("NMMUCQFIR"); + }; + + register NMMUCQFIR_ACT1 + { + name "P9 chip NMMUCQFIR ACT1"; + scomaddr 0x05012c07; + capture group default; + capture req nonzero("NMMUCQFIR"); + }; + + ############################################################################ + # P9 chip NMMUFIR + ############################################################################ + + register NMMUFIR + { + name "P9 chip NMMUFIR"; + scomaddr 0x05012c40; + reset (&, 0x05012c41); + mask (|, 0x05012c45); + capture group default; + }; + + register NMMUFIR_MASK + { + name "P9 chip NMMUFIR MASK"; + scomaddr 0x05012c43; + capture group default; + }; + + register NMMUFIR_ACT0 + { + name "P9 chip NMMUFIR ACT0"; + scomaddr 0x05012c46; + capture group default; + capture req nonzero("NMMUFIR"); + }; + + register NMMUFIR_ACT1 + { + name "P9 chip NMMUFIR ACT1"; + scomaddr 0x05012c47; + capture group default; + capture req nonzero("NMMUFIR"); + }; + + ############################################################################ + # P9 chip INTCQFIR + ############################################################################ + + register INTCQFIR + { + name "P9 chip INTCQFIR"; + scomaddr 0x05013030; + reset (&, 0x05013031); + mask (|, 0x05013035); + capture group default; + }; + + register INTCQFIR_MASK + { + name "P9 chip INTCQFIR MASK"; + scomaddr 0x05013033; + capture group default; + }; + + register INTCQFIR_ACT0 + { + name "P9 chip INTCQFIR ACT0"; + scomaddr 0x05013036; + capture group default; + capture req nonzero("INTCQFIR"); + }; + + register INTCQFIR_ACT1 + { + name "P9 chip INTCQFIR ACT1"; + scomaddr 0x05013037; + capture group default; + capture req nonzero("INTCQFIR"); + }; + + ############################################################################ + # P9 chip PBIOEFIR + ############################################################################ + + register PBIOEFIR + { + name "P9 chip PBIOEFIR"; + scomaddr 0x05013400; + reset (&, 0x05013401); + mask (|, 0x05013405); + capture group default; + }; + + register PBIOEFIR_MASK + { + name "P9 chip PBIOEFIR MASK"; + scomaddr 0x05013403; + capture group default; + }; + + register PBIOEFIR_ACT0 + { + name "P9 chip PBIOEFIR ACT0"; + scomaddr 0x05013406; + capture group default; + capture req nonzero("PBIOEFIR"); + }; + + register PBIOEFIR_ACT1 + { + name "P9 chip PBIOEFIR ACT1"; + scomaddr 0x05013407; + capture group default; + capture req nonzero("PBIOEFIR"); + }; + + ############################################################################ + # P9 chip PBIOOFIR + ############################################################################ + + register PBIOOFIR + { + name "P9 chip PBIOOFIR"; + scomaddr 0x05013800; + reset (&, 0x05013801); + mask (|, 0x05013805); + capture group default; + }; + + register PBIOOFIR_MASK + { + name "P9 chip PBIOOFIR MASK"; + scomaddr 0x05013803; + capture group default; + }; + + register PBIOOFIR_ACT0 + { + name "P9 chip PBIOOFIR ACT0"; + scomaddr 0x05013806; + capture group default; + capture req nonzero("PBIOOFIR"); + }; + + register PBIOOFIR_ACT1 + { + name "P9 chip PBIOOFIR ACT1"; + scomaddr 0x05013807; + capture group default; + capture req nonzero("PBIOOFIR"); + }; + + ############################################################################ + # XB Chiplet FIR + ############################################################################ + + register XB_CHIPLET_CS_FIR + { + name "XB Chiplet Checkstop FIR"; + scomaddr 0x06040000; + capture group default; + }; + + register XB_CHIPLET_RE_FIR + { + name "XB Chiplet Recoverable FIR"; + scomaddr 0x06040001; + capture group default; + }; + + register XB_CHIPLET_FIR_MASK + { + name "XB Chiplet FIR MASK"; + scomaddr 0x06040002; + capture group default; + }; + + ############################################################################ + # XB Chiplet Unit Checkstop FIR + ############################################################################ + + register XB_CHIPLET_UCS_FIR + { + name "XB Chiplet Unit Checkstop FIR"; + scomaddr 0x06040018; + capture group default; + }; + + register XB_CHIPLET_UCS_FIR_MASK + { + name "XB Chiplet Unit Checkstop FIR MASK"; + scomaddr 0x06040019; + capture group default; + }; + + ############################################################################ + # P9 chip XB_LFIR + ############################################################################ + + register XB_LFIR + { + name "P9 chip XB_LFIR"; + scomaddr 0x0604000a; + reset (&, 0x0604000b); + mask (|, 0x0604000f); + capture group default; + }; + + register XB_LFIR_MASK + { + name "P9 chip XB_LFIR MASK"; + scomaddr 0x0604000d; + capture group default; + }; + + register XB_LFIR_ACT0 + { + name "P9 chip XB_LFIR ACT0"; + scomaddr 0x06040010; + capture group default; + capture req nonzero("XB_LFIR"); + }; + + register XB_LFIR_ACT1 + { + name "P9 chip XB_LFIR ACT1"; + scomaddr 0x06040011; + capture group default; + capture req nonzero("XB_LFIR"); + }; + + ############################################################################ + # P9 chip XBPPEFIR + ############################################################################ + + register XBPPEFIR + { + name "P9 chip XBPPEFIR"; + scomaddr 0x06010840; + reset (&, 0x06010841); + mask (|, 0x06010845); + capture group default; + }; + + register XBPPEFIR_MASK + { + name "P9 chip XBPPEFIR MASK"; + scomaddr 0x06010843; + capture group default; + }; + + register XBPPEFIR_ACT0 + { + name "P9 chip XBPPEFIR ACT0"; + scomaddr 0x06010846; + capture group default; + capture req nonzero("XBPPEFIR"); + }; + + register XBPPEFIR_ACT1 + { + name "P9 chip XBPPEFIR ACT1"; + scomaddr 0x06010847; + capture group default; + capture req nonzero("XBPPEFIR"); + }; + + ############################################################################ + # PCI0 Chiplet FIR + ############################################################################ + + register PCI0_CHIPLET_CS_FIR + { + name "PCI0 Chiplet Checkstop FIR"; + scomaddr 0x0d040000; + capture group PciChipletFir0; + }; + + register PCI0_CHIPLET_RE_FIR + { + name "PCI0 Chiplet Recoverable FIR"; + scomaddr 0x0d040001; + capture group PciChipletFir0; + }; + + register PCI0_CHIPLET_FIR_MASK + { + name "PCI0 Chiplet FIR MASK"; + scomaddr 0x0d040002; + capture group PciChipletFir0; + }; + + ############################################################################ + # PCI1 Chiplet FIR + ############################################################################ + + register PCI1_CHIPLET_CS_FIR + { + name "PCI1 Chiplet Checkstop FIR"; + scomaddr 0x0e040000; + capture group PciChipletFir1; + }; + + register PCI1_CHIPLET_RE_FIR + { + name "PCI1 Chiplet Recoverable FIR"; + scomaddr 0x0e040001; + capture group PciChipletFir1; + }; + + register PCI1_CHIPLET_FIR_MASK + { + name "PCI1 Chiplet FIR MASK"; + scomaddr 0x0e040002; + capture group PciChipletFir1; + }; + + ############################################################################ + # PCI2 Chiplet FIR + ############################################################################ + + register PCI2_CHIPLET_CS_FIR + { + name "PCI2 Chiplet Checkstop FIR"; + scomaddr 0x0f040000; + capture group PciChipletFir2; + }; + + register PCI2_CHIPLET_RE_FIR + { + name "PCI2 Chiplet Recoverable FIR"; + scomaddr 0x0f040001; + capture group PciChipletFir2; + }; + + register PCI2_CHIPLET_FIR_MASK + { + name "PCI2 Chiplet FIR MASK"; + scomaddr 0x0f040002; + capture group PciChipletFir2; + }; + +# Include registers not defined by the xml +.include "p9_common_proc_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Global Attention FIR +################################################################################ + +rule rGLOBAL_FIR +{ + CHECK_STOP: + GLOBAL_CS_FIR; + RECOVERABLE: + GLOBAL_RE_FIR; +}; + +group gGLOBAL_FIR attntype CHECK_STOP, RECOVERABLE + filter singlebit +{ + /** GLOBAL_FIR[1] + * Attention from TP chiplet + */ + (rGLOBAL_FIR, bit(1)) ? analyze(gTP_CHIPLET_FIR); + + /** GLOBAL_FIR[2] + * Attention from N0 chiplet + */ + (rGLOBAL_FIR, bit(2)) ? analyze(gN0_CHIPLET_FIR); + + /** GLOBAL_FIR[3] + * Attention from N1 chiplet + */ + (rGLOBAL_FIR, bit(3)) ? analyze(gN1_CHIPLET_FIR); + + /** GLOBAL_FIR[4] + * Attention from N2 chiplet + */ + (rGLOBAL_FIR, bit(4)) ? analyze(gN2_CHIPLET_FIR); + + /** GLOBAL_FIR[5] + * Attention from N3 chiplet + */ + (rGLOBAL_FIR, bit(5)) ? analyze(gN3_CHIPLET_FIR); + + /** GLOBAL_FIR[6] + * Attention from XB chiplet + */ + (rGLOBAL_FIR, bit(6)) ? analyze(gXB_CHIPLET_FIR); + + /** GLOBAL_FIR[7] + * Attention from MC 0 chiplet + */ + (rGLOBAL_FIR, bit(7)) ? analyzeConnectedMC0; + + /** GLOBAL_FIR[8] + * Attention from MC 1 chiplet + */ + (rGLOBAL_FIR, bit(8)) ? analyzeConnectedMC1; + + /** GLOBAL_FIR[9] + * Attention from OB 0 chiplet + */ + (rGLOBAL_FIR, bit(9)) ? analyzeConnectedOBUS0; + + /** GLOBAL_FIR[10] + * Attention from OB 1 chiplet + */ + (rGLOBAL_FIR, bit(10)) ? analyzeConnectedOBUS1; + + /** GLOBAL_FIR[11] + * Attention from OB 2 chiplet + */ + (rGLOBAL_FIR, bit(11)) ? analyzeConnectedOBUS2; + + /** GLOBAL_FIR[12] + * Attention from OB 3 chiplet + */ + (rGLOBAL_FIR, bit(12)) ? analyzeConnectedOBUS3; + + /** GLOBAL_FIR[13] + * Attention from PCI0 chiplet + */ + (rGLOBAL_FIR, bit(13)) ? analyzePciChipletFir0; + + /** GLOBAL_FIR[14] + * Attention from PCI1 chiplet + */ + (rGLOBAL_FIR, bit(14)) ? analyzePciChipletFir1; + + /** GLOBAL_FIR[15] + * Attention from PCI2 chiplet + */ + (rGLOBAL_FIR, bit(15)) ? analyzePciChipletFir2; + + /** GLOBAL_FIR[16] + * Attention from EQ 0 chiplet + */ + (rGLOBAL_FIR, bit(16)) ? analyzeConnectedEQ0; + + /** GLOBAL_FIR[17] + * Attention from EQ 1 chiplet + */ + (rGLOBAL_FIR, bit(17)) ? analyzeConnectedEQ1; + + /** GLOBAL_FIR[18] + * Attention from EQ 2 chiplet + */ + (rGLOBAL_FIR, bit(18)) ? analyzeConnectedEQ2; + + /** GLOBAL_FIR[19] + * Attention from EQ 3 chiplet + */ + (rGLOBAL_FIR, bit(19)) ? analyzeConnectedEQ3; + + /** GLOBAL_FIR[20] + * Attention from EQ 4 chiplet + */ + (rGLOBAL_FIR, bit(20)) ? analyzeConnectedEQ4; + + /** GLOBAL_FIR[21] + * Attention from EQ 5 chiplet + */ + (rGLOBAL_FIR, bit(21)) ? analyzeConnectedEQ5; + + /** GLOBAL_FIR[32] + * Attention from EC 0 chiplet + */ + (rGLOBAL_FIR, bit(32)) ? analyzeConnectedEC0; + + /** GLOBAL_FIR[33] + * Attention from EC 1 chiplet + */ + (rGLOBAL_FIR, bit(33)) ? analyzeConnectedEC1; + + /** GLOBAL_FIR[34] + * Attention from EC 2 chiplet + */ + (rGLOBAL_FIR, bit(34)) ? analyzeConnectedEC2; + + /** GLOBAL_FIR[35] + * Attention from EC 3 chiplet + */ + (rGLOBAL_FIR, bit(35)) ? analyzeConnectedEC3; + + /** GLOBAL_FIR[36] + * Attention from EC 4 chiplet + */ + (rGLOBAL_FIR, bit(36)) ? analyzeConnectedEC4; + + /** GLOBAL_FIR[37] + * Attention from EC 5 chiplet + */ + (rGLOBAL_FIR, bit(37)) ? analyzeConnectedEC5; + + /** GLOBAL_FIR[38] + * Attention from EC 6 chiplet + */ + (rGLOBAL_FIR, bit(38)) ? analyzeConnectedEC6; + + /** GLOBAL_FIR[39] + * Attention from EC 7 chiplet + */ + (rGLOBAL_FIR, bit(39)) ? analyzeConnectedEC7; + + /** GLOBAL_FIR[40] + * Attention from EC 8 chiplet + */ + (rGLOBAL_FIR, bit(40)) ? analyzeConnectedEC8; + + /** GLOBAL_FIR[41] + * Attention from EC 9 chiplet + */ + (rGLOBAL_FIR, bit(41)) ? analyzeConnectedEC9; + + /** GLOBAL_FIR[42] + * Attention from EC 10 chiplet + */ + (rGLOBAL_FIR, bit(42)) ? analyzeConnectedEC10; + + /** GLOBAL_FIR[43] + * Attention from EC 11 chiplet + */ + (rGLOBAL_FIR, bit(43)) ? analyzeConnectedEC11; + + /** GLOBAL_FIR[44] + * Attention from EC 12 chiplet + */ + (rGLOBAL_FIR, bit(44)) ? analyzeConnectedEC12; + + /** GLOBAL_FIR[45] + * Attention from EC 13 chiplet + */ + (rGLOBAL_FIR, bit(45)) ? analyzeConnectedEC13; + + /** GLOBAL_FIR[46] + * Attention from EC 14 chiplet + */ + (rGLOBAL_FIR, bit(46)) ? analyzeConnectedEC14; + + /** GLOBAL_FIR[47] + * Attention from EC 15 chiplet + */ + (rGLOBAL_FIR, bit(47)) ? analyzeConnectedEC15; + + /** GLOBAL_FIR[48] + * Attention from EC 16 chiplet + */ + (rGLOBAL_FIR, bit(48)) ? analyzeConnectedEC16; + + /** GLOBAL_FIR[49] + * Attention from EC 17 chiplet + */ + (rGLOBAL_FIR, bit(49)) ? analyzeConnectedEC17; + + /** GLOBAL_FIR[50] + * Attention from EC 18 chiplet + */ + (rGLOBAL_FIR, bit(50)) ? analyzeConnectedEC18; + + /** GLOBAL_FIR[51] + * Attention from EC 19 chiplet + */ + (rGLOBAL_FIR, bit(51)) ? analyzeConnectedEC19; + + /** GLOBAL_FIR[52] + * Attention from EC 20 chiplet + */ + (rGLOBAL_FIR, bit(52)) ? analyzeConnectedEC20; + + /** GLOBAL_FIR[53] + * Attention from EC 21 chiplet + */ + (rGLOBAL_FIR, bit(53)) ? analyzeConnectedEC21; + + /** GLOBAL_FIR[54] + * Attention from EC 22 chiplet + */ + (rGLOBAL_FIR, bit(54)) ? analyzeConnectedEC22; + + /** GLOBAL_FIR[55] + * Attention from EC 23 chiplet + */ + (rGLOBAL_FIR, bit(55)) ? analyzeConnectedEC23; + +}; + +################################################################################ +# Global Unit Checkstop FIR +################################################################################ + +rule rGLOBAL_UCS_FIR +{ + UNIT_CS: + GLOBAL_UCS_FIR; +}; + +group gGLOBAL_UCS_FIR attntype UNIT_CS + filter singlebit +{ + /** GLOBAL_UCS_FIR[2] + * Attention from N0 chiplet + */ + (rGLOBAL_UCS_FIR, bit(2)) ? analyze(gN0_CHIPLET_UCS_FIR); + + /** GLOBAL_UCS_FIR[3] + * Attention from N1 chiplet + */ + (rGLOBAL_UCS_FIR, bit(3)) ? analyze(gN1_CHIPLET_UCS_FIR); + + /** GLOBAL_UCS_FIR[5] + * Attention from N3 chiplet + */ + (rGLOBAL_UCS_FIR, bit(5)) ? analyze(gN3_CHIPLET_UCS_FIR); + + /** GLOBAL_UCS_FIR[6] + * Attention from XB chiplet + */ + (rGLOBAL_UCS_FIR, bit(6)) ? analyze(gXB_CHIPLET_UCS_FIR); + + /** GLOBAL_UCS_FIR[7] + * Attention from MC 0 chiplet + */ + (rGLOBAL_UCS_FIR, bit(7)) ? analyzeConnectedMC0; + + /** GLOBAL_UCS_FIR[8] + * Attention from MC 1 chiplet + */ + (rGLOBAL_UCS_FIR, bit(8)) ? analyzeConnectedMC1; + + /** GLOBAL_UCS_FIR[9] + * Attention from OB 0 chiplet + */ + (rGLOBAL_UCS_FIR, bit(9)) ? analyzeConnectedOBUS0; + + /** GLOBAL_UCS_FIR[10] + * Attention from OB 1 chiplet + */ + (rGLOBAL_UCS_FIR, bit(10)) ? analyzeConnectedOBUS1; + + /** GLOBAL_UCS_FIR[11] + * Attention from OB 2 chiplet + */ + (rGLOBAL_UCS_FIR, bit(11)) ? analyzeConnectedOBUS2; + + /** GLOBAL_UCS_FIR[12] + * Attention from OB 3 chiplet + */ + (rGLOBAL_UCS_FIR, bit(12)) ? analyzeConnectedOBUS3; + + /** GLOBAL_UCS_FIR[32] + * Attention from EC 0 chiplet + */ + (rGLOBAL_UCS_FIR, bit(32)) ? analyzeConnectedEC0; + + /** GLOBAL_UCS_FIR[33] + * Attention from EC 1 chiplet + */ + (rGLOBAL_UCS_FIR, bit(33)) ? analyzeConnectedEC1; + + /** GLOBAL_UCS_FIR[34] + * Attention from EC 2 chiplet + */ + (rGLOBAL_UCS_FIR, bit(34)) ? analyzeConnectedEC2; + + /** GLOBAL_UCS_FIR[35] + * Attention from EC 3 chiplet + */ + (rGLOBAL_UCS_FIR, bit(35)) ? analyzeConnectedEC3; + + /** GLOBAL_UCS_FIR[36] + * Attention from EC 4 chiplet + */ + (rGLOBAL_UCS_FIR, bit(36)) ? analyzeConnectedEC4; + + /** GLOBAL_UCS_FIR[37] + * Attention from EC 5 chiplet + */ + (rGLOBAL_UCS_FIR, bit(37)) ? analyzeConnectedEC5; + + /** GLOBAL_UCS_FIR[38] + * Attention from EC 6 chiplet + */ + (rGLOBAL_UCS_FIR, bit(38)) ? analyzeConnectedEC6; + + /** GLOBAL_UCS_FIR[39] + * Attention from EC 7 chiplet + */ + (rGLOBAL_UCS_FIR, bit(39)) ? analyzeConnectedEC7; + + /** GLOBAL_UCS_FIR[40] + * Attention from EC 8 chiplet + */ + (rGLOBAL_UCS_FIR, bit(40)) ? analyzeConnectedEC8; + + /** GLOBAL_UCS_FIR[41] + * Attention from EC 9 chiplet + */ + (rGLOBAL_UCS_FIR, bit(41)) ? analyzeConnectedEC9; + + /** GLOBAL_UCS_FIR[42] + * Attention from EC 10 chiplet + */ + (rGLOBAL_UCS_FIR, bit(42)) ? analyzeConnectedEC10; + + /** GLOBAL_UCS_FIR[43] + * Attention from EC 11 chiplet + */ + (rGLOBAL_UCS_FIR, bit(43)) ? analyzeConnectedEC11; + + /** GLOBAL_UCS_FIR[44] + * Attention from EC 12 chiplet + */ + (rGLOBAL_UCS_FIR, bit(44)) ? analyzeConnectedEC12; + + /** GLOBAL_UCS_FIR[45] + * Attention from EC 13 chiplet + */ + (rGLOBAL_UCS_FIR, bit(45)) ? analyzeConnectedEC13; + + /** GLOBAL_UCS_FIR[46] + * Attention from EC 14 chiplet + */ + (rGLOBAL_UCS_FIR, bit(46)) ? analyzeConnectedEC14; + + /** GLOBAL_UCS_FIR[47] + * Attention from EC 15 chiplet + */ + (rGLOBAL_UCS_FIR, bit(47)) ? analyzeConnectedEC15; + + /** GLOBAL_UCS_FIR[48] + * Attention from EC 16 chiplet + */ + (rGLOBAL_UCS_FIR, bit(48)) ? analyzeConnectedEC16; + + /** GLOBAL_UCS_FIR[49] + * Attention from EC 17 chiplet + */ + (rGLOBAL_UCS_FIR, bit(49)) ? analyzeConnectedEC17; + + /** GLOBAL_UCS_FIR[50] + * Attention from EC 18 chiplet + */ + (rGLOBAL_UCS_FIR, bit(50)) ? analyzeConnectedEC18; + + /** GLOBAL_UCS_FIR[51] + * Attention from EC 19 chiplet + */ + (rGLOBAL_UCS_FIR, bit(51)) ? analyzeConnectedEC19; + + /** GLOBAL_UCS_FIR[52] + * Attention from EC 20 chiplet + */ + (rGLOBAL_UCS_FIR, bit(52)) ? analyzeConnectedEC20; + + /** GLOBAL_UCS_FIR[53] + * Attention from EC 21 chiplet + */ + (rGLOBAL_UCS_FIR, bit(53)) ? analyzeConnectedEC21; + + /** GLOBAL_UCS_FIR[54] + * Attention from EC 22 chiplet + */ + (rGLOBAL_UCS_FIR, bit(54)) ? analyzeConnectedEC22; + + /** GLOBAL_UCS_FIR[55] + * Attention from EC 23 chiplet + */ + (rGLOBAL_UCS_FIR, bit(55)) ? analyzeConnectedEC23; + +}; + +################################################################################ +# Global Host Attention FIR +################################################################################ + +rule rGLOBAL_HA_FIR +{ + HOST_ATTN: + GLOBAL_HA_FIR; +}; + +group gGLOBAL_HA_FIR attntype HOST_ATTN + filter singlebit +{ + /** GLOBAL_HA_FIR[3] + * Attention from N1 chiplet + */ + (rGLOBAL_HA_FIR, bit(3)) ? analyze(gN1_CHIPLET_HA_FIR); + + /** GLOBAL_HA_FIR[5] + * Attention from N3 chiplet + */ + (rGLOBAL_HA_FIR, bit(5)) ? analyze(gN3_CHIPLET_HA_FIR); + + /** GLOBAL_HA_FIR[7] + * Attention from MC 0 chiplet + */ + (rGLOBAL_HA_FIR, bit(7)) ? analyzeConnectedMC0; + + /** GLOBAL_HA_FIR[8] + * Attention from MC 1 chiplet + */ + (rGLOBAL_HA_FIR, bit(8)) ? analyzeConnectedMC1; + +}; + +################################################################################ +# TP Chiplet FIR +################################################################################ + +rule rTP_CHIPLET_FIR +{ + CHECK_STOP: + TP_CHIPLET_CS_FIR & ~TP_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (TP_CHIPLET_RE_FIR >> 2) & ~TP_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gTP_CHIPLET_FIR + filter singlebit +{ + /** TP_CHIPLET_FIR[3] + * Attention from TP_LFIR + */ + (rTP_CHIPLET_FIR, bit(3)) ? analyzeTP_LFIR; + + /** TP_CHIPLET_FIR[4] + * Attention from OCCFIR + */ + (rTP_CHIPLET_FIR, bit(4)) ? analyzeOCCFIR; + +}; + +################################################################################ +# P9 chip TP_LFIR +################################################################################ + +rule rTP_LFIR +{ + CHECK_STOP: + TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & ~TP_LFIR_ACT1; + RECOVERABLE: + TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & TP_LFIR_ACT1; +}; + +group gTP_LFIR + filter singlebit, + cs_root_cause +{ + /** TP_LFIR[0] + * CFIR internal parity error + */ + (rTP_LFIR, bit(0)) ? self_th_32perDay; + + /** TP_LFIR[1] + * Chiplet Control Reg: PCB Access Error + */ + (rTP_LFIR, bit(1)) ? self_th_32perDay; + + /** TP_LFIR[2] + * Clock Controller: PCB Access Error + */ + (rTP_LFIR, bit(2)) ? self_th_32perDay; + + /** TP_LFIR[3] + * Clock Controller: Summarized Error + */ + (rTP_LFIR, bit(3)) ? self_th_32perDay; + + /** TP_LFIR[4] + * PSCOM Logic: PCB Access Error + */ + (rTP_LFIR, bit(4)) ? defaultMaskedError; + + /** TP_LFIR[5] + * PSCOM Logic: Summarized internal errors + */ + (rTP_LFIR, bit(5)) ? defaultMaskedError; + + /** TP_LFIR[6] + * Therm Logic: Summarized internal errors + */ + (rTP_LFIR, bit(6)) ? defaultMaskedError; + + /** TP_LFIR[7] + * Therm Logic: PCB Access Error + */ + (rTP_LFIR, bit(7)) ? defaultMaskedError; + + /** TP_LFIR[8] + * Therm Logic: Temperature critical trip + */ + (rTP_LFIR, bit(8)) ? defaultMaskedError; + + /** TP_LFIR[9] + * Therm Logic: Temperature fatal trip + */ + (rTP_LFIR, bit(9)) ? defaultMaskedError; + + /** TP_LFIR[10] + * UNUSED in P9 + */ + (rTP_LFIR, bit(10)) ? defaultMaskedError; + + /** TP_LFIR[11] + * Debug Logic: Scom Satelite Error + */ + (rTP_LFIR, bit(11)) ? defaultMaskedError; + + /** TP_LFIR[12] + * Trace Logic: Scom Satellite Error + */ + (rTP_LFIR, bit(12)) ? defaultMaskedError; + + /** TP_LFIR[13] + * Trace Logic: Scom Satellite Error + */ + (rTP_LFIR, bit(13)) ? defaultMaskedError; + + /** TP_LFIR[14] + * Freq Meas. Reg PE or VMEAS/KVREF timeout + */ + (rTP_LFIR, bit(14)) ? defaultMaskedError; + + /** TP_LFIR[15] + * Interrupt Macro: PCB Access Error + */ + (rTP_LFIR, bit(15)) ? defaultMaskedError; + + /** TP_LFIR[16] + * PCB Master Logic: PCB Timout + */ + (rTP_LFIR, bit(16)) ? defaultMaskedError; + + /** TP_LFIR[17] + * I2C Master Logic: Local Bus Parity error + */ + (rTP_LFIR, bit(17)) ? self_th_1; + + /** TP_LFIR[18] + * TOD Logic: Summerized internal errors + */ + (rTP_LFIR, bit(18)) ? analyzeTodBackupTopology; + + /** TP_LFIR[19] + * TOD Logic: PIB Slave access errors + */ + (rTP_LFIR, bit(19)) ? analyzePibError; + + /** TP_LFIR[20] + * TOD Logic: Error report from PHYP + */ + (rTP_LFIR, bit(20)) ? analyzePhypTodError; + + /** TP_LFIR[21] + * PCB slave Unmasked err summary + */ + (rTP_LFIR, bit(21)) ? pcb_slave_internal_parity; + + /** TP_LFIR[22] + * SBE Logic: PPE Internal State Error + */ + (rTP_LFIR, bit(22)) ? defaultMaskedError; + + /** TP_LFIR[23] + * PPE interface invalid seq/protocol err + */ + (rTP_LFIR, bit(23)) ? defaultMaskedError; + + /** TP_LFIR[24] + * SBE Logic: PPE Watchdog timeout + */ + (rTP_LFIR, bit(24)) ? defaultMaskedError; + + /** TP_LFIR[25] + * PPE saw proc halt initiated by fw, etc. + */ + (rTP_LFIR, bit(25)) ? defaultMaskedError; + + /** TP_LFIR[26] + * PPE in halt state driven by RAMDBG bit 0 + */ + (rTP_LFIR, bit(26)) ? sbe_vital_attn; + + /** TP_LFIR[27] + * PPE debug: Watchdog timer proc rst/halt + */ + (rTP_LFIR, bit(27)) ? defaultMaskedError; + + /** TP_LFIR[28] + * SBE Logic: SEEPROM Address err etc. + */ + (rTP_LFIR, bit(28)) ? defaultMaskedError; + + /** TP_LFIR[29] + * SBE Logic: Any I2C Master Error + */ + (rTP_LFIR, bit(29)) ? defaultMaskedError; + + /** TP_LFIR[30] + * SBE Logic: Programmable errors + */ + (rTP_LFIR, bit(30)) ? defaultMaskedError; + + /** TP_LFIR[31] + * OTP Logic: invalid reg access etc. + */ + (rTP_LFIR, bit(31)) ? defaultMaskedError; + + /** TP_LFIR[32] + * Trigger from e_c4_occ_rx_alert_b input + */ + (rTP_LFIR, bit(32)) ? defaultMaskedError; + + /** TP_LFIR[33] + * Unused in P9 + */ + (rTP_LFIR, bit(33)) ? defaultMaskedError; + + /** TP_LFIR[34] + * Multicast group: group cntr zero + */ + (rTP_LFIR, bit(34)) ? defaultMaskedError; + + /** TP_LFIR[35] + * PCB Master: Receive fsm Inv. state etc. + */ + (rTP_LFIR, bit(35)) ? defaultMaskedError; + + /** TP_LFIR[36] + * system ref osc switch to backup + */ + (rTP_LFIR, bit(36)) ? sys_osc_switch_error; + + /** TP_LFIR[37] + * PCI osc switch to backup + */ + (rTP_LFIR, bit(37)) ? pci_osc_switch_error; + + /** TP_LFIR[38] + * PIB MEM: Summarized err - PIB access ops + */ + (rTP_LFIR, bit(38)) ? defaultMaskedError; + + /** TP_LFIR[39] + * PIB MEM: Summarized err-fast access ops + */ + (rTP_LFIR, bit(39)) ? defaultMaskedError; + + /** TP_LFIR[40] + * OTP Logic: UE or CE counter overflow + */ + (rTP_LFIR, bit(40)) ? defaultMaskedError; + + /** TP_LFIR[41] + * malfunction alert or Local Checkstop + */ + (rTP_LFIR, bit(41)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip OCCFIR +################################################################################ + +rule rOCCFIR +{ + CHECK_STOP: + OCCFIR & ~OCCFIR_MASK & ~OCCFIR_ACT0 & ~OCCFIR_ACT1; + RECOVERABLE: + OCCFIR & ~OCCFIR_MASK & ~OCCFIR_ACT0 & OCCFIR_ACT1; +}; + +group gOCCFIR + filter singlebit, + cs_root_cause +{ + /** OCCFIR[0] + * OCC_FW0 + */ + (rOCCFIR, bit(0)) ? defaultMaskedError; + + /** OCCFIR[1] + * OCC_FW1 + */ + (rOCCFIR, bit(1)) ? defaultMaskedError; + + /** OCCFIR[2] + * OCC_CME_ERROR_NOTIFY + */ + (rOCCFIR, bit(2)) ? defaultMaskedError; + + /** OCCFIR[3] + * STOP_RECOVERY_NOTIFY_PRD + */ + (rOCCFIR, bit(3)) ? pmRecovery; + + /** OCCFIR[4] + * OCC_HB_ERROR + */ + (rOCCFIR, bit(4)) ? defaultMaskedError; + + /** OCCFIR[5] + * GPE0 watchdog timeout condition + */ + (rOCCFIR, bit(5)) ? defaultMaskedError; + + /** OCCFIR[6] + * GPE1 watchdog timeout condition + */ + (rOCCFIR, bit(6)) ? defaultMaskedError; + + /** OCCFIR[7] + * GPE2 watchdog timeout condition + */ + (rOCCFIR, bit(7)) ? defaultMaskedError; + + /** OCCFIR[8] + * GPE3 watchdog timeout condition + */ + (rOCCFIR, bit(8)) ? defaultMaskedError; + + /** OCCFIR[9] + * GPE0 asserted an error condition + */ + (rOCCFIR, bit(9)) ? threshold_and_mask_self; + + /** OCCFIR[10] + * GPE1 asserted an error condition + */ + (rOCCFIR, bit(10)) ? threshold_and_mask_self; + + /** OCCFIR[11] + * GPE2 asserted an error condition + */ + (rOCCFIR, bit(11)) ? defaultMaskedError; + + /** OCCFIR[12] + * GPE3 asserted an error condition + */ + (rOCCFIR, bit(12)) ? defaultMaskedError; + + /** OCCFIR[13] + * OCB_ERROR + */ + (rOCCFIR, bit(13)) ? defaultMaskedError; + + /** OCCFIR[14] + * SRAM Unrecoverable Error + */ + (rOCCFIR, bit(14)) ? self_th_1; + + /** OCCFIR[15] + * SRAM CE + */ + (rOCCFIR, bit(15)) ? threshold_and_mask_self; + + /** OCCFIR[16] + * SRAM Read Error + */ + (rOCCFIR, bit(16)) ? threshold_and_mask_self; + + /** OCCFIR[17] + * SRAM Write error + */ + (rOCCFIR, bit(17)) ? threshold_and_mask_self; + + /** OCCFIR[18] + * SRAM ctrl detected pe on tank read data + */ + (rOCCFIR, bit(18)) ? threshold_and_mask_self; + + /** OCCFIR[19] + * SRAM cntrl detected OCI write data pe + */ + (rOCCFIR, bit(19)) ? threshold_and_mask_self; + + /** OCCFIR[20] + * SRAM cntrl detected OCI byte enable PE + */ + (rOCCFIR, bit(20)) ? threshold_and_mask_self; + + /** OCCFIR[21] + * SRAM controller detected OCI address PE + */ + (rOCCFIR, bit(21)) ? threshold_and_mask_self; + + /** OCCFIR[22] + * GPE0_HALTED: + */ + (rOCCFIR, bit(22)) ? defaultMaskedError; + + /** OCCFIR[23] + * GPE1_HALTED: + */ + (rOCCFIR, bit(23)) ? defaultMaskedError; + + /** OCCFIR[24] + * GPE2_HALTED: + */ + (rOCCFIR, bit(24)) ? defaultMaskedError; + + /** OCCFIR[25] + * GPE3_HALTED: + */ + (rOCCFIR, bit(25)) ? defaultMaskedError; + + /** OCCFIR[26] + * EXTERNAL_TRAP: + */ + (rOCCFIR, bit(26)) ? defaultMaskedError; + + /** OCCFIR[27] + * PPC405_CORE_RESET + */ + (rOCCFIR, bit(27)) ? defaultMaskedError; + + /** OCCFIR[28] + * PPC405_CHIP_RESET + */ + (rOCCFIR, bit(28)) ? defaultMaskedError; + + /** OCCFIR[29] + * PPC405_SYSTEM_RESET + */ + (rOCCFIR, bit(29)) ? defaultMaskedError; + + /** OCCFIR[30] + * PPC405_DBGMSRWE + */ + (rOCCFIR, bit(30)) ? defaultMaskedError; + + /** OCCFIR[31] + * PPC405_DBGSTOPACK + */ + (rOCCFIR, bit(31)) ? defaultMaskedError; + + /** OCCFIR[32] + * OCB_DB_OCI_TIMEOUT + */ + (rOCCFIR, bit(32)) ? threshold_and_mask_self; + + /** OCCFIR[33] + * OCB_DB_OCI_READ_DATA_PARITY + */ + (rOCCFIR, bit(33)) ? threshold_and_mask_self; + + /** OCCFIR[34] + * OCB_DB_OCI_SLAVE_ERROR + */ + (rOCCFIR, bit(34)) ? threshold_and_mask_self; + + /** OCCFIR[35] + * OCB_PIB_ADDR_PARITY_ERR + */ + (rOCCFIR, bit(35)) ? threshold_and_mask_self; + + /** OCCFIR[36] + * OCB_PIB_DATA_PARITY_ERR + */ + (rOCCFIR, bit(36)) ? threshold_and_mask_self; + + /** OCCFIR[37] + * OCB_IDC0_ERROR + */ + (rOCCFIR, bit(37)) ? threshold_and_mask_self; + + /** OCCFIR[38] + * OCB_IDC1_ERROR + */ + (rOCCFIR, bit(38)) ? threshold_and_mask_self; + + /** OCCFIR[39] + * OCB_IDC2_ERROR + */ + (rOCCFIR, bit(39)) ? threshold_and_mask_self; + + /** OCCFIR[40] + * OCB_IDC3_ERROR + */ + (rOCCFIR, bit(40)) ? threshold_and_mask_self; + + /** OCCFIR[41] + * SRT_FSM_ERR + */ + (rOCCFIR, bit(41)) ? threshold_and_mask_self; + + /** OCCFIR[42] + * JTAGACC_ERR + */ + (rOCCFIR, bit(42)) ? threshold_and_mask_self; + + /** OCCFIR[43] + * spare + */ + (rOCCFIR, bit(43)) ? defaultMaskedError; + + /** OCCFIR[44] + * C405_ECC_UE + */ + (rOCCFIR, bit(44)) ? threshold_and_mask_self; + + /** OCCFIR[45] + * C405_ECC_CE + */ + (rOCCFIR, bit(45)) ? self_th_1; + + /** OCCFIR[46] + * C405_OCI_MACHINECHECK + */ + (rOCCFIR, bit(46)) ? threshold_and_mask_self; + + /** OCCFIR[47] + * SRAM_SPARE_DIRECT_ERROR0 + */ + (rOCCFIR, bit(47)) ? threshold_and_mask_self; + + /** OCCFIR[48] + * SRAM_SPARE_DIRECT_ERROR1 + */ + (rOCCFIR, bit(48)) ? threshold_and_mask_self; + + /** OCCFIR[49] + * SRAM_SPARE_DIRECT_ERROR2 + */ + (rOCCFIR, bit(49)) ? threshold_and_mask_self; + + /** OCCFIR[50] + * SRAM_SPARE_DIRECT_ERROR3 + */ + (rOCCFIR, bit(50)) ? threshold_and_mask_self; + + /** OCCFIR[51] + * GPE0_OCISLV_ERR + */ + (rOCCFIR, bit(51)) ? threshold_and_mask_self; + + /** OCCFIR[52] + * GPE1_OCISLV_ERR + */ + (rOCCFIR, bit(52)) ? threshold_and_mask_self; + + /** OCCFIR[53] + * GPE2_OCISLV_ERR + */ + (rOCCFIR, bit(53)) ? threshold_and_mask_self; + + /** OCCFIR[54] + * GPE3_OCISLV_ERR + */ + (rOCCFIR, bit(54)) ? threshold_and_mask_self; + + /** OCCFIR[55] + * C405ICU_M_TIMEOUT + */ + (rOCCFIR, bit(55)) ? defaultMaskedError; + + /** OCCFIR[56] + * C405DCU_M_TIMEOUT + */ + (rOCCFIR, bit(56)) ? threshold_and_mask_self; + + /** OCCFIR[57] + * OCC_COMPLEX_FAULT + */ + (rOCCFIR, bit(57)) ? threshold_and_mask_self; + + /** OCCFIR[58] + * OCC_COMPLEX_NOTIFY + */ + (rOCCFIR, bit(58)) ? threshold_and_mask_self; + + /** OCCFIR[59:61] + * spare + */ + (rOCCFIR, bit(59|60|61)) ? defaultMaskedError; + + /** OCCFIR[62] + * scom + */ + (rOCCFIR, bit(62)) ? defaultMaskedError; + + /** OCCFIR[63] + * scom error + */ + (rOCCFIR, bit(63)) ? defaultMaskedError; + +}; + +################################################################################ +# N0 Chiplet FIR +################################################################################ + +rule rN0_CHIPLET_FIR +{ + CHECK_STOP: + N0_CHIPLET_CS_FIR & ~N0_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (N0_CHIPLET_RE_FIR >> 2) & ~N0_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gN0_CHIPLET_FIR + filter singlebit +{ + /** N0_CHIPLET_FIR[3] + * Attention from N0_LFIR + */ + (rN0_CHIPLET_FIR, bit(3)) ? analyzeN0_LFIR; + + /** N0_CHIPLET_FIR[4] + * Attention from NXDMAENGFIR + */ + (rN0_CHIPLET_FIR, bit(4)) ? analyzeNXDMAENGFIR; + + /** N0_CHIPLET_FIR[5] + * Attention from NXCQFIR + */ + (rN0_CHIPLET_FIR, bit(5)) ? analyzeNXCQFIR; + + /** N0_CHIPLET_FIR[6] + * Attention from CXAFIR 0 + */ + (rN0_CHIPLET_FIR, bit(6)) ? analyzeConnectedCAPP0; + +}; + +################################################################################ +# N0 Chiplet Unit Checkstop FIR +################################################################################ + +rule rN0_CHIPLET_UCS_FIR +{ + UNIT_CS: + N0_CHIPLET_UCS_FIR & ~(N0_CHIPLET_UCS_FIR_MASK >> 1) & `7fffffffffffffff`; +}; + +group gN0_CHIPLET_UCS_FIR + filter singlebit +{ + /** N0_CHIPLET_UCS_FIR[1] + * Attention from NXDMAENGFIR + */ + (rN0_CHIPLET_UCS_FIR, bit(1)) ? analyzeNXDMAENGFIR; + + /** N0_CHIPLET_UCS_FIR[2] + * Attention from NXCQFIR + */ + (rN0_CHIPLET_UCS_FIR, bit(2)) ? analyzeNXCQFIR; + + /** N0_CHIPLET_UCS_FIR[3] + * Attention from CXAFIR 0 + */ + (rN0_CHIPLET_UCS_FIR, bit(3)) ? analyzeConnectedCAPP0; + +}; + +################################################################################ +# P9 chip N0_LFIR +################################################################################ + +rule rN0_LFIR +{ + CHECK_STOP: + N0_LFIR & ~N0_LFIR_MASK & ~N0_LFIR_ACT0 & ~N0_LFIR_ACT1; + RECOVERABLE: + N0_LFIR & ~N0_LFIR_MASK & ~N0_LFIR_ACT0 & N0_LFIR_ACT1; +}; + +group gN0_LFIR + filter singlebit, + cs_root_cause +{ + /** N0_LFIR[0] + * CFIR internal parity error + */ + (rN0_LFIR, bit(0)) ? self_th_32perDay; + + /** N0_LFIR[1] + * Chiplet Control Reg: PCB Access Error + */ + (rN0_LFIR, bit(1)) ? self_th_32perDay; + + /** N0_LFIR[2] + * Clock Controller: PCB Access Error + */ + (rN0_LFIR, bit(2)) ? self_th_32perDay; + + /** N0_LFIR[3] + * Clock Controller: Summarized Error + */ + (rN0_LFIR, bit(3)) ? self_th_32perDay; + + /** N0_LFIR[4] + * PSCOM Logic: PCB Access Error + */ + (rN0_LFIR, bit(4)) ? defaultMaskedError; + + /** N0_LFIR[5] + * PSCOM Logic: Summarized internal errors + */ + (rN0_LFIR, bit(5)) ? defaultMaskedError; + + /** N0_LFIR[6] + * Therm Logic: Summarized internal errors + */ + (rN0_LFIR, bit(6)) ? defaultMaskedError; + + /** N0_LFIR[7] + * Therm Logic: PCB Access Error + */ + (rN0_LFIR, bit(7)) ? defaultMaskedError; + + /** N0_LFIR[8] + * Therm Logic: Temperature critical trip + */ + (rN0_LFIR, bit(8)) ? defaultMaskedError; + + /** N0_LFIR[9] + * Therm Logic: Temperature fatal trip + */ + (rN0_LFIR, bit(9)) ? defaultMaskedError; + + /** N0_LFIR[10] + * UNUSED in P9 + */ + (rN0_LFIR, bit(10)) ? defaultMaskedError; + + /** N0_LFIR[11] + * Debug Logic: Scom Satellite Error + */ + (rN0_LFIR, bit(11)) ? defaultMaskedError; + + /** N0_LFIR[12] + * Scom Satellite Error - Trace0 + */ + (rN0_LFIR, bit(12)) ? defaultMaskedError; + + /** N0_LFIR[13] + * Scom Satellite Error - Trace0 + */ + (rN0_LFIR, bit(13)) ? defaultMaskedError; + + /** N0_LFIR[14] + * Scom Satellite Error - Trace1 + */ + (rN0_LFIR, bit(14)) ? defaultMaskedError; + + /** N0_LFIR[15] + * Scom Satellite Error - Trace1 + */ + (rN0_LFIR, bit(15)) ? defaultMaskedError; + + /** N0_LFIR[16:23] + * spare + */ + (rN0_LFIR, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError; + + /** N0_LFIR[24] + * Unused + */ + (rN0_LFIR, bit(24)) ? defaultMaskedError; + + /** N0_LFIR[25] + * Unused + */ + (rN0_LFIR, bit(25)) ? defaultMaskedError; + + /** N0_LFIR[26:40] + * spare + */ + (rN0_LFIR, bit(26|27|28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError; + + /** N0_LFIR[41] + * Malfunction Alert or Local Checkstop + */ + (rN0_LFIR, bit(41)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip NXCQFIR +################################################################################ + +rule rNXCQFIR +{ + CHECK_STOP: + NXCQFIR & ~NXCQFIR_MASK & ~NXCQFIR_ACT0 & ~NXCQFIR_ACT1; + RECOVERABLE: + NXCQFIR & ~NXCQFIR_MASK & ~NXCQFIR_ACT0 & NXCQFIR_ACT1; + UNIT_CS: + NXCQFIR & ~NXCQFIR_MASK & NXCQFIR_ACT0 & NXCQFIR_ACT1; +}; + +group gNXCQFIR + filter singlebit, + cs_root_cause +{ + /** NXCQFIR[0] + * PBI internal parity error + */ + (rNXCQFIR, bit(0)) ? nx_th_1; + + /** NXCQFIR[1] + * PowerBus CE error + */ + (rNXCQFIR, bit(1)) ? nx_th_32perDay; + + /** NXCQFIR[2] + * PowerBus UE error + */ + (rNXCQFIR, bit(2)) ? nx_th_1; + + /** NXCQFIR[3] + * PBUS_ECC_SUE_FIR: PowerBus SUE error + */ + (rNXCQFIR, bit(3)) ? defaultMaskedError; + + /** NXCQFIR[4] + * Inbound array CE error + */ + (rNXCQFIR, bit(4)) ? nx_th_32perDay; + + /** NXCQFIR[5] + * Inbound array UE error + */ + (rNXCQFIR, bit(5)) ? nx_th_1; + + /** NXCQFIR[6] + * PASTE_REJECT_FIR: Paste request rejected + */ + (rNXCQFIR, bit(6)) ? level2_th_1; + + /** NXCQFIR[7] + * PowerBus command hang error + */ + (rNXCQFIR, bit(7)) ? defaultMaskedError; + + /** NXCQFIR[8] + * PowerBus read address error + */ + (rNXCQFIR, bit(8)) ? nx_th_1; + + /** NXCQFIR[9] + * PowerBus write address error + */ + (rNXCQFIR, bit(9)) ? nx_th_1; + + /** NXCQFIR[10] + * PowerBus miscellaneous error + */ + (rNXCQFIR, bit(10)) ? nx_th_1; + + /** NXCQFIR[11] + * MMIO_BAR_PE_FIR: MMIO BAR parity error + */ + (rNXCQFIR, bit(11)) ? nx_th_1; + + /** NXCQFIR[12] + * UMAC detected UE on WC Interrupt + */ + (rNXCQFIR, bit(12)) ? nx_th_1; + + /** NXCQFIR[13] + * ACK_DEAD cresp received by read command + */ + (rNXCQFIR, bit(13)) ? defaultMaskedError; + + /** NXCQFIR[14] + * ACK_DEAD cresp received by write command + */ + (rNXCQFIR, bit(14)) ? defaultMaskedError; + + /** NXCQFIR[15] + * Link check aborted while waiting on data + */ + (rNXCQFIR, bit(15)) ? defaultMaskedError; + + /** NXCQFIR[16] + * internal transfer hang poll time expired + */ + (rNXCQFIR, bit(16)) ? nx_th_1; + + /** NXCQFIR[17] + * Parity error on ERAT arrays + */ + (rNXCQFIR, bit(17)) ? nx_th_1; + + /** NXCQFIR[18] + * Correctable error on ERAT arrays + */ + (rNXCQFIR, bit(18)) ? nx_th_32perDay; + + /** NXCQFIR[19] + * Uncorrectable error on ERAT arrays + */ + (rNXCQFIR, bit(19)) ? nx_th_32perDay; + + /** NXCQFIR[20] + * SUE on ERAT arrays + */ + (rNXCQFIR, bit(20)) ? nx_th_1_SUE; + + /** NXCQFIR[21] + * NMMU hang on checkin/checkout request + */ + (rNXCQFIR, bit(21)) ? level2_th_1; + + /** NXCQFIR[22] + * ERAT control logic error + */ + (rNXCQFIR, bit(22)) ? nx_th_1; + + /** NXCQFIR[23] + * UE on the Powerbus data for xlate + */ + (rNXCQFIR, bit(23)) ? nx_th_1; + + /** NXCQFIR[24] + * SUE on the Powerbus data for xlate + */ + (rNXCQFIR, bit(24)) ? nx_th_1_SUE; + + /** NXCQFIR[25] + * ACK_DEAD cresp received by UMAC read + */ + (rNXCQFIR, bit(25)) ? defaultMaskedError; + + /** NXCQFIR[26] + * Link check aborted waiting on UMAC data + */ + (rNXCQFIR, bit(26)) ? defaultMaskedError; + + /** NXCQFIR[27] + * UE on CRB QW0/4 + */ + (rNXCQFIR, bit(27)) ? nx_th_1; + + /** NXCQFIR[28] + * SUE on CRB QW0/4 + */ + (rNXCQFIR, bit(28)) ? nx_th_1_SUE; + + /** NXCQFIR[29] + * UMAC has detected a control logic error + */ + (rNXCQFIR, bit(29)) ? nx_th_1; + + /** NXCQFIR[30] + * Reserved fieldUMAC_SCOM_sat_err) + */ + (rNXCQFIR, bit(30)) ? defaultMaskedError; + + /** NXCQFIR[31] + * Write to RNG SCOM when writes disabled + */ + (rNXCQFIR, bit(31)) ? defaultMaskedError; + + /** NXCQFIR[32] + * first noise source in the RNG has failed + */ + (rNXCQFIR, bit(32)) ? nx_th_32perDay; + + /** NXCQFIR[33] + * second noise source in the RNG failed + */ + (rNXCQFIR, bit(33)) ? nx_th_32perDay; + + /** NXCQFIR[34] + * RNG has detected a control logic error + */ + (rNXCQFIR, bit(34)) ? nx_th_1; + + /** NXCQFIR[35] + * NMMU has signaled local checkstop + */ + (rNXCQFIR, bit(35)) ? nx_th_1; + + /** NXCQFIR[36] + * VAS has signaled local checkstop + */ + (rNXCQFIR, bit(36)) ? nx_th_1; + + /** NXCQFIR[37] + * PBCQ has detected a control logic error + */ + (rNXCQFIR, bit(37)) ? nx_th_1; + + /** NXCQFIR[38] + * PBCQ detected failed link + */ + (rNXCQFIR, bit(38)) ? defaultMaskedError; + + /** NXCQFIR[39] + * UMAC detected SUE on WC Interrupt + */ + (rNXCQFIR, bit(39)) ? nx_th_1_SUE; + + /** NXCQFIR[40] + * SMF address bit = 1 error + */ + (rNXCQFIR, bit(40)) ? defaultMaskedError; + + /** NXCQFIR[41] + * Spare + */ + (rNXCQFIR, bit(41)) ? defaultMaskedError; + + /** NXCQFIR[42] + * scom error + */ + (rNXCQFIR, bit(42)) ? defaultMaskedError; + + /** NXCQFIR[43] + * scom error + */ + (rNXCQFIR, bit(43)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip NXDMAENGFIR +################################################################################ + +rule rNXDMAENGFIR +{ + CHECK_STOP: + NXDMAENGFIR & ~NXDMAENGFIR_MASK & ~NXDMAENGFIR_ACT0 & ~NXDMAENGFIR_ACT1; + RECOVERABLE: + NXDMAENGFIR & ~NXDMAENGFIR_MASK & ~NXDMAENGFIR_ACT0 & NXDMAENGFIR_ACT1; + UNIT_CS: + NXDMAENGFIR & ~NXDMAENGFIR_MASK & NXDMAENGFIR_ACT0 & NXDMAENGFIR_ACT1; +}; + +group gNXDMAENGFIR + filter singlebit, + cs_root_cause +{ + /** NXDMAENGFIR[0] + * DMA hang timer expired + */ + (rNXDMAENGFIR, bit(0)) ? nx_th_1; + + /** NXDMAENGFIR[1] + * SHM invalid state + */ + (rNXDMAENGFIR, bit(1)) ? nx_th_1; + + /** NXDMAENGFIR[2:3] + * spare + */ + (rNXDMAENGFIR, bit(2|3)) ? defaultMaskedError; + + /** NXDMAENGFIR[4] + * Channel 0 842 engine ECC CE error + */ + (rNXDMAENGFIR, bit(4)) ? nx_th_32perDay; + + /** NXDMAENGFIR[5] + * Channel 0 842 engine ECC UE error + */ + (rNXDMAENGFIR, bit(5)) ? nx_th_1; + + /** NXDMAENGFIR[6] + * Channel 1 842 engine ECC CE error + */ + (rNXDMAENGFIR, bit(6)) ? nx_th_32perDay; + + /** NXDMAENGFIR[7] + * Channel 1 842 engine ECC UE error + */ + (rNXDMAENGFIR, bit(7)) ? nx_th_1; + + /** NXDMAENGFIR[8] + * DMA Non-zero CSB CC detected + */ + (rNXDMAENGFIR, bit(8)) ? defaultMaskedError; + + /** NXDMAENGFIR[9] + * DMA array ECC CE error + */ + (rNXDMAENGFIR, bit(9)) ? nx_th_32perDay; + + /** NXDMAENGFIR[10] + * DMA outWR/inRD ECC CE error + */ + (rNXDMAENGFIR, bit(10)) ? nx_th_32perDay; + + /** NXDMAENGFIR[11] + * Channel 4 GZIP ECC CE + */ + (rNXDMAENGFIR, bit(11)) ? nx_th_32perDay; + + /** NXDMAENGFIR[12] + * Channel 4 GZIP ECC UE + */ + (rNXDMAENGFIR, bit(12)) ? nx_th_1; + + /** NXDMAENGFIR[13] + * Channel 4 GZIP ECC PE + */ + (rNXDMAENGFIR, bit(13)) ? nx_th_1; + + /** NXDMAENGFIR[14] + * SCOM error from other satellites + */ + (rNXDMAENGFIR, bit(14)) ? defaultMaskedError; + + /** NXDMAENGFIR[15] + * DMA invalid state error (unrecoverable) + */ + (rNXDMAENGFIR, bit(15)) ? nx_th_1; + + /** NXDMAENGFIR[16] + * DMA invalid state error (unrecoverable) + */ + (rNXDMAENGFIR, bit(16)) ? nx_th_1; + + /** NXDMAENGFIR[17] + * DMA array ECC UE error + */ + (rNXDMAENGFIR, bit(17)) ? nx_th_1; + + /** NXDMAENGFIR[18] + * DMA outWR/inRD ECC UE error + */ + (rNXDMAENGFIR, bit(18)) ? nx_th_1; + + /** NXDMAENGFIR[19] + * DMA inRD done error + */ + (rNXDMAENGFIR, bit(19)) ? defaultMaskedError; + + /** NXDMAENGFIR[20] + * Channel 0 invalid state error + */ + (rNXDMAENGFIR, bit(20)) ? nx_th_1; + + /** NXDMAENGFIR[21] + * Channel 1 invalid state error + */ + (rNXDMAENGFIR, bit(21)) ? nx_th_1; + + /** NXDMAENGFIR[22] + * Channel 2 invalid state error + */ + (rNXDMAENGFIR, bit(22)) ? nx_th_1; + + /** NXDMAENGFIR[23] + * Channel 3 invalid state error + */ + (rNXDMAENGFIR, bit(23)) ? nx_th_1; + + /** NXDMAENGFIR[24] + * Channel 4 invalid state error + */ + (rNXDMAENGFIR, bit(24)) ? nx_th_1; + + /** NXDMAENGFIR[25:30] + * spare + */ + (rNXDMAENGFIR, bit(25|26|27|28|29|30)) ? defaultMaskedError; + + /** NXDMAENGFIR[31] + * CRB UE, on CSB/CCB + */ + (rNXDMAENGFIR, bit(31)) ? nx_th_1; + + /** NXDMAENGFIR[32] + * CRB SUE, on CSB/CCB + */ + (rNXDMAENGFIR, bit(32)) ? nx_th_1_SUE; + + /** NXDMAENGFIR[33] + * DMA outWR/inRD ECC SUE error + */ + (rNXDMAENGFIR, bit(33)) ? defaultMaskedError; + + /** NXDMAENGFIR[34] + * Channel 0 watchdog timer expired + */ + (rNXDMAENGFIR, bit(34)) ? nx_th_32perDay; + + /** NXDMAENGFIR[35] + * Channel 1 watchdog timer expired + */ + (rNXDMAENGFIR, bit(35)) ? nx_th_32perDay; + + /** NXDMAENGFIR[36] + * Channel 2 watchdog timer expired + */ + (rNXDMAENGFIR, bit(36)) ? nx_th_32perDay; + + /** NXDMAENGFIR[37] + * Channel 3 watchdog timer expired + */ + (rNXDMAENGFIR, bit(37)) ? nx_th_32perDay; + + /** NXDMAENGFIR[38] + * Hypervisor local checkstop + */ + (rNXDMAENGFIR, bit(38)) ? nx_th_1; + + /** NXDMAENGFIR[39] + * Channel 4 watchdog timer expired + */ + (rNXDMAENGFIR, bit(39)) ? nx_th_32perDay; + + /** NXDMAENGFIR[40:47] + * spare + */ + (rNXDMAENGFIR, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError; + + /** NXDMAENGFIR[48] + * scom error + */ + (rNXDMAENGFIR, bit(48)) ? defaultMaskedError; + + /** NXDMAENGFIR[49] + * scom error + */ + (rNXDMAENGFIR, bit(49)) ? defaultMaskedError; + +}; + +################################################################################ +# N1 Chiplet FIR +################################################################################ + +rule rN1_CHIPLET_FIR +{ + CHECK_STOP: + N1_CHIPLET_CS_FIR & ~N1_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (N1_CHIPLET_RE_FIR >> 2) & ~N1_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gN1_CHIPLET_FIR + filter singlebit +{ + /** N1_CHIPLET_FIR[3] + * Attention from N1_LFIR + */ + (rN1_CHIPLET_FIR, bit(3)) ? analyzeN1_LFIR; + + /** N1_CHIPLET_FIR[4] + * Attention from MCFIR 2 + */ + (rN1_CHIPLET_FIR, bit(4)) ? analyzeConnectedMI2; + + /** N1_CHIPLET_FIR[5] + * Attention from MCFIR 3 + */ + (rN1_CHIPLET_FIR, bit(5)) ? analyzeConnectedMI3; + + /** N1_CHIPLET_FIR[6] + * Attention from MCDFIR + */ + (rN1_CHIPLET_FIR, bit(6)) ? analyzeMCDFIR_0; + + /** N1_CHIPLET_FIR[7] + * Attention from MCDFIR + */ + (rN1_CHIPLET_FIR, bit(7)) ? analyzeMCDFIR_1; + + /** N1_CHIPLET_FIR[8] + * Attention from VASFIR + */ + (rN1_CHIPLET_FIR, bit(8)) ? analyzeVASFIR; + + /** N1_CHIPLET_FIR[11] + * Attention from NPU0FIR 2 + */ + (rN1_CHIPLET_FIR, bit(11)) ? analyzeConnectedNPU2; + + /** N1_CHIPLET_FIR[12] + * Attention from NPU1FIR 2 + */ + (rN1_CHIPLET_FIR, bit(12)) ? analyzeConnectedNPU2; + + /** N1_CHIPLET_FIR[13] + * Attention from NPU2FIR 2 + */ + (rN1_CHIPLET_FIR, bit(13)) ? analyzeConnectedNPU2; + +}; + +################################################################################ +# N1 Chiplet Unit Checkstop FIR +################################################################################ + +rule rN1_CHIPLET_UCS_FIR +{ + UNIT_CS: + N1_CHIPLET_UCS_FIR & ~(N1_CHIPLET_UCS_FIR_MASK >> 1) & `7fffffffffffffff`; +}; + +group gN1_CHIPLET_UCS_FIR + filter singlebit +{ + /** N1_CHIPLET_UCS_FIR[1] + * Attention from MCFIR 2 + */ + (rN1_CHIPLET_UCS_FIR, bit(1)) ? analyzeConnectedMI2; + + /** N1_CHIPLET_UCS_FIR[2] + * Attention from MCFIR 3 + */ + (rN1_CHIPLET_UCS_FIR, bit(2)) ? analyzeConnectedMI3; + + /** N1_CHIPLET_UCS_FIR[5] + * Attention from VASFIR + */ + (rN1_CHIPLET_UCS_FIR, bit(5)) ? analyzeVASFIR; + + /** N1_CHIPLET_UCS_FIR[6] + * Attention from NPU0FIR 2 + */ + (rN1_CHIPLET_UCS_FIR, bit(6)) ? analyzeConnectedNPU2; + + /** N1_CHIPLET_UCS_FIR[7] + * Attention from NPU1FIR 2 + */ + (rN1_CHIPLET_UCS_FIR, bit(7)) ? analyzeConnectedNPU2; + + /** N1_CHIPLET_UCS_FIR[8] + * Attention from NPU2FIR 2 + */ + (rN1_CHIPLET_UCS_FIR, bit(8)) ? analyzeConnectedNPU2; + +}; + +################################################################################ +# N1 Chiplet Host Attention FIR +################################################################################ + +rule rN1_CHIPLET_HA_FIR +{ + HOST_ATTN: + N1_CHIPLET_HA_FIR & ~(N1_CHIPLET_HA_FIR_MASK >> 1) & `7fffffffffffffff`; +}; + +group gN1_CHIPLET_HA_FIR + filter singlebit +{ + /** N1_CHIPLET_HA_FIR[1] + * Attention from MCFIR 2 + */ + (rN1_CHIPLET_HA_FIR, bit(1)) ? analyzeConnectedMI2; + + /** N1_CHIPLET_HA_FIR[2] + * Attention from MCFIR 3 + */ + (rN1_CHIPLET_HA_FIR, bit(2)) ? analyzeConnectedMI3; + +}; + +################################################################################ +# P9 chip N1_LFIR +################################################################################ + +rule rN1_LFIR +{ + CHECK_STOP: + N1_LFIR & ~N1_LFIR_MASK & ~N1_LFIR_ACT0 & ~N1_LFIR_ACT1; + RECOVERABLE: + N1_LFIR & ~N1_LFIR_MASK & ~N1_LFIR_ACT0 & N1_LFIR_ACT1; +}; + +group gN1_LFIR + filter singlebit, + cs_root_cause +{ + /** N1_LFIR[0] + * CFIR internal parity error + */ + (rN1_LFIR, bit(0)) ? self_th_32perDay; + + /** N1_LFIR[1] + * Chiplet Control Reg: PCB Access Error + */ + (rN1_LFIR, bit(1)) ? self_th_32perDay; + + /** N1_LFIR[2] + * Clock Controller: PCB Access Error + */ + (rN1_LFIR, bit(2)) ? self_th_32perDay; + + /** N1_LFIR[3] + * Clock Controller: Summarized Error + */ + (rN1_LFIR, bit(3)) ? self_th_32perDay; + + /** N1_LFIR[4] + * PSCOM Logic: PCB Access Error + */ + (rN1_LFIR, bit(4)) ? defaultMaskedError; + + /** N1_LFIR[5] + * PSCOM Logic: Summarized internal errors + */ + (rN1_LFIR, bit(5)) ? defaultMaskedError; + + /** N1_LFIR[6] + * Therm Logic: Summarized internal errors + */ + (rN1_LFIR, bit(6)) ? defaultMaskedError; + + /** N1_LFIR[7] + * Therm Logic: PCB Access Error + */ + (rN1_LFIR, bit(7)) ? defaultMaskedError; + + /** N1_LFIR[8] + * Therm Logic: Temperature critical trip + */ + (rN1_LFIR, bit(8)) ? defaultMaskedError; + + /** N1_LFIR[9] + * Therm Logic: Temperature fatal trip + */ + (rN1_LFIR, bit(9)) ? defaultMaskedError; + + /** N1_LFIR[10] + * UNUSED in P9 + */ + (rN1_LFIR, bit(10)) ? defaultMaskedError; + + /** N1_LFIR[11] + * Debug Logic: Scom Satellite Error + */ + (rN1_LFIR, bit(11)) ? defaultMaskedError; + + /** N1_LFIR[12] + * Scom Satellite Error - Trace0 + */ + (rN1_LFIR, bit(12)) ? defaultMaskedError; + + /** N1_LFIR[13] + * Scom Satellite Error - Trace0 + */ + (rN1_LFIR, bit(13)) ? defaultMaskedError; + + /** N1_LFIR[14] + * Scom Satellite Error - Trace1 + */ + (rN1_LFIR, bit(14)) ? defaultMaskedError; + + /** N1_LFIR[15] + * Scom Satellite Error - Trace1 + */ + (rN1_LFIR, bit(15)) ? defaultMaskedError; + + /** N1_LFIR[16:23] + * spare + */ + (rN1_LFIR, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError; + + /** N1_LFIR[24] + * Unused + */ + (rN1_LFIR, bit(24)) ? defaultMaskedError; + + /** N1_LFIR[25] + * Unused + */ + (rN1_LFIR, bit(25)) ? defaultMaskedError; + + /** N1_LFIR[26:40] + * spare + */ + (rN1_LFIR, bit(26|27|28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError; + + /** N1_LFIR[41] + * Malfunction Alert or Local Checkstop + */ + (rN1_LFIR, bit(41)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip MCDFIR 0 +################################################################################ + +rule rMCDFIR_0 +{ + CHECK_STOP: + MCDFIR_0 & ~MCDFIR_0_MASK & ~MCDFIR_0_ACT0 & ~MCDFIR_0_ACT1; + RECOVERABLE: + MCDFIR_0 & ~MCDFIR_0_MASK & ~MCDFIR_0_ACT0 & MCDFIR_0_ACT1; +}; + +group gMCDFIR_0 + filter singlebit, + cs_root_cause +{ + /** MCDFIR_0[0] + * MCD array had a unrecoverable ECC error + */ + (rMCDFIR_0, bit(0)) ? self_th_32perDay; + + /** MCDFIR_0[0] + * MCD array had a unrecoverable ECC error + */ + (rMCDFIR_0, bit(0)) ? self_th_1; # NIMBUS_21,NIMBUS_23,CUMULUS_13 + + /** MCDFIR_0[1] + * MCD array had a correctable ECC error + */ + (rMCDFIR_0, bit(1)) ? defaultMaskedError; + + /** MCDFIR_0[2] + * PowerBus address Parity Error + */ + (rMCDFIR_0, bit(2)) ? self_th_1; + + /** MCDFIR_0[3] + * Register bit flip in State Machine Logic + */ + (rMCDFIR_0, bit(3)) ? self_th_1; + + /** MCDFIR_0[4] + * cl_probe command hung + */ + (rMCDFIR_0, bit(4)) ? defaultMaskedError; + + /** MCDFIR_0[5] + * cResp for cl_probe is address error. + */ + (rMCDFIR_0, bit(5)) ? defaultMaskedError; + + /** MCDFIR_0[6] + * Unsolicited cresp received + */ + (rMCDFIR_0, bit(6)) ? self_th_1; + + /** MCDFIR_0[7] + * PowerBus ttag Parity Error + */ + (rMCDFIR_0, bit(7)) ? self_th_1; + + /** MCDFIR_0[8] + * MCD scom register update error + */ + (rMCDFIR_0, bit(8)) ? self_th_1; + + /** MCDFIR_0[9] + * ack_dead_cresp received + */ + (rMCDFIR_0, bit(9)) ? defaultMaskedError; + + /** MCDFIR_0[10] + * Internal SCOM error + */ + (rMCDFIR_0, bit(10)) ? defaultMaskedError; + + /** MCDFIR_0[11] + * Internal SCOM error + */ + (rMCDFIR_0, bit(11)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip MCDFIR 1 +################################################################################ + +rule rMCDFIR_1 +{ + CHECK_STOP: + MCDFIR_1 & ~MCDFIR_1_MASK & ~MCDFIR_1_ACT0 & ~MCDFIR_1_ACT1; + RECOVERABLE: + MCDFIR_1 & ~MCDFIR_1_MASK & ~MCDFIR_1_ACT0 & MCDFIR_1_ACT1; +}; + +group gMCDFIR_1 + filter singlebit, + cs_root_cause +{ + /** MCDFIR_1[0] + * MCD array had a unrecoverable ECC error + */ + (rMCDFIR_1, bit(0)) ? self_th_32perDay; + + /** MCDFIR_1[0] + * MCD array had a unrecoverable ECC error + */ + (rMCDFIR_1, bit(0)) ? self_th_1; # NIMBUS_21,NIMBUS_23,CUMULUS_13 + + /** MCDFIR_1[1] + * MCD array had a correctable ECC error + */ + (rMCDFIR_1, bit(1)) ? defaultMaskedError; + + /** MCDFIR_1[2] + * PowerBus address Parity Error + */ + (rMCDFIR_1, bit(2)) ? self_th_1; + + /** MCDFIR_1[3] + * Register bit flip in State Machine Logic + */ + (rMCDFIR_1, bit(3)) ? self_th_1; + + /** MCDFIR_1[4] + * cl_probe command hung + */ + (rMCDFIR_1, bit(4)) ? defaultMaskedError; + + /** MCDFIR_1[5] + * cResp for cl_probe is address error. + */ + (rMCDFIR_1, bit(5)) ? defaultMaskedError; + + /** MCDFIR_1[6] + * Unsolicited cresp received + */ + (rMCDFIR_1, bit(6)) ? self_th_1; + + /** MCDFIR_1[7] + * PowerBus ttag Parity Error + */ + (rMCDFIR_1, bit(7)) ? self_th_1; + + /** MCDFIR_1[8] + * MCD scom register update error + */ + (rMCDFIR_1, bit(8)) ? self_th_1; + + /** MCDFIR_1[9] + * ack_dead_cresp received + */ + (rMCDFIR_1, bit(9)) ? defaultMaskedError; + + /** MCDFIR_1[10] + * Internal SCOM error + */ + (rMCDFIR_1, bit(10)) ? defaultMaskedError; + + /** MCDFIR_1[11] + * Internal SCOM error + */ + (rMCDFIR_1, bit(11)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip VASFIR +################################################################################ + +rule rVASFIR +{ + CHECK_STOP: + VASFIR & ~VASFIR_MASK & ~VASFIR_ACT0 & ~VASFIR_ACT1; + RECOVERABLE: + VASFIR & ~VASFIR_MASK & ~VASFIR_ACT0 & VASFIR_ACT1; + UNIT_CS: + VASFIR & ~VASFIR_MASK & VASFIR_ACT0 & VASFIR_ACT1; +}; + +group gVASFIR + filter singlebit, + cs_root_cause +{ + /** VASFIR[0] + * Egress Hardware Error + */ + (rVASFIR, bit(0)) ? self_th_1; + + /** VASFIR[1] + * Ingress Hardware Error + */ + (rVASFIR, bit(1)) ? self_th_1; + + /** VASFIR[2] + * PowerBus (CQ) Hardware Error + */ + (rVASFIR, bit(2)) ? self_th_1; + + /** VASFIR[3] + * Window Context Cache Hardware Error + */ + (rVASFIR, bit(3)) ? self_th_1; + + /** VASFIR[4] + * Register/MMIO Hardware Error + */ + (rVASFIR, bit(4)) ? self_th_1; + + /** VASFIR[5] + * PowerBus (CQ) Interface Parity Error + */ + (rVASFIR, bit(5)) ? self_th_1; + + /** VASFIR[6] + * PB(CQ) Addr Error CRESP on Read + */ + (rVASFIR, bit(6)) ? self_M_level2_L_th_1; + + /** VASFIR[7] + * PB (CQ) Address Error CRESP on Write + */ + (rVASFIR, bit(7)) ? self_M_level2_L_th_1; + + /** VASFIR[8] + * Egress Correctable ECC Error + */ + (rVASFIR, bit(8)) ? self_th_5perHour; + + /** VASFIR[9] + * Ingress Correctable ECC Error + */ + (rVASFIR, bit(9)) ? self_th_5perHour; + + /** VASFIR[10] + * PB (CQ) CE on inbound/array data + */ + (rVASFIR, bit(10)) ? defaultMaskedError; + + /** VASFIR[11] + * WC Correctable ECC Error + */ + (rVASFIR, bit(11)) ? self_th_5perHour; + + /** VASFIR[12] + * Register/MMIO Correctable ECC Error + */ + (rVASFIR, bit(12)) ? self_th_5perHour; + + /** VASFIR[13] + * PB Correctable Error on outbound data + */ + (rVASFIR, bit(13)) ? self_th_5perHour; + + /** VASFIR[14] + * PB Uncorrectable Error on outbound data + */ + (rVASFIR, bit(14)) ? self_th_1; + + /** VASFIR[15] + * PB Master State Machine Hang + */ + (rVASFIR, bit(15)) ? defaultMaskedError; + + /** VASFIR[16] + * EG Uncorrectable ECC Error + */ + (rVASFIR, bit(16)) ? self_th_1; + + /** VASFIR[17] + * IN Uncorrectable ECC Error + */ + (rVASFIR, bit(17)) ? self_th_1; + + /** VASFIR[18] + * PB UE on inbound array data + */ + (rVASFIR, bit(18)) ? self_th_1; + + /** VASFIR[19] + * WC Uncorrectable ECC Error + */ + (rVASFIR, bit(19)) ? self_th_1; + + /** VASFIR[20] + * RG/MMIO Uncorrectable ECC Error + */ + (rVASFIR, bit(20)) ? self_th_1; + + /** VASFIR[21] + * IN CAM Parity Error + */ + (rVASFIR, bit(21)) ? self_th_1; + + /** VASFIR[22] + * IN software castout to active window + */ + (rVASFIR, bit(22)) ? self_th_1; + + /** VASFIR[23] + * spare + */ + (rVASFIR, bit(23)) ? defaultMaskedError; + + /** VASFIR[24] + * EG Special UE (SUE) Error + */ + (rVASFIR, bit(24)) ? self_th_1_SUE; + + /** VASFIR[25] + * IN SUE Error + */ + (rVASFIR, bit(25)) ? self_th_1_SUE; + + /** VASFIR[26] + * PB SUE Error + */ + (rVASFIR, bit(26)) ? self_th_1_SUE; + + /** VASFIR[27] + * WC SUE Error + */ + (rVASFIR, bit(27)) ? self_th_1_SUE; + + /** VASFIR[28] + * RG/MMIO SUE Error + */ + (rVASFIR, bit(28)) ? self_th_1_SUE; + + /** VASFIR[29] + * PB Link Error on Read + */ + (rVASFIR, bit(29)) ? self_th_1; + + /** VASFIR[30] + * PB Link Error on Write + */ + (rVASFIR, bit(30)) ? defaultMaskedError; + + /** VASFIR[31] + * PB Link Abort Op Received + */ + (rVASFIR, bit(31)) ? self_th_1; + + /** VASFIR[32] + * MMIO Read to Unimplemented Reg (HYP) + */ + (rVASFIR, bit(32)) ? self_th_1; + + /** VASFIR[33] + * MMIO Read to Unimplemented Reg (OS) + */ + (rVASFIR, bit(33)) ? defaultMaskedError; + + /** VASFIR[34] + * MMIO Write to Unimplemented Reg (HYP) + */ + (rVASFIR, bit(34)) ? self_th_1; + + /** VASFIR[35] + * MMIO Write to Unimplemented Reg (OS) + */ + (rVASFIR, bit(35)) ? defaultMaskedError; + + /** VASFIR[36] + * non-8B MMIO Detected (HYP) + */ + (rVASFIR, bit(36)) ? self_th_1; + + /** VASFIR[37] + * non-8B MMIO Detected (OS) + */ + (rVASFIR, bit(37)) ? defaultMaskedError; + + /** VASFIR[38] + * Write Monitor Op to non-open Window + */ + (rVASFIR, bit(38)) ? self_th_1; + + /** VASFIR[39] + * Multiple Wr Mon Register Match + */ + (rVASFIR, bit(39)) ? self_th_1; + + /** VASFIR[40] + * Page Migration Requested but not enabled + */ + (rVASFIR, bit(40)) ? self_th_1; + + /** VASFIR[41] + * Page Migration size != FIFO size + */ + (rVASFIR, bit(41)) ? self_th_1; + + /** VASFIR[42] + * ASB Notify not claimed + */ + (rVASFIR, bit(42)) ? self_th_1; + + /** VASFIR[43] + * Write Monitor Op error + */ + (rVASFIR, bit(43)) ? self_th_1; + + /** VASFIR[44] + * VAS rejected a paste command + */ + (rVASFIR, bit(44)) ? defaultMaskedError; + + /** VASFIR[45] + * Data Hang + */ + (rVASFIR, bit(45)) ? defaultMaskedError; + + /** VASFIR[46] + * Incoming PB Parity Error + */ + (rVASFIR, bit(46)) ? self_th_1; + + /** VASFIR[47] + * Error from SCOMFIR satellite + */ + (rVASFIR, bit(47)) ? defaultMaskedError; + + /** VASFIR[48] + * NX_VAS_Local_XSTOP received + */ + (rVASFIR, bit(48)) ? self_th_1; + + /** VASFIR[49] + * scom error + */ + (rVASFIR, bit(49)) ? defaultMaskedError; + + /** VASFIR[50:51] + * spare + */ + (rVASFIR, bit(50|51)) ? defaultMaskedError; + + /** VASFIR[52] + * scom error + */ + (rVASFIR, bit(52)) ? defaultMaskedError; + + /** VASFIR[53] + * scom error + */ + (rVASFIR, bit(53)) ? defaultMaskedError; + +}; + +################################################################################ +# N2 Chiplet FIR +################################################################################ + +rule rN2_CHIPLET_FIR +{ + CHECK_STOP: + N2_CHIPLET_CS_FIR & ~N2_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (N2_CHIPLET_RE_FIR >> 2) & ~N2_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gN2_CHIPLET_FIR + filter singlebit +{ + /** N2_CHIPLET_FIR[3] + * Attention from N2_LFIR + */ + (rN2_CHIPLET_FIR, bit(3)) ? analyzeN2_LFIR; + + /** N2_CHIPLET_FIR[5] + * Attention from PHBNFIR 0 + */ + (rN2_CHIPLET_FIR, bit(5)) ? analyzeConnectedPHB0; + + /** N2_CHIPLET_FIR[6] + * Attention from PHBNFIR 1 + */ + (rN2_CHIPLET_FIR, bit(6)) ? analyzeConnectedPHB1; + + /** N2_CHIPLET_FIR[7] + * Attention from PHBNFIR 3 + */ + (rN2_CHIPLET_FIR, bit(7)) ? analyzeConnectedPHB3; + + /** N2_CHIPLET_FIR[8] + * Attention from PHBNFIR 2 + */ + (rN2_CHIPLET_FIR, bit(8)) ? analyzeConnectedPHB2; + + /** N2_CHIPLET_FIR[9] + * Attention from PHBNFIR 4 + */ + (rN2_CHIPLET_FIR, bit(9)) ? analyzeConnectedPHB4; + + /** N2_CHIPLET_FIR[10] + * Attention from PHBNFIR 5 + */ + (rN2_CHIPLET_FIR, bit(10)) ? analyzeConnectedPHB5; + + /** N2_CHIPLET_FIR[11] + * Attention from PSIFIR + */ + (rN2_CHIPLET_FIR, bit(11)) ? analyzePSIFIR; + +}; + +################################################################################ +# P9 chip N2_LFIR +################################################################################ + +rule rN2_LFIR +{ + CHECK_STOP: + N2_LFIR & ~N2_LFIR_MASK & ~N2_LFIR_ACT0 & ~N2_LFIR_ACT1; + RECOVERABLE: + N2_LFIR & ~N2_LFIR_MASK & ~N2_LFIR_ACT0 & N2_LFIR_ACT1; +}; + +group gN2_LFIR + filter singlebit, + cs_root_cause +{ + /** N2_LFIR[0] + * CFIR internal parity error + */ + (rN2_LFIR, bit(0)) ? self_th_32perDay; + + /** N2_LFIR[1] + * Chiplet Control Reg: PCB Access Error + */ + (rN2_LFIR, bit(1)) ? self_th_32perDay; + + /** N2_LFIR[2] + * Clock Controller: PCB Access Error + */ + (rN2_LFIR, bit(2)) ? self_th_32perDay; + + /** N2_LFIR[3] + * Clock Controller: Summarized Error + */ + (rN2_LFIR, bit(3)) ? self_th_32perDay; + + /** N2_LFIR[4] + * PSCOM Logic: PCB Access Error + */ + (rN2_LFIR, bit(4)) ? defaultMaskedError; + + /** N2_LFIR[5] + * PSCOM Logic: Summarized internal errors + */ + (rN2_LFIR, bit(5)) ? defaultMaskedError; + + /** N2_LFIR[6] + * Therm Logic: Summarized internal errors + */ + (rN2_LFIR, bit(6)) ? defaultMaskedError; + + /** N2_LFIR[7] + * Therm Logic: PCB Access Error + */ + (rN2_LFIR, bit(7)) ? defaultMaskedError; + + /** N2_LFIR[8] + * Therm Logic: Temperature critical trip + */ + (rN2_LFIR, bit(8)) ? defaultMaskedError; + + /** N2_LFIR[9] + * Therm Logic: Temperature fatal trip + */ + (rN2_LFIR, bit(9)) ? defaultMaskedError; + + /** N2_LFIR[10] + * UNUSED in P9 + */ + (rN2_LFIR, bit(10)) ? defaultMaskedError; + + /** N2_LFIR[11] + * Debug Logic: Scom Satellite Error + */ + (rN2_LFIR, bit(11)) ? defaultMaskedError; + + /** N2_LFIR[12] + * Scom Satellite Error - Trace0 + */ + (rN2_LFIR, bit(12)) ? defaultMaskedError; + + /** N2_LFIR[13] + * Scom Satellite Error - Trace0 + */ + (rN2_LFIR, bit(13)) ? defaultMaskedError; + + /** N2_LFIR[14] + * Scom Satellite Error - Trace1 + */ + (rN2_LFIR, bit(14)) ? defaultMaskedError; + + /** N2_LFIR[15] + * Scom Satellite Error - Trace1 + */ + (rN2_LFIR, bit(15)) ? defaultMaskedError; + + /** N2_LFIR[16:23] + * spare + */ + (rN2_LFIR, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError; + + /** N2_LFIR[24] + * Unused + */ + (rN2_LFIR, bit(24)) ? defaultMaskedError; + + /** N2_LFIR[25] + * Unused + */ + (rN2_LFIR, bit(25)) ? defaultMaskedError; + + /** N2_LFIR[26:40] + * spare + */ + (rN2_LFIR, bit(26|27|28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError; + + /** N2_LFIR[41] + * Malfunction Alert or Local Checkstop + */ + (rN2_LFIR, bit(41)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip PSIFIR +################################################################################ + +rule rPSIFIR +{ + CHECK_STOP: + PSIFIR & ~PSIFIR_MASK & ~PSIFIR_ACT0 & ~PSIFIR_ACT1; + RECOVERABLE: + PSIFIR & ~PSIFIR_MASK & ~PSIFIR_ACT0 & PSIFIR_ACT1; +}; + +group gPSIFIR + filter singlebit, + cs_root_cause +{ + /** PSIFIR[0:4] + * spare + */ + (rPSIFIR, bit(0|1|2|3|4)) ? defaultMaskedError; + + /** PSIFIR[5] + * scom error + */ + (rPSIFIR, bit(5)) ? defaultMaskedError; + + /** PSIFIR[6] + * scom error + */ + (rPSIFIR, bit(6)) ? defaultMaskedError; + +}; + +################################################################################ +# N3 Chiplet FIR +################################################################################ + +rule rN3_CHIPLET_FIR +{ + CHECK_STOP: + N3_CHIPLET_CS_FIR & ~N3_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (N3_CHIPLET_RE_FIR >> 2) & ~N3_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gN3_CHIPLET_FIR + filter singlebit +{ + /** N3_CHIPLET_FIR[3] + * Attention from N3_LFIR + */ + (rN3_CHIPLET_FIR, bit(3)) ? analyzeN3_LFIR; + + /** N3_CHIPLET_FIR[4] + * Attention from MCFIR 0 + */ + (rN3_CHIPLET_FIR, bit(4)) ? analyzeConnectedMI0; + + /** N3_CHIPLET_FIR[5] + * Attention from MCFIR 1 + */ + (rN3_CHIPLET_FIR, bit(5)) ? analyzeConnectedMI1; + + /** N3_CHIPLET_FIR[6] + * Attention from PBWESTFIR + */ + (rN3_CHIPLET_FIR, bit(6)) ? analyzePBWESTFIR; + + /** N3_CHIPLET_FIR[7] + * Attention from PBCENTFIR + */ + (rN3_CHIPLET_FIR, bit(7)) ? analyzePBCENTFIR; + + /** N3_CHIPLET_FIR[8] + * Attention from PBEASTFIR + */ + (rN3_CHIPLET_FIR, bit(8)) ? analyzePBEASTFIR; + + /** N3_CHIPLET_FIR[10] + * Attention from NPU0FIR 0 + */ + (rN3_CHIPLET_FIR, bit(10)) ? analyzeConnectedNPU0; + + /** N3_CHIPLET_FIR[11] + * Attention from NPU1FIR 0 + */ + (rN3_CHIPLET_FIR, bit(11)) ? analyzeConnectedNPU0; + + /** N3_CHIPLET_FIR[12] + * Attention from NMMUCQFIR + */ + (rN3_CHIPLET_FIR, bit(12)) ? analyzeNMMUCQFIR; + + /** N3_CHIPLET_FIR[13] + * Attention from NMMUFIR + */ + (rN3_CHIPLET_FIR, bit(13)) ? analyzeNMMUFIR; + + /** N3_CHIPLET_FIR[14] + * Attention from PBPPEFIR + */ + (rN3_CHIPLET_FIR, bit(14)) ? analyzePBPPEFIR; + + /** N3_CHIPLET_FIR[15] + * Attention from PBIOEFIR + */ + (rN3_CHIPLET_FIR, bit(15)) ? analyzePBIOEFIR; + + /** N3_CHIPLET_FIR[16] + * Attention from PBIOOFIR + */ + (rN3_CHIPLET_FIR, bit(16)) ? analyzePBIOOFIR; + + /** N3_CHIPLET_FIR[17] + * Attention from INTCQFIR + */ + (rN3_CHIPLET_FIR, bit(17)) ? analyzeINTCQFIR; + + /** N3_CHIPLET_FIR[18] + * Attention from PBAFIR + */ + (rN3_CHIPLET_FIR, bit(18)) ? analyzePBAFIR; + + /** N3_CHIPLET_FIR[19] + * Attention from PSIHBFIR + */ + (rN3_CHIPLET_FIR, bit(19)) ? analyzePSIHBFIR; + + /** N3_CHIPLET_FIR[20] + * Attention from PBAMFIR + */ + (rN3_CHIPLET_FIR, bit(20)) ? analyzePBAMFIR; + + /** N3_CHIPLET_FIR[21] + * Attention from NPU0FIR 1 + */ + (rN3_CHIPLET_FIR, bit(21)) ? analyzeConnectedNPU1; + + /** N3_CHIPLET_FIR[22] + * Attention from ENHCAFIR + */ + (rN3_CHIPLET_FIR, bit(22)) ? analyzeENHCAFIR; + + /** N3_CHIPLET_FIR[23] + * Attention from NPU2FIR 0 + */ + (rN3_CHIPLET_FIR, bit(23)) ? analyzeConnectedNPU0; + + /** N3_CHIPLET_FIR[24] + * Attention from NPU1FIR 1 + */ + (rN3_CHIPLET_FIR, bit(24)) ? analyzeConnectedNPU1; + + /** N3_CHIPLET_FIR[25] + * Attention from NPU2FIR 1 + */ + (rN3_CHIPLET_FIR, bit(25)) ? analyzeConnectedNPU1; + +}; + +################################################################################ +# N3 Chiplet Unit Checkstop FIR +################################################################################ + +rule rN3_CHIPLET_UCS_FIR +{ + UNIT_CS: + N3_CHIPLET_UCS_FIR & ~(N3_CHIPLET_UCS_FIR_MASK >> 1) & `7fffffffffffffff`; +}; + +group gN3_CHIPLET_UCS_FIR + filter singlebit +{ + /** N3_CHIPLET_UCS_FIR[1] + * Attention from MCFIR 0 + */ + (rN3_CHIPLET_UCS_FIR, bit(1)) ? analyzeConnectedMI0; + + /** N3_CHIPLET_UCS_FIR[2] + * Attention from MCFIR 1 + */ + (rN3_CHIPLET_UCS_FIR, bit(2)) ? analyzeConnectedMI1; + + /** N3_CHIPLET_UCS_FIR[3] + * Attention from NPU0FIR 1 + */ + (rN3_CHIPLET_UCS_FIR, bit(3)) ? analyzeConnectedNPU1; + + /** N3_CHIPLET_UCS_FIR[4] + * Attention from NPU1FIR 1 + */ + (rN3_CHIPLET_UCS_FIR, bit(4)) ? analyzeConnectedNPU1; + + /** N3_CHIPLET_UCS_FIR[5] + * Attention from NPU2FIR 1 + */ + (rN3_CHIPLET_UCS_FIR, bit(5)) ? analyzeConnectedNPU1; + + /** N3_CHIPLET_UCS_FIR[6] + * Attention from NPU2FIR 0 + */ + (rN3_CHIPLET_UCS_FIR, bit(6)) ? analyzeConnectedNPU0; + + /** N3_CHIPLET_UCS_FIR[7] + * Attention from NPU0FIR 0 + */ + (rN3_CHIPLET_UCS_FIR, bit(7)) ? analyzeConnectedNPU0; + + /** N3_CHIPLET_UCS_FIR[8] + * Attention from NPU1FIR 0 + */ + (rN3_CHIPLET_UCS_FIR, bit(8)) ? analyzeConnectedNPU0; + + /** N3_CHIPLET_UCS_FIR[9] + * Attention from NMMUCQFIR + */ + (rN3_CHIPLET_UCS_FIR, bit(9)) ? analyzeNMMUCQFIR; + + /** N3_CHIPLET_UCS_FIR[10] + * Attention from NMMUFIR + */ + (rN3_CHIPLET_UCS_FIR, bit(10)) ? analyzeNMMUFIR; + +}; + +################################################################################ +# N3 Chiplet Host Attention FIR +################################################################################ + +rule rN3_CHIPLET_HA_FIR +{ + HOST_ATTN: + N3_CHIPLET_HA_FIR & ~(N3_CHIPLET_HA_FIR_MASK >> 1) & `7fffffffffffffff`; +}; + +group gN3_CHIPLET_HA_FIR + filter singlebit +{ + /** N3_CHIPLET_HA_FIR[1] + * Attention from MCFIR 0 + */ + (rN3_CHIPLET_HA_FIR, bit(1)) ? analyzeConnectedMI0; + + /** N3_CHIPLET_HA_FIR[2] + * Attention from MCFIR 1 + */ + (rN3_CHIPLET_HA_FIR, bit(2)) ? analyzeConnectedMI1; + +}; + +################################################################################ +# P9 chip N3_LFIR +################################################################################ + +rule rN3_LFIR +{ + CHECK_STOP: + N3_LFIR & ~N3_LFIR_MASK & ~N3_LFIR_ACT0 & ~N3_LFIR_ACT1; + RECOVERABLE: + N3_LFIR & ~N3_LFIR_MASK & ~N3_LFIR_ACT0 & N3_LFIR_ACT1; +}; + +group gN3_LFIR + filter singlebit, + cs_root_cause +{ + /** N3_LFIR[0] + * CFIR internal parity error + */ + (rN3_LFIR, bit(0)) ? self_th_32perDay; + + /** N3_LFIR[1] + * Chiplet Control Reg: PCB Access Error + */ + (rN3_LFIR, bit(1)) ? self_th_32perDay; + + /** N3_LFIR[2] + * Clock Controller: PCB Access Error + */ + (rN3_LFIR, bit(2)) ? self_th_32perDay; + + /** N3_LFIR[3] + * Clock Controller: Summarized Error + */ + (rN3_LFIR, bit(3)) ? self_th_32perDay; + + /** N3_LFIR[4] + * PSCOM Logic: PCB Access Error + */ + (rN3_LFIR, bit(4)) ? defaultMaskedError; + + /** N3_LFIR[5] + * PSCOM Logic: Summarized internal errors + */ + (rN3_LFIR, bit(5)) ? defaultMaskedError; + + /** N3_LFIR[6] + * Therm Logic: Summarized internal errors + */ + (rN3_LFIR, bit(6)) ? defaultMaskedError; + + /** N3_LFIR[7] + * Therm Logic: PCB Access Error + */ + (rN3_LFIR, bit(7)) ? defaultMaskedError; + + /** N3_LFIR[8] + * Therm Logic: Temperature critical trip + */ + (rN3_LFIR, bit(8)) ? defaultMaskedError; + + /** N3_LFIR[9] + * Therm Logic: Temperature fatal trip + */ + (rN3_LFIR, bit(9)) ? defaultMaskedError; + + /** N3_LFIR[10] + * UNUSED in P9 + */ + (rN3_LFIR, bit(10)) ? defaultMaskedError; + + /** N3_LFIR[11] + * Debug Logic: Scom Satellite Error + */ + (rN3_LFIR, bit(11)) ? defaultMaskedError; + + /** N3_LFIR[12] + * Scom Satellite Error - Trace0 + */ + (rN3_LFIR, bit(12)) ? defaultMaskedError; + + /** N3_LFIR[13] + * Scom Satellite Error - Trace0 + */ + (rN3_LFIR, bit(13)) ? defaultMaskedError; + + /** N3_LFIR[14] + * Scom Satellite Error - Trace1 + */ + (rN3_LFIR, bit(14)) ? defaultMaskedError; + + /** N3_LFIR[15] + * Scom Satellite Error - Trace1 + */ + (rN3_LFIR, bit(15)) ? defaultMaskedError; + + /** N3_LFIR[16:23] + * spare + */ + (rN3_LFIR, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError; + + /** N3_LFIR[24] + * Unused + */ + (rN3_LFIR, bit(24)) ? defaultMaskedError; + + /** N3_LFIR[25] + * Unused + */ + (rN3_LFIR, bit(25)) ? defaultMaskedError; + + /** N3_LFIR[26:31] + * spare + */ + (rN3_LFIR, bit(26|27|28|29|30|31)) ? defaultMaskedError; + + /** N3_LFIR[32] + * deadman timer expired + */ + (rN3_LFIR, bit(32)) ? deadmanTimer; + + /** N3_LFIR[33] + * system quiesce failed + */ + (rN3_LFIR, bit(33)) ? self_th_1; + + /** N3_LFIR[34] + * chip quiesce failed + */ + (rN3_LFIR, bit(34)) ? self_th_1; + + /** N3_LFIR[35:40] + * spare + */ + (rN3_LFIR, bit(35|36|37|38|39|40)) ? defaultMaskedError; + + /** N3_LFIR[41] + * Malfunction Alert or Local Checkstop + */ + (rN3_LFIR, bit(41)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip PBWESTFIR +################################################################################ + +rule rPBWESTFIR +{ + CHECK_STOP: + PBWESTFIR & ~PBWESTFIR_MASK & ~PBWESTFIR_ACT0 & ~PBWESTFIR_ACT1; + RECOVERABLE: + PBWESTFIR & ~PBWESTFIR_MASK & ~PBWESTFIR_ACT0 & PBWESTFIR_ACT1; +}; + +group gPBWESTFIR + filter singlebit, + cs_root_cause +{ + /** PBWESTFIR[0] + * pbeq0 hw1 error, PE in custom array + */ + (rPBWESTFIR, bit(0)) ? self_th_1; + + /** PBWESTFIR[1] + * pbeq0 hw2 error, PE in custom array + */ + (rPBWESTFIR, bit(1)) ? self_th_1; + + /** PBWESTFIR[2] + * pbieq0_pbh_protocol_error + */ + (rPBWESTFIR, bit(2)) ? self_th_1; + + /** PBWESTFIR[3] + * pbieq0_pbh_overflow_error + */ + (rPBWESTFIR, bit(3)) ? self_th_1; + + /** PBWESTFIR[4] + * pbeq1 hw1 error, PE in custom array + */ + (rPBWESTFIR, bit(4)) ? self_th_1; + + /** PBWESTFIR[5] + * pbeq1 hw2 error, PE in custom array + */ + (rPBWESTFIR, bit(5)) ? self_th_1; + + /** PBWESTFIR[6] + * pbieq1_pbh_protocol_error + */ + (rPBWESTFIR, bit(6)) ? self_th_1; + + /** PBWESTFIR[7] + * pbieq1_pbh_overflow_error + */ + (rPBWESTFIR, bit(7)) ? self_th_1; + + /** PBWESTFIR[8] + * pbeq2 hw1 error, PE in custom array + */ + (rPBWESTFIR, bit(8)) ? self_th_1; + + /** PBWESTFIR[9] + * pbeq2 hw2 error, PE in custom array + */ + (rPBWESTFIR, bit(9)) ? self_th_1; + + /** PBWESTFIR[10] + * pbieq2_pbh_protocol_error + */ + (rPBWESTFIR, bit(10)) ? self_th_1; + + /** PBWESTFIR[11] + * pbieq2_pbh_overflow_error + */ + (rPBWESTFIR, bit(11)) ? self_th_1; + + /** PBWESTFIR[12] + * pbeq3 hw1 error, PE in custom array + */ + (rPBWESTFIR, bit(12)) ? self_th_1; + + /** PBWESTFIR[13] + * pbeq3 hw2 error, PE in custom array + */ + (rPBWESTFIR, bit(13)) ? self_th_1; + + /** PBWESTFIR[14] + * pbieq3_pbh_protocol_error + */ + (rPBWESTFIR, bit(14)) ? self_th_1; + + /** PBWESTFIR[15] + * pbieq3_pbh_overflow_error + */ + (rPBWESTFIR, bit(15)) ? self_th_1; + + /** PBWESTFIR[16:31] + * spare + */ + (rPBWESTFIR, bit(16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31)) ? defaultMaskedError; + + /** PBWESTFIR[32] + * scom error + */ + (rPBWESTFIR, bit(32)) ? defaultMaskedError; + + /** PBWESTFIR[33] + * scom error + */ + (rPBWESTFIR, bit(33)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip PBCENTFIR +################################################################################ + +rule rPBCENTFIR +{ + CHECK_STOP: + PBCENTFIR & ~PBCENTFIR_MASK & ~PBCENTFIR_ACT0 & ~PBCENTFIR_ACT1; + RECOVERABLE: + PBCENTFIR & ~PBCENTFIR_MASK & ~PBCENTFIR_ACT0 & PBCENTFIR_ACT1; +}; + +group gPBCENTFIR + filter singlebit, + cs_root_cause +{ + /** PBCENTFIR[0] + * pb protocol_error + */ + (rPBCENTFIR, bit(0)) ? level2_M_self_L_th_1; + + /** PBCENTFIR[1] + * pb overflow error + */ + (rPBCENTFIR, bit(1)) ? level2_M_self_L_th_1; + + /** PBCENTFIR[2] + * pw hw parity error + */ + (rPBCENTFIR, bit(2)) ? level2_M_self_L_th_1; + + /** PBCENTFIR[3] + * spare + */ + (rPBCENTFIR, bit(3)) ? defaultMaskedError; + + /** PBCENTFIR[4] + * pb coherency error + */ + (rPBCENTFIR, bit(4)) ? level2_M_self_L_th_1; + + /** PBCENTFIR[5] + * pb cresp addr error + */ + (rPBCENTFIR, bit(5)) ? defaultMaskedError; + + /** PBCENTFIR[6] + * pb cresp error + */ + (rPBCENTFIR, bit(6)) ? level2_M_self_L_th_1; + + /** PBCENTFIR[7] + * pb hang recovery limit error + */ + (rPBCENTFIR, bit(7)) ? defaultMaskedError; + + /** PBCENTFIR[8] + * pb data_route_error + */ + (rPBCENTFIR, bit(8)) ? level2_M_self_L_th_1; + + /** PBCENTFIR[9] + * pb hang_recovery_gte_level1 + */ + (rPBCENTFIR, bit(9)) ? pb_cent_hang_recovery_gte; + + /** PBCENTFIR[10] + * pb fsp checkstop + */ + (rPBCENTFIR, bit(10)) ? level2_dump_SW; + + /** PBCENTFIR[11:15] + * spare + */ + (rPBCENTFIR, bit(11|12|13|14|15)) ? defaultMaskedError; + + /** PBCENTFIR[16] + * scom error + */ + (rPBCENTFIR, bit(16)) ? defaultMaskedError; + + /** PBCENTFIR[17] + * scom error + */ + (rPBCENTFIR, bit(17)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip PBEASTFIR +################################################################################ + +rule rPBEASTFIR +{ + CHECK_STOP: + PBEASTFIR & ~PBEASTFIR_MASK & ~PBEASTFIR_ACT0 & ~PBEASTFIR_ACT1; + RECOVERABLE: + PBEASTFIR & ~PBEASTFIR_MASK & ~PBEASTFIR_ACT0 & PBEASTFIR_ACT1; +}; + +group gPBEASTFIR + filter singlebit, + cs_root_cause +{ + /** PBEASTFIR[0] + * pbieq4_pbh_hw1_error + */ + (rPBEASTFIR, bit(0)) ? self_th_1; + + /** PBEASTFIR[1] + * pbieq4_pbh_hw2_error + */ + (rPBEASTFIR, bit(1)) ? self_th_1; + + /** PBEASTFIR[2] + * pbieq4_pbh_protocol_error + */ + (rPBEASTFIR, bit(2)) ? level2_M_self_L_th_1; + + /** PBEASTFIR[3] + * pbieq4_pbh_overflow_error + */ + (rPBEASTFIR, bit(3)) ? level2_M_self_L_th_1; + + /** PBEASTFIR[4] + * pbieq5_pbh_hw1_error + */ + (rPBEASTFIR, bit(4)) ? self_th_1; + + /** PBEASTFIR[5] + * pbieq5_pbh_hw2_error + */ + (rPBEASTFIR, bit(5)) ? self_th_1; + + /** PBEASTFIR[6] + * pbieq5_pbh_protocol_error + */ + (rPBEASTFIR, bit(6)) ? level2_M_self_L_th_1; + + /** PBEASTFIR[7] + * pbieq5_pbh_overflow_error + */ + (rPBEASTFIR, bit(7)) ? level2_M_self_L_th_1; + + /** PBEASTFIR[8:15] + * spare + */ + (rPBEASTFIR, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError; + + /** PBEASTFIR[16] + * pb data_overflow_error + */ + (rPBEASTFIR, bit(16)) ? level2_M_self_L_th_1; + + /** PBEASTFIR[17] + * pb data_protocol_error + */ + (rPBEASTFIR, bit(17)) ? level2_M_self_L_th_1; + + /** PBEASTFIR[18] + * pb data_route_error + */ + (rPBEASTFIR, bit(18)) ? level2_M_self_L_th_1; + + /** PBEASTFIR[19:30] + * spare + */ + (rPBEASTFIR, bit(19|20|21|22|23|24|25|26|27|28|29|30)) ? defaultMaskedError; + + /** PBEASTFIR[31] + * Hypervisor initiated checkstop for TI + */ + (rPBEASTFIR, bit(31)) ? level2_th_1; + + /** PBEASTFIR[32] + * scom error + */ + (rPBEASTFIR, bit(32)) ? defaultMaskedError; + + /** PBEASTFIR[33] + * scom error + */ + (rPBEASTFIR, bit(33)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip PBPPEFIR +################################################################################ + +rule rPBPPEFIR +{ + CHECK_STOP: + PBPPEFIR & ~PBPPEFIR_MASK & ~PBPPEFIR_ACT0 & ~PBPPEFIR_ACT1; + RECOVERABLE: + PBPPEFIR & ~PBPPEFIR_MASK & ~PBPPEFIR_ACT0 & PBPPEFIR_ACT1; +}; + +group gPBPPEFIR + filter singlebit, + cs_root_cause +{ + /** PBPPEFIR[0] + * PPE asserted an internally detected err + */ + (rPBPPEFIR, bit(0)) ? threshold_and_mask_self; + + /** PBPPEFIR[1] + * PPE err on ext interface to the Mem + */ + (rPBPPEFIR, bit(1)) ? threshold_and_mask_self; + + /** PBPPEFIR[2] + * PPE halted due to lack of progress. + */ + (rPBPPEFIR, bit(2)) ? threshold_and_mask_self; + + /** PBPPEFIR[3] + * PPE halted on breakpoint event. + */ + (rPBPPEFIR, bit(3)) ? threshold_and_mask_self; + + /** PBPPEFIR[4] + * PPE watchdog expired + */ + (rPBPPEFIR, bit(4)) ? defaultMaskedError; + + /** PBPPEFIR[5] + * PPE halt + */ + (rPBPPEFIR, bit(5)) ? defaultMaskedError; + + /** PBPPEFIR[6] + * PPE debug trigger + */ + (rPBPPEFIR, bit(6)) ? defaultMaskedError; + + /** PBPPEFIR[7] + * SRAM uncorrectable error + */ + (rPBPPEFIR, bit(7)) ? threshold_and_mask_self; + + /** PBPPEFIR[8] + * SRM correctable error + */ + (rPBPPEFIR, bit(8)) ? threshold_and_mask_self; + + /** PBPPEFIR[9] + * Scrub timer tick while scrub pending + */ + (rPBPPEFIR, bit(9)) ? threshold_and_mask_self; + + /** PBPPEFIR[10] + * reserved + */ + (rPBPPEFIR, bit(10)) ? defaultMaskedError; + + /** PBPPEFIR[11] + * spare + */ + (rPBPPEFIR, bit(11)) ? defaultMaskedError; + + /** PBPPEFIR[12] + * scom error + */ + (rPBPPEFIR, bit(12)) ? defaultMaskedError; + + /** PBPPEFIR[13] + * scom error + */ + (rPBPPEFIR, bit(13)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip PBAFIR +################################################################################ + +rule rPBAFIR +{ + CHECK_STOP: + PBAFIR & ~PBAFIR_MASK & ~PBAFIR_ACT0 & ~PBAFIR_ACT1; + RECOVERABLE: + PBAFIR & ~PBAFIR_MASK & ~PBAFIR_ACT0 & PBAFIR_ACT1; +}; + +group gPBAFIR + filter singlebit, + cs_root_cause +{ + /** PBAFIR[0] + * PBA OCI Addr PE err + */ + (rPBAFIR, bit(0)) ? self_th_1; + + /** PBAFIR[1] + * PBA CRESP Addr Error for Read + */ + (rPBAFIR, bit(1)) ? defaultMaskedError; + + /** PBAFIR[2] + * PBA Read Data Timeout + */ + (rPBAFIR, bit(2)) ? defaultMaskedError; + + /** PBAFIR[3] + * PBA Read Data SUE Error + */ + (rPBAFIR, bit(3)) ? defaultMaskedError; + + /** PBAFIR[4] + * PBA Read Data UE Error + */ + (rPBAFIR, bit(4)) ? self_th_1; + + /** PBAFIR[5] + * PBA Read Data CE Error + */ + (rPBAFIR, bit(5)) ? self_th_32perDay; + + /** PBAFIR[6] + * PBA OCI Slave Initialization Error + */ + (rPBAFIR, bit(6)) ? level2_dump_SW; + + /** PBAFIR[7] + * OCI Write Data Parity Error + */ + (rPBAFIR, bit(7)) ? self_th_1; + + /** PBAFIR[8] + * spare + */ + (rPBAFIR, bit(8)) ? defaultMaskedError; + + /** PBAFIR[9] + * PBA Unexpected CRESP + */ + (rPBAFIR, bit(9)) ? level2_th_1; + + /** PBAFIR[10] + * PBA Unexpected Data PB data received + */ + (rPBAFIR, bit(10)) ? level2_th_1; + + /** PBAFIR[11] + * PBA Tag parity Error + */ + (rPBAFIR, bit(11)) ? self_th_1; + + /** PBAFIR[12] + * PBA CRESP Addr Error for Write + */ + (rPBAFIR, bit(12)) ? level2_th_1; + + /** PBAFIR[13] + * PBA Invalid CRESP + */ + (rPBAFIR, bit(13)) ? level2_th_1; + + /** PBAFIR[14] + * PBA CRESP ACK Dead response r + */ + (rPBAFIR, bit(14)) ? defaultMaskedError; + + /** PBAFIR[15] + * PBA OPERATIONAL Timeout detected + */ + (rPBAFIR, bit(15)) ? level2_th_1; + + /** PBAFIR[16] + * BCUE Setup Error + */ + (rPBAFIR, bit(16)) ? defaultMaskedError; + + /** PBAFIR[17] + * BCUE PowerBus Link + */ + (rPBAFIR, bit(17)) ? defaultMaskedError; + + /** PBAFIR[18] + * PBA CRESP Addr Error for BC Write + */ + (rPBAFIR, bit(18)) ? defaultMaskedError; + + /** PBAFIR[19] + * BCUE Read Data Parity Error OR MRDERR + */ + (rPBAFIR, bit(19)) ? defaultMaskedError; + + /** PBAFIR[20] + * BCDE Setup Error Block Copy Error + */ + (rPBAFIR, bit(20)) ? defaultMaskedError; + + /** PBAFIR[21] + * BCDE PowerBus Link error + */ + (rPBAFIR, bit(21)) ? defaultMaskedError; + + /** PBAFIR[22] + * PBA CRESP Addr Error for BC Read + */ + (rPBAFIR, bit(22)) ? defaultMaskedError; + + /** PBAFIR[23] + * PBA Read Data Timeout + */ + (rPBAFIR, bit(23)) ? defaultMaskedError; + + /** PBAFIR[24] + * PBA Read Data SUE Error + */ + (rPBAFIR, bit(24)) ? defaultMaskedError; + + /** PBAFIR[25] + * PBA Read Data UE Error + */ + (rPBAFIR, bit(25)) ? defaultMaskedError; + + /** PBAFIR[26] + * PBA Read Data CE Error + */ + (rPBAFIR, bit(26)) ? defaultMaskedError; + + /** PBAFIR[27] + * BCDE Write Data error + */ + (rPBAFIR, bit(27)) ? defaultMaskedError; + + /** PBAFIR[28] + * Internal Logic Error. + */ + (rPBAFIR, bit(28)) ? self_th_1; + + /** PBAFIR[29] + * Byte count is less than full cache line + */ + (rPBAFIR, bit(29)) ? level2_dump_SW; + + /** PBAFIR[30] + * Illegal access to OCI Register. + */ + (rPBAFIR, bit(30)) ? level2_dump_SW; + + /** PBAFIR[31] + * Push Write Error. + */ + (rPBAFIR, bit(31)) ? defaultMaskedError; + + /** PBAFIR[32] + * PBAXRCV Low data before High Data + */ + (rPBAFIR, bit(32)) ? defaultMaskedError; + + /** PBAFIR[33] + * PBAXRCV low data timeout + */ + (rPBAFIR, bit(33)) ? defaultMaskedError; + + /** PBAFIR[34] + * PBA Reservation timeout + */ + (rPBAFIR, bit(34)) ? defaultMaskedError; + + /** PBAFIR[35] + * Illegal PBAX Flow. + */ + (rPBAFIR, bit(35)) ? defaultMaskedError; + + /** PBAFIR[36] + * PBA engine retry threshold reached + */ + (rPBAFIR, bit(36)) ? defaultMaskedError; + + /** PBAFIR[37] + * PBA engine retry threshold reached + */ + (rPBAFIR, bit(37)) ? defaultMaskedError; + + /** PBAFIR[38] + * PBAXSND Reservation Timeout + */ + (rPBAFIR, bit(38)) ? defaultMaskedError; + + /** PBAFIR[39] + * PBAXSND Reservation Error. + */ + (rPBAFIR, bit(39)) ? defaultMaskedError; + + /** PBAFIR[40] + * PBA CRESP ACK Dead response + */ + (rPBAFIR, bit(40)) ? defaultMaskedError; + + /** PBAFIR[41:43] + * spare + */ + (rPBAFIR, bit(41|42|43)) ? defaultMaskedError; + + /** PBAFIR[44] + * Internal fir parity error duplicate + */ + (rPBAFIR, bit(44)) ? defaultMaskedError; + + /** PBAFIR[45] + * Internal fir parity error + */ + (rPBAFIR, bit(45)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip PSIHBFIR +################################################################################ + +rule rPSIHBFIR +{ + CHECK_STOP: + PSIHBFIR & ~PSIHBFIR_MASK & ~PSIHBFIR_ACT0 & ~PSIHBFIR_ACT1; + RECOVERABLE: + PSIHBFIR & ~PSIHBFIR_MASK & ~PSIHBFIR_ACT0 & PSIHBFIR_ACT1; +}; + +group gPSIHBFIR + filter singlebit, + cs_root_cause +{ + /** PSIHBFIR[0] + * CE from PowerBus data + */ + (rPSIHBFIR, bit(0)) ? self_th_32perDay; + + /** PSIHBFIR[1] + * UE from PowerBus data + */ + (rPSIHBFIR, bit(1)) ? self_th_1; + + /** PSIHBFIR[2] + * SUE from PowerBus data + */ + (rPSIHBFIR, bit(2)) ? defaultMaskedError; + + /** PSIHBFIR[3] + * Interrupt Condition present in PSIHB + */ + (rPSIHBFIR, bit(3)) ? defaultMaskedError; + + /** PSIHBFIR[4] + * Interrupt from FSP is being processed + */ + (rPSIHBFIR, bit(4)) ? defaultMaskedError; + + /** PSIHBFIR[5] + * CE from PSILL data + */ + (rPSIHBFIR, bit(5)) ? defaultMaskedError; + + /** PSIHBFIR[6] + * UE from PSILL data + */ + (rPSIHBFIR, bit(6)) ? defaultMaskedError; + + /** PSIHBFIR[7] + * Error bit se + */ + (rPSIHBFIR, bit(7)) ? defaultMaskedError; + + /** PSIHBFIR[8] + * Invalid TType Hit on PHB or FSP bar + */ + (rPSIHBFIR, bit(8)) ? level2_M_self_L_th_1; + + /** PSIHBFIR[9] + * Invalid CResp returned + */ + (rPSIHBFIR, bit(9)) ? level2_M_self_L_th_1; + + /** PSIHBFIR[10] + * PowerBus time out waiting for data grant + */ + (rPSIHBFIR, bit(10)) ? level2_th_1; + + /** PSIHBFIR[11] + * PB parity error in a tag/addr bus + */ + (rPSIHBFIR, bit(11)) ? level2_M_self_L_th_1; + + /** PSIHBFIR[12] + * FSP tried access to trusted space + */ + (rPSIHBFIR, bit(12)) ? level2_th_1; + + /** PSIHBFIR[13] + * Unexpected PB CRESP or DATA + */ + (rPSIHBFIR, bit(13)) ? level2_M_self_L_th_1; + + /** PSIHBFIR[14] + * Intr. reg change witn int. pending + */ + (rPSIHBFIR, bit(14)) ? defaultMaskedError; + + /** PSIHBFIR[15] + * PSI Interrupt address Error + */ + (rPSIHBFIR, bit(15)) ? self_M_level2_L_th_1; + + /** PSIHBFIR[16] + * OCC Interrupt address Error + */ + (rPSIHBFIR, bit(16)) ? self_M_level2_L_th_1; + + /** PSIHBFIR[17] + * FSI Interrupt address Error + */ + (rPSIHBFIR, bit(17)) ? self_M_level2_L_th_1; + + /** PSIHBFIR[18] + * LPC Interrupt address Error + */ + (rPSIHBFIR, bit(18)) ? self_M_level2_L_th_1; + + /** PSIHBFIR[19] + * LOCAL ERROR Interrupt address Error + */ + (rPSIHBFIR, bit(19)) ? self_M_level2_L_th_1; + + /** PSIHBFIR[20] + * HOST ERROR Interrupt address Error + */ + (rPSIHBFIR, bit(20)) ? self_M_level2_L_th_1; + + /** PSIHBFIR[21] + * PSI global error bit 0 + */ + (rPSIHBFIR, bit(21)) ? defaultMaskedError; + + /** PSIHBFIR[22] + * PSI global error bit 1 + */ + (rPSIHBFIR, bit(22)) ? defaultMaskedError; + + /** PSIHBFIR[23] + * Upstream error + */ + (rPSIHBFIR, bit(23)) ? level2_M_self_L_th_32perDay; + + /** PSIHBFIR[24:26] + * spare + */ + (rPSIHBFIR, bit(24|25|26)) ? defaultMaskedError; + + /** PSIHBFIR[27] + * scom error + */ + (rPSIHBFIR, bit(27)) ? defaultMaskedError; + + /** PSIHBFIR[28] + * fir parity Error + */ + (rPSIHBFIR, bit(28)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip ENHCAFIR +################################################################################ + +rule rENHCAFIR +{ + CHECK_STOP: + ENHCAFIR & ~ENHCAFIR_MASK & ~ENHCAFIR_ACT0 & ~ENHCAFIR_ACT1; + RECOVERABLE: + ENHCAFIR & ~ENHCAFIR_MASK & ~ENHCAFIR_ACT0 & ENHCAFIR_ACT1; +}; + +group gENHCAFIR + filter singlebit, + cs_root_cause +{ + /** ENHCAFIR[0] + * PB0 data UE + */ + (rENHCAFIR, bit(0)) ? defaultMaskedError; + + /** ENHCAFIR[1] + * PB0 data SUE + */ + (rENHCAFIR, bit(1)) ? defaultMaskedError; + + /** ENHCAFIR[2] + * PB0 data ue + */ + (rENHCAFIR, bit(2)) ? defaultMaskedError; + + /** ENHCAFIR[3] + * spare + */ + (rENHCAFIR, bit(3)) ? defaultMaskedError; + + /** ENHCAFIR[4] + * Castout Drop Counter Full + */ + (rENHCAFIR, bit(4)) ? defaultMaskedError; + + /** ENHCAFIR[5] + * Data Hang Detect + */ + (rENHCAFIR, bit(5)) ? defaultMaskedError; + + /** ENHCAFIR[6] + * Unexpected data or cresp + */ + (rENHCAFIR, bit(6)) ? defaultMaskedError; + + /** ENHCAFIR[7] + * Internal Error + */ + (rENHCAFIR, bit(7)) ? defaultMaskedError; + + /** ENHCAFIR[8] + * ADU checkstop error from power bus data + */ + (rENHCAFIR, bit(8)) ? defaultMaskedError; + + /** ENHCAFIR[9] + * ADU checkstop error from alter display + */ + (rENHCAFIR, bit(9)) ? defaultMaskedError; + + /** ENHCAFIR[10] + * ADU checkstop error from xsco m + */ + (rENHCAFIR, bit(10)) ? defaultMaskedError; + + /** ENHCAFIR[11] + * ADU checkstop from power bus cmd + */ + (rENHCAFIR, bit(11)) ? defaultMaskedError; + + /** ENHCAFIR[12] + * ADU checkstop error from power bus send + */ + (rENHCAFIR, bit(12)) ? defaultMaskedError; + + /** ENHCAFIR[13] + * ADU checkstop from power bus receive + */ + (rENHCAFIR, bit(13)) ? defaultMaskedError; + + /** ENHCAFIR[14] + * ADU recoverable error from pb data + */ + (rENHCAFIR, bit(14)) ? defaultMaskedError; + + /** ENHCAFIR[15] + * ADU recoverable error from alter display + */ + (rENHCAFIR, bit(15)) ? defaultMaskedError; + + /** ENHCAFIR[16] + * ADU recoverable error from xscom + */ + (rENHCAFIR, bit(16)) ? defaultMaskedError; + + /** ENHCAFIR[17] + * ADU recoverable from power bus cmd + */ + (rENHCAFIR, bit(17)) ? defaultMaskedError; + + /** ENHCAFIR[18] + * ADU recoverable error from pb send + */ + (rENHCAFIR, bit(18)) ? defaultMaskedError; + + /** ENHCAFIR[19] + * ADU recoverable error from pb receive + */ + (rENHCAFIR, bit(19)) ? defaultMaskedError; + + /** ENHCAFIR[20] + * NHTM scom error + */ + (rENHCAFIR, bit(20)) ? defaultMaskedError; + + /** ENHCAFIR[21] + * spare + */ + (rENHCAFIR, bit(21)) ? defaultMaskedError; + + /** ENHCAFIR[22] + * scom error + */ + (rENHCAFIR, bit(22)) ? defaultMaskedError; + + /** ENHCAFIR[23] + * scom error + */ + (rENHCAFIR, bit(23)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip PBAMFIR +################################################################################ + +rule rPBAMFIR +{ + CHECK_STOP: + PBAMFIR & ~PBAMFIR_MASK & ~PBAMFIR_ACT0 & ~PBAMFIR_ACT1; + RECOVERABLE: + PBAMFIR & ~PBAMFIR_MASK & ~PBAMFIR_ACT0 & PBAMFIR_ACT1; +}; + +group gPBAMFIR + filter singlebit, + cs_root_cause +{ + /** PBAMFIR[0] + * action0_for_invalid_transfer_size + */ + (rPBAMFIR, bit(0)) ? self_th_1; + + /** PBAMFIR[1] + * action0_for_invalid_command + */ + (rPBAMFIR, bit(1)) ? self_th_1; + + /** PBAMFIR[2] + * action0_for_invalid_address_alignment + */ + (rPBAMFIR, bit(2)) ? self_th_1; + + /** PBAMFIR[3] + * action0_for_OPB_error + */ + (rPBAMFIR, bit(3)) ? defaultMaskedError; + + /** PBAMFIR[4] + * action0_for_OPB_timeout + */ + (rPBAMFIR, bit(4)) ? defaultMaskedError; + + /** PBAMFIR[5] + * action0_for_OPB_master_hang_timeout + */ + (rPBAMFIR, bit(5)) ? self_th_32perDay; + + /** PBAMFIR[6] + * master_cmd_buffer_parity_error + */ + (rPBAMFIR, bit(6)) ? self_th_1; + + /** PBAMFIR[7] + * master_dat_buffer_parity_error + */ + (rPBAMFIR, bit(7)) ? self_th_1; + + /** PBAMFIR[8:9] + * spare + */ + (rPBAMFIR, bit(8|9)) ? defaultMaskedError; + + /** PBAMFIR[10] + * scom error + */ + (rPBAMFIR, bit(10)) ? defaultMaskedError; + + /** PBAMFIR[11] + * scom error + */ + (rPBAMFIR, bit(11)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip NMMUCQFIR +################################################################################ + +rule rNMMUCQFIR +{ + CHECK_STOP: + NMMUCQFIR & ~NMMUCQFIR_MASK & ~NMMUCQFIR_ACT0 & ~NMMUCQFIR_ACT1; + RECOVERABLE: + NMMUCQFIR & ~NMMUCQFIR_MASK & ~NMMUCQFIR_ACT0 & NMMUCQFIR_ACT1; + UNIT_CS: + NMMUCQFIR & ~NMMUCQFIR_MASK & NMMUCQFIR_ACT0 & NMMUCQFIR_ACT1; +}; + +group gNMMUCQFIR + filter singlebit, + cs_root_cause +{ + /** NMMUCQFIR[0] + * PBI_PE_FIR: PBI internal parity error + */ + (rNMMUCQFIR, bit(0)) ? self_th_1; + + /** NMMUCQFIR[1] + * PowerBus command hang error + */ + (rNMMUCQFIR, bit(1)) ? defaultMaskedError; + + /** NMMUCQFIR[2] + * PowerBus read address error + */ + (rNMMUCQFIR, bit(2)) ? self_M_level2_L_th_1; + + /** NMMUCQFIR[3] + * PowerBus write address error + */ + (rNMMUCQFIR, bit(3)) ? self_M_level2_L_th_1; + + /** NMMUCQFIR[4] + * PowerBus miscellaneous error + */ + (rNMMUCQFIR, bit(4)) ? self_th_1; + + /** NMMUCQFIR[5] + * spare + */ + (rNMMUCQFIR, bit(5)) ? defaultMaskedError; + + /** NMMUCQFIR[6] + * PowerBus Xlate UE error + */ + (rNMMUCQFIR, bit(6)) ? self_th_1; + + /** NMMUCQFIR[7] + * PowerBus Xlate SUE error + */ + (rNMMUCQFIR, bit(7)) ? self_th_1_SUE; + + /** NMMUCQFIR[8] + * PowerBus CE error + */ + (rNMMUCQFIR, bit(8)) ? self_th_32perDay; + + /** NMMUCQFIR[9] + * PowerBus UE error + */ + (rNMMUCQFIR, bit(9)) ? self_th_1; + + /** NMMUCQFIR[10] + * PowerBus SUE error + */ + (rNMMUCQFIR, bit(10)) ? defaultMaskedError; + + /** NMMUCQFIR[11] + * Inbound LCO_ARRAY CE error + */ + (rNMMUCQFIR, bit(11)) ? self_th_32perDay; + + /** NMMUCQFIR[12] + * Inbound LCO_ARRAY UE error + */ + (rNMMUCQFIR, bit(12)) ? self_th_1; + + /** NMMUCQFIR[13] + * Inbound LCO_ARRAY SUE error + */ + (rNMMUCQFIR, bit(13)) ? defaultMaskedError; + + /** NMMUCQFIR[14] + * Inbound array CE error + */ + (rNMMUCQFIR, bit(14)) ? self_th_32perDay; + + /** NMMUCQFIR[15] + * Inbound array UE error + */ + (rNMMUCQFIR, bit(15)) ? self_th_1; + + /** NMMUCQFIR[16] + * internal state error + */ + (rNMMUCQFIR, bit(16)) ? self_th_1; + + /** NMMUCQFIR[17] + * ACK_DEAD cresp received by read command + */ + (rNMMUCQFIR, bit(17)) ? defaultMaskedError; + + /** NMMUCQFIR[18] + * ACK_DEAD cresp received by write command + */ + (rNMMUCQFIR, bit(18)) ? defaultMaskedError; + + /** NMMUCQFIR[19] + * Link check aborted while waiting on data + */ + (rNMMUCQFIR, bit(19)) ? defaultMaskedError; + + /** NMMUCQFIR[20] + * scom error + */ + (rNMMUCQFIR, bit(20)) ? defaultMaskedError; + + /** NMMUCQFIR[21] + * scom error + */ + (rNMMUCQFIR, bit(21)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip NMMUFIR +################################################################################ + +rule rNMMUFIR +{ + CHECK_STOP: + NMMUFIR & ~NMMUFIR_MASK & ~NMMUFIR_ACT0 & ~NMMUFIR_ACT1; + RECOVERABLE: + NMMUFIR & ~NMMUFIR_MASK & ~NMMUFIR_ACT0 & NMMUFIR_ACT1; + UNIT_CS: + NMMUFIR & ~NMMUFIR_MASK & NMMUFIR_ACT0 & NMMUFIR_ACT1; +}; + +group gNMMUFIR + filter singlebit, + cs_root_cause +{ + /** NMMUFIR[0] + * Fabric DIn xlat array CE error detected. + */ + (rNMMUFIR, bit(0)) ? self_th_32perDay; + + /** NMMUFIR[1] + * Fabric DIn xlat array UE error detected. + */ + (rNMMUFIR, bit(1)) ? self_th_1; + + /** NMMUFIR[2] + * Fabric DIn xlat array SUE error + */ + (rNMMUFIR, bit(2)) ? self_th_1_SUE; + + /** NMMUFIR[3] + * Fabric mst rd array CE error detected. + */ + (rNMMUFIR, bit(3)) ? self_th_32perDay; + + /** NMMUFIR[4] + * Fabric mst rd array UE error detected. + */ + (rNMMUFIR, bit(4)) ? self_th_1; + + /** NMMUFIR[5] + * Fabric mst rd array SUE error detected. + */ + (rNMMUFIR, bit(5)) ? defaultMaskedError; + + /** NMMUFIR[6] + * Fabric xlat protocol error detected. + */ + (rNMMUFIR, bit(6)) ? self_th_1; + + /** NMMUFIR[7] + * Fabric xlat op timeout detected. + */ + (rNMMUFIR, bit(7)) ? defaultMaskedError; + + /** NMMUFIR[8] + * SLB directory parity error detected. + */ + (rNMMUFIR, bit(8)) ? self_th_1; + + /** NMMUFIR[9] + * SLB cache parity error detected. + */ + (rNMMUFIR, bit(9)) ? self_th_1; + + /** NMMUFIR[10] + * SLB lru parity error detected. + */ + (rNMMUFIR, bit(10)) ? self_th_1; + + /** NMMUFIR[11] + * SLB multi-hit error detected. + */ + (rNMMUFIR, bit(11)) ? threshold_and_mask_self; + + /** NMMUFIR[12] + * TLB directory parity error detected. + */ + (rNMMUFIR, bit(12)) ? self_th_1; + + /** NMMUFIR[13] + * TLB cache parity error detected. + */ + (rNMMUFIR, bit(13)) ? self_th_1; + + /** NMMUFIR[14] + * TLB lru parity error detected. + */ + (rNMMUFIR, bit(14)) ? self_th_1; + + /** NMMUFIR[15] + * TLB multi-hit error detected. + */ + (rNMMUFIR, bit(15)) ? threshold_and_mask_self; + + /** NMMUFIR[16] + * Segment fault detected . + */ + (rNMMUFIR, bit(16)) ? defaultMaskedError; + + /** NMMUFIR[17] + * Page fault detected, no matching pte. + */ + (rNMMUFIR, bit(17)) ? defaultMaskedError; + + /** NMMUFIR[18] + * Page fault, basic prot chk fail. + */ + (rNMMUFIR, bit(18)) ? defaultMaskedError; + + /** NMMUFIR[19] + * Page fault detected, virt prot chk fail. + */ + (rNMMUFIR, bit(19)) ? defaultMaskedError; + + /** NMMUFIR[20] + * Page fault detected,seid mismatch . + */ + (rNMMUFIR, bit(20)) ? defaultMaskedError; + + /** NMMUFIR[21] + * Address error cresp detected by twsm + */ + (rNMMUFIR, bit(21)) ? self_M_level2_L_th_1; + + /** NMMUFIR[22] + * PTE update fail due to armwf mismatch. + */ + (rNMMUFIR, bit(22)) ? defaultMaskedError; + + /** NMMUFIR[23] + * Address error cresp detected by twsm + */ + (rNMMUFIR, bit(23)) ? self_M_level2_L_th_1; + + /** NMMUFIR[24] + * Unsupported radix cfg for guest-side . + */ + (rNMMUFIR, bit(24)) ? defaultMaskedError; + + /** NMMUFIR[25] + * Unsupported radix cfg for host-side . + */ + (rNMMUFIR, bit(25)) ? defaultMaskedError; + + /** NMMUFIR[26] + * Invalid wimg setting detected . + */ + (rNMMUFIR, bit(26)) ? defaultMaskedError; + + /** NMMUFIR[27] + * Invalid radix quad access detected . + */ + (rNMMUFIR, bit(27)) ? defaultMaskedError; + + /** NMMUFIR[28] + * Unexpected access to foreign addr space + */ + (rNMMUFIR, bit(28)) ? defaultMaskedError; + + /** NMMUFIR[29] + * Prefetch abort/fail detected . + */ + (rNMMUFIR, bit(29)) ? defaultMaskedError; + + /** NMMUFIR[30] + * Context cache array parity er + */ + (rNMMUFIR, bit(30)) ? self_th_1; + + /** NMMUFIR[31] + * Radix pwc array parity error detected . + */ + (rNMMUFIR, bit(31)) ? self_th_1; + + /** NMMUFIR[32] + * Tablewalk sm control error detected . + */ + (rNMMUFIR, bit(32)) ? self_th_1; + + /** NMMUFIR[33] + * Castout sm control error detected . + */ + (rNMMUFIR, bit(33)) ? self_th_1; + + /** NMMUFIR[34] + * Check-in sm control error detected . + */ + (rNMMUFIR, bit(34)) ? self_th_1; + + /** NMMUFIR[35] + * Invalidate sm control error detected . + */ + (rNMMUFIR, bit(35)) ? self_th_1; + + /** NMMUFIR[36] + * Tablewalk sm timeout error detected . + */ + (rNMMUFIR, bit(36)) ? defaultMaskedError; + + /** NMMUFIR[37] + * Castout sm timeout error detected . + */ + (rNMMUFIR, bit(37)) ? defaultMaskedError; + + /** NMMUFIR[38] + * Check-in sm timeout error detected . + */ + (rNMMUFIR, bit(38)) ? defaultMaskedError; + + /** NMMUFIR[39] + * Invalidate sm timeout error detected . + */ + (rNMMUFIR, bit(39)) ? defaultMaskedError; + + /** NMMUFIR[40] + * NX local checkstop error detected . + */ + (rNMMUFIR, bit(40)) ? defaultMaskedError; + + /** NMMUFIR[41] + * CP0 local checkstop error detected . + */ + (rNMMUFIR, bit(41)) ? defaultMaskedError; + + /** NMMUFIR[42] + * CP1 local checkstop error detected . + */ + (rNMMUFIR, bit(42)) ? defaultMaskedError; + + /** NMMUFIR[43] + * NPU local checkstop error detected . + */ + (rNMMUFIR, bit(43)) ? defaultMaskedError; + + /** NMMUFIR[44] + * FBC local checkstop error detected . + */ + (rNMMUFIR, bit(44)) ? defaultMaskedError; + + /** NMMUFIR[45] + * Snoop invalidate filter overflow . + */ + (rNMMUFIR, bit(45)) ? defaultMaskedError; + + /** NMMUFIR[46] + * scom error + */ + (rNMMUFIR, bit(46)) ? defaultMaskedError; + + /** NMMUFIR[47] + * scom error + */ + (rNMMUFIR, bit(47)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip INTCQFIR +################################################################################ + +rule rINTCQFIR +{ + CHECK_STOP: + INTCQFIR & ~INTCQFIR_MASK & ~INTCQFIR_ACT0 & ~INTCQFIR_ACT1; + RECOVERABLE: + INTCQFIR & ~INTCQFIR_MASK & ~INTCQFIR_ACT0 & INTCQFIR_ACT1; +}; + +group gINTCQFIR + filter singlebit, + cs_root_cause +{ + /** INTCQFIR[0] + * INT_CQ_FIR_PI_ECC_CE: + */ + (rINTCQFIR, bit(0)) ? self_th_32perDay; + + /** INTCQFIR[1] + * INT_CQ_FIR_PI_ECC_UE: + */ + (rINTCQFIR, bit(1)) ? self_th_1; + + /** INTCQFIR[2] + * INT_CQ_FIR_PI_ECC_SUE: + */ + (rINTCQFIR, bit(2)) ? self_th_1_SUE; + + /** INTCQFIR[3] + * INT_CQ_FIR_ST_ECC_CE: + */ + (rINTCQFIR, bit(3)) ? self_th_32perDay; + + /** INTCQFIR[4] + * INT_CQ_FIR_ST_ECC_UE: + */ + (rINTCQFIR, bit(4)) ? self_th_1; + + /** INTCQFIR[5] + * INT_CQ_FIR_LD_ECC_CE: + */ + (rINTCQFIR, bit(5)) ? self_th_32perDay; + + /** INTCQFIR[6] + * INT_CQ_FIR_LD_ECC_UE: + */ + (rINTCQFIR, bit(6)) ? self_th_1; + + /** INTCQFIR[7] + * INT_CQ_FIR_CL_ECC_CE: + */ + (rINTCQFIR, bit(7)) ? self_th_32perDay; + + /** INTCQFIR[8] + * INT_CQ_FIR_CL_ECC_UE: + */ + (rINTCQFIR, bit(8)) ? self_th_1; + + /** INTCQFIR[9] + * INT_CQ_FIR_WR_ECC_CE: + */ + (rINTCQFIR, bit(9)) ? self_th_32perDay; + + /** INTCQFIR[10] + * INT_CQ_FIR_WR_ECC_UE: + */ + (rINTCQFIR, bit(10)) ? self_th_1; + + /** INTCQFIR[11] + * INT_CQ_FIR_RD_ECC_CE: + */ + (rINTCQFIR, bit(11)) ? self_th_32perDay; + + /** INTCQFIR[12] + * INT_CQ_FIR_RD_ECC_UE: + */ + (rINTCQFIR, bit(12)) ? self_th_1; + + /** INTCQFIR[13] + * INT_CQ_FIR_AI_ECC_CE: + */ + (rINTCQFIR, bit(13)) ? self_th_32perDay; + + /** INTCQFIR[14] + * INT_CQ_FIR_AI_ECC_UE: + */ + (rINTCQFIR, bit(14)) ? self_th_1; + + /** INTCQFIR[15] + * INT_CQ_FIR_AIB_IN_CMD_CTL_PERR: + */ + (rINTCQFIR, bit(15)) ? self_th_1; + + /** INTCQFIR[16] + * INT_CQ_FIR_AIB_IN_CMD_PERR: + */ + (rINTCQFIR, bit(16)) ? self_th_1; + + /** INTCQFIR[17] + * INT_CQ_FIR_AIB_IN_DAT_CTL_PERR: + */ + (rINTCQFIR, bit(17)) ? self_th_1; + + /** INTCQFIR[18] + * INT_CQ_FIR_PB_PARITY_ERROR: + */ + (rINTCQFIR, bit(18)) ? self_th_1; + + /** INTCQFIR[19] + * INT_CQ_FIR_PB_RCMDX_CI_ERR1: + */ + (rINTCQFIR, bit(19)) ? self_th_1; + + /** INTCQFIR[20] + * INT_CQ_FIR_PB_RCMDX_CI_ERR2: + */ + (rINTCQFIR, bit(20)) ? self_th_1; + + /** INTCQFIR[21] + * INT_CQ_FIR_PB_RCMDX_CI_ERR3: + */ + (rINTCQFIR, bit(21)) ? self_th_1; + + /** INTCQFIR[22] + * INT_CQ_FIR_RCVD_POISONED_CIST_DATA: + */ + (rINTCQFIR, bit(22)) ? self_th_32perDay; + + /** INTCQFIR[23] + * INT_CQ_FIR_MRT_ERR_NOT_VALID: + */ + (rINTCQFIR, bit(23)) ? self_th_1; + + /** INTCQFIR[24] + * INT_CQ_FIR_MRT_ERR_PSIZE: + */ + (rINTCQFIR, bit(24)) ? self_th_1; + + /** INTCQFIR[25] + * INT_CQ_FIR_SCOM_S_ERR: + */ + (rINTCQFIR, bit(25)) ? defaultMaskedError; + + /** INTCQFIR[26] + * INT_CQ_FIR_TCTXT_PRESP_ERROR: + */ + (rINTCQFIR, bit(26)) ? self_th_1; + + /** INTCQFIR[27] + * INT_CQ_FIR_WRQ_OP_HANG: + */ + (rINTCQFIR, bit(27)) ? defaultMaskedError; + + /** INTCQFIR[28] + * INT_CQ_FIR_RDQ_OP_HANG: + */ + (rINTCQFIR, bit(28)) ? defaultMaskedError; + + /** INTCQFIR[29] + * INT_CQ_FIR_INTQ_OP_HANG: + */ + (rINTCQFIR, bit(29)) ? defaultMaskedError; + + /** INTCQFIR[30] + * INT_CQ_FIR_RDQ_DATA_HANG: + */ + (rINTCQFIR, bit(30)) ? self_th_1; + + /** INTCQFIR[31] + * INT_CQ_FIR_STQ_DATA_HANG: + */ + (rINTCQFIR, bit(31)) ? self_th_1; + + /** INTCQFIR[32] + * INT_CQ_FIR_LDQ_DATA_HANG: + */ + (rINTCQFIR, bit(32)) ? self_th_1; + + /** INTCQFIR[33] + * INT_CQ_FIR_WRQ_BAD_CRESP: + */ + (rINTCQFIR, bit(33)) ? self_M_level2_L_th_1; + + /** INTCQFIR[34] + * INT_CQ_FIR_RDQ_BAD_CRESP: + */ + (rINTCQFIR, bit(34)) ? self_M_level2_L_th_1; + + /** INTCQFIR[35] + * INT_CQ_FIR_INTQ_BAD_CRESP: + */ + (rINTCQFIR, bit(35)) ? self_M_level2_L_th_1; + + /** INTCQFIR[36] + * INT_CQ_FIR_BAD_128K_VP_OP: + */ + (rINTCQFIR, bit(36)) ? self_th_1; + + /** INTCQFIR[37] + * INT_CQ_FIR_RDQ_ABORT_OP: + */ + (rINTCQFIR, bit(37)) ? defaultMaskedError; + + /** INTCQFIR[38] + * INT_CQ_FIR_PC_CRD_PERR: + */ + (rINTCQFIR, bit(38)) ? self_th_1; + + /** INTCQFIR[39] + * INT_CQ_FIR_PC_CRD_AVAIL_PERR: + */ + (rINTCQFIR, bit(39)) ? self_th_1; + + /** INTCQFIR[40] + * INT_CQ_FIR_VC_CRD_PERR: + */ + (rINTCQFIR, bit(40)) ? self_th_1; + + /** INTCQFIR[41] + * INT_CQ_FIR_VC_CRD_AVAIL_PERR: + */ + (rINTCQFIR, bit(41)) ? self_th_1; + + /** INTCQFIR[42] + * INT_CQ_FIR_CMD_QX_SEVERE_ERR: + */ + (rINTCQFIR, bit(42)) ? self_th_1; + + /** INTCQFIR[43] + * INT_CQ_FIR_RDQ_ABORT_TRM: + */ + (rINTCQFIR, bit(43)) ? self_th_32perDay; + + /** INTCQFIR[44] + * INT_CQ_FIR_UNSOLICITED_CRESP: + */ + (rINTCQFIR, bit(44)) ? level2_M_self_L_th_1; + + /** INTCQFIR[45] + * INT_CQ_FIR_UNSOLICITED_PBDATA: + */ + (rINTCQFIR, bit(45)) ? self_th_1; + + /** INTCQFIR[46] + * INT_CQ_FIR_FIR_PARITY_ERR: + */ + (rINTCQFIR, bit(46)) ? self_th_1; + + /** INTCQFIR[47] + * INT_CQ_FIR_PGM_DBG_ACCESS: + */ + (rINTCQFIR, bit(47)) ? threshold_and_mask_self; + + /** INTCQFIR[48] + * spare + */ + (rINTCQFIR, bit(48)) ? defaultMaskedError; + + /** INTCQFIR[49:51] + * INT_CQ_FIR_PC_FATAL_ERROR_0_2: + */ + (rINTCQFIR, bit(49|50|51)) ? self_th_1; + + /** INTCQFIR[52:54] + * INT_CQ_FIR_PC_RECOV_ERROR_0_2: + */ + (rINTCQFIR, bit(52|53|54)) ? analyzeIntCqFirPcRecovError; + + /** INTCQFIR[55:57] + * INT_CQ_FIR_PC_INFO_ERROR_0_2: + */ + (rINTCQFIR, bit(55|56|57)) ? defaultMaskedError; + + /** INTCQFIR[58:59] + * INT_CQ_FIR_VC_FATAL_ERROR_0_1: + */ + (rINTCQFIR, bit(58|59)) ? self_th_1; + + /** INTCQFIR[60:61] + * INT_CQ_FIR_VC_RECOV_ERROR_0_1: + */ + (rINTCQFIR, bit(60|61)) ? level2_M_self_L_th_1; + + /** INTCQFIR[62:63] + * INT_CQ_FIR_VC_INFO_ERROR_0_1: + */ + (rINTCQFIR, bit(62|63)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip PBIOEFIR +################################################################################ + +rule rPBIOEFIR +{ + CHECK_STOP: + PBIOEFIR & ~PBIOEFIR_MASK & ~PBIOEFIR_ACT0 & ~PBIOEFIR_ACT1; + RECOVERABLE: + PBIOEFIR & ~PBIOEFIR_MASK & ~PBIOEFIR_ACT0 & PBIOEFIR_ACT1; +}; + +group gPBIOEFIR + filter singlebit, + cs_root_cause(8,11,14) +{ + /** PBIOEFIR[0] + * fmr00 trained + */ + (rPBIOEFIR, bit(0)) ? defaultMaskedError; + + /** PBIOEFIR[1] + * fmr01 trained + */ + (rPBIOEFIR, bit(1)) ? defaultMaskedError; + + /** PBIOEFIR[2] + * fmr02 trained + */ + (rPBIOEFIR, bit(2)) ? defaultMaskedError; + + /** PBIOEFIR[3] + * fmr03 trained + */ + (rPBIOEFIR, bit(3)) ? defaultMaskedError; + + /** PBIOEFIR[4] + * fmr04 trained + */ + (rPBIOEFIR, bit(4)) ? defaultMaskedError; + + /** PBIOEFIR[5] + * fmr05 trained + */ + (rPBIOEFIR, bit(5)) ? defaultMaskedError; + + /** PBIOEFIR[6:7] + * spare + */ + (rPBIOEFIR, bit(6|7)) ? defaultMaskedError; + + /** PBIOEFIR[8] + * dob01 ue + */ + (rPBIOEFIR, bit(8)) ? self_th_1_UERE; + + /** PBIOEFIR[9] + * d0b01 ce + */ + (rPBIOEFIR, bit(9)) ? self_th_32perDay; + + /** PBIOEFIR[10] + * dob01 sue + */ + (rPBIOEFIR, bit(10)) ? defaultMaskedError; + + /** PBIOEFIR[11] + * dob23 ue + */ + (rPBIOEFIR, bit(11)) ? self_th_1_UERE; + + /** PBIOEFIR[12] + * dob23 ce + */ + (rPBIOEFIR, bit(12)) ? self_th_32perDay; + + /** PBIOEFIR[13] + * dob23 sue + */ + (rPBIOEFIR, bit(13)) ? defaultMaskedError; + + /** PBIOEFIR[14] + * dob45 ue + */ + (rPBIOEFIR, bit(14)) ? self_th_1_UERE; + + /** PBIOEFIR[15] + * dob45 ce + */ + (rPBIOEFIR, bit(15)) ? self_th_32perDay; + + /** PBIOEFIR[16] + * dob45 sue + */ + (rPBIOEFIR, bit(16)) ? defaultMaskedError; + + /** PBIOEFIR[17] + * spare + */ + (rPBIOEFIR, bit(17)) ? defaultMaskedError; + + /** PBIOEFIR[18] + * spare + */ + (rPBIOEFIR, bit(18)) ? defaultMaskedError; + + /** PBIOEFIR[19] + * spare + */ + (rPBIOEFIR, bit(19)) ? defaultMaskedError; + + /** PBIOEFIR[20] + * X0 even link framer or outbnd switch err + */ + (rPBIOEFIR, bit(20)) ? self_th_1; + + /** PBIOEFIR[21] + * X0 odd internal framer err + */ + (rPBIOEFIR, bit(21)) ? self_th_1; + + /** PBIOEFIR[22] + * X1 even link framer or outbnd switch err + */ + (rPBIOEFIR, bit(22)) ? self_th_1; + + /** PBIOEFIR[23] + * X1 odd internal framer err + */ + (rPBIOEFIR, bit(23)) ? self_th_1; + + /** PBIOEFIR[24] + * X2 even link framer or outbnd switch err + */ + (rPBIOEFIR, bit(24)) ? self_th_1; + + /** PBIOEFIR[25] + * X2 odd internal framer err + */ + (rPBIOEFIR, bit(25)) ? self_th_1; + + /** PBIOEFIR[26:27] + * spare + */ + (rPBIOEFIR, bit(26|27)) ? defaultMaskedError; + + /** PBIOEFIR[28] + * parser00 attn or X0evn link down + */ + (rPBIOEFIR, bit(28)) ? calloutBusInterface_xbus0_th_1; + + /** PBIOEFIR[29] + * parser01 attn or X0odd link down + */ + (rPBIOEFIR, bit(29)) ? calloutBusInterface_xbus0_th_1; + + /** PBIOEFIR[30] + * parser02 attn or X1evn link down + */ + (rPBIOEFIR, bit(30)) ? calloutBusInterface_xbus1_th_1; + + /** PBIOEFIR[31] + * parser03 attn or X1odd link down + */ + (rPBIOEFIR, bit(31)) ? calloutBusInterface_xbus1_th_1; + + /** PBIOEFIR[32] + * parser04 attn or X2evn link down + */ + (rPBIOEFIR, bit(32)) ? calloutBusInterface_xbus2_th_1; + + /** PBIOEFIR[33] + * parser05 attn or X2odd link down + */ + (rPBIOEFIR, bit(33)) ? calloutBusInterface_xbus2_th_1; + + /** PBIOEFIR[34:35] + * spare + */ + (rPBIOEFIR, bit(34|35)) ? defaultMaskedError; + + /** PBIOEFIR[36] + * mb00 spattn + */ + (rPBIOEFIR, bit(36)) ? defaultMaskedError; + + /** PBIOEFIR[37] + * mb01 spattn + */ + (rPBIOEFIR, bit(37)) ? defaultMaskedError; + + /** PBIOEFIR[38] + * mb10 spattn + */ + (rPBIOEFIR, bit(38)) ? defaultMaskedError; + + /** PBIOEFIR[39] + * mb11 spattn + */ + (rPBIOEFIR, bit(39)) ? defaultMaskedError; + + /** PBIOEFIR[40] + * mb20 spattn + */ + (rPBIOEFIR, bit(40)) ? defaultMaskedError; + + /** PBIOEFIR[41] + * mb21 spattn + */ + (rPBIOEFIR, bit(41)) ? defaultMaskedError; + + /** PBIOEFIR[42] + * mb30 spattn + */ + (rPBIOEFIR, bit(42)) ? defaultMaskedError; + + /** PBIOEFIR[43] + * mb31 spattn + */ + (rPBIOEFIR, bit(43)) ? defaultMaskedError; + + /** PBIOEFIR[44] + * mb40 spattn + */ + (rPBIOEFIR, bit(44)) ? defaultMaskedError; + + /** PBIOEFIR[45] + * mb41 spattn + */ + (rPBIOEFIR, bit(45)) ? defaultMaskedError; + + /** PBIOEFIR[46] + * mb50 spattn + */ + (rPBIOEFIR, bit(46)) ? defaultMaskedError; + + /** PBIOEFIR[47] + * mb51 spattn + */ + (rPBIOEFIR, bit(47)) ? defaultMaskedError; + + /** PBIOEFIR[48:51] + * spare + */ + (rPBIOEFIR, bit(48|49|50|51)) ? defaultMaskedError; + + /** PBIOEFIR[52] + * data outbnd switch int. err-links 01 + */ + (rPBIOEFIR, bit(52)) ? calloutBusInterface_xbus0_th_1; + + /** PBIOEFIR[53] + * data outbnd switch int. err-links 23 + */ + (rPBIOEFIR, bit(53)) ? calloutBusInterface_xbus1_th_1; + + /** PBIOEFIR[54] + * data outbnd switch int. err-links 45 + */ + (rPBIOEFIR, bit(54)) ? calloutBusInterface_xbus2_th_1; + + /** PBIOEFIR[55] + * spare + */ + (rPBIOEFIR, bit(55)) ? defaultMaskedError; + + /** PBIOEFIR[56] + * data inbnd switch int. err-links 01 + */ + (rPBIOEFIR, bit(56)) ? calloutBusInterface_xbus0_th_1; + + /** PBIOEFIR[57] + * data inbnd switch int. err-links 23 + */ + (rPBIOEFIR, bit(57)) ? calloutBusInterface_xbus1_th_1; + + /** PBIOEFIR[58] + * data inbnd switch int. err-links 45 + */ + (rPBIOEFIR, bit(58)) ? calloutBusInterface_xbus2_th_1; + + /** PBIOEFIR[59:61] + * spare + */ + (rPBIOEFIR, bit(59|60|61)) ? defaultMaskedError; + + /** PBIOEFIR[62] + * scom error + */ + (rPBIOEFIR, bit(62)) ? defaultMaskedError; + + /** PBIOEFIR[63] + * scom error + */ + (rPBIOEFIR, bit(63)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip PBIOOFIR +################################################################################ + +rule rPBIOOFIR +{ + CHECK_STOP: + PBIOOFIR & ~PBIOOFIR_MASK & ~PBIOOFIR_ACT0 & ~PBIOOFIR_ACT1; + RECOVERABLE: + PBIOOFIR & ~PBIOOFIR_MASK & ~PBIOOFIR_ACT0 & PBIOOFIR_ACT1; +}; + +group gPBIOOFIR + filter singlebit, + cs_root_cause(8,11,14,17) +{ + /** PBIOOFIR[0] + * fmr00 trained + */ + (rPBIOOFIR, bit(0)) ? defaultMaskedError; + + /** PBIOOFIR[1] + * fmr01 trained + */ + (rPBIOOFIR, bit(1)) ? defaultMaskedError; + + /** PBIOOFIR[2] + * fmr02 trained + */ + (rPBIOOFIR, bit(2)) ? defaultMaskedError; + + /** PBIOOFIR[3] + * fmr03 trained + */ + (rPBIOOFIR, bit(3)) ? defaultMaskedError; + + /** PBIOOFIR[4] + * fmr04 trained + */ + (rPBIOOFIR, bit(4)) ? defaultMaskedError; + + /** PBIOOFIR[5] + * fmr05 trained + */ + (rPBIOOFIR, bit(5)) ? defaultMaskedError; + + /** PBIOOFIR[6] + * fmr06 trained + */ + (rPBIOOFIR, bit(6)) ? defaultMaskedError; + + /** PBIOOFIR[7] + * fmr07 trained + */ + (rPBIOOFIR, bit(7)) ? defaultMaskedError; + + /** PBIOOFIR[8] + * dob01 ue + */ + (rPBIOOFIR, bit(8)) ? self_th_1_UERE; + + /** PBIOOFIR[9] + * dob01 ce + */ + (rPBIOOFIR, bit(9)) ? self_th_32perDay; + + /** PBIOOFIR[10] + * dob01 sue + */ + (rPBIOOFIR, bit(10)) ? defaultMaskedError; + + /** PBIOOFIR[11] + * dob23 ue + */ + (rPBIOOFIR, bit(11)) ? self_th_1_UERE; + + /** PBIOOFIR[12] + * dob23 ce + */ + (rPBIOOFIR, bit(12)) ? self_th_32perDay; + + /** PBIOOFIR[13] + * dob23 sue + */ + (rPBIOOFIR, bit(13)) ? defaultMaskedError; + + /** PBIOOFIR[14] + * dob45 ue + */ + (rPBIOOFIR, bit(14)) ? self_th_1_UERE; + + /** PBIOOFIR[15] + * dob45 ce + */ + (rPBIOOFIR, bit(15)) ? self_th_32perDay; + + /** PBIOOFIR[16] + * dob45 sue + */ + (rPBIOOFIR, bit(16)) ? defaultMaskedError; + + /** PBIOOFIR[17] + * dob67 ue + */ + (rPBIOOFIR, bit(17)) ? self_th_1_UERE; + + /** PBIOOFIR[18] + * dob67 ce + */ + (rPBIOOFIR, bit(18)) ? self_th_32perDay; + + /** PBIOOFIR[19] + * dob67 sue + */ + (rPBIOOFIR, bit(19)) ? defaultMaskedError; + + /** PBIOOFIR[20] + * A0 even link framer error + */ + (rPBIOOFIR, bit(20)) ? self_th_1; + + /** PBIOOFIR[21] + * A0 odd framer error + */ + (rPBIOOFIR, bit(21)) ? self_th_1; + + /** PBIOOFIR[22] + * A1 even link framer error + */ + (rPBIOOFIR, bit(22)) ? self_th_1; + + /** PBIOOFIR[23] + * A1 odd link framer error + */ + (rPBIOOFIR, bit(23)) ? self_th_1; + + /** PBIOOFIR[24] + * A2 even link framer error + */ + (rPBIOOFIR, bit(24)) ? self_th_1; + + /** PBIOOFIR[25] + * A2 odd link framer error + */ + (rPBIOOFIR, bit(25)) ? self_th_1; + + /** PBIOOFIR[26] + * A3 even link framer error + */ + (rPBIOOFIR, bit(26)) ? self_th_1; + + /** PBIOOFIR[27] + * A3 odd link framer error + */ + (rPBIOOFIR, bit(27)) ? self_th_1; + + /** PBIOOFIR[28] + * parser00 attn + */ + (rPBIOOFIR, bit(28)) ? obus0SmpFailure_L0; + + /** PBIOOFIR[29] + * parser01 attn + */ + (rPBIOOFIR, bit(29)) ? obus0SmpFailure_L1; + + /** PBIOOFIR[30] + * parser02 attn + */ + (rPBIOOFIR, bit(30)) ? obus1SmpFailure_L0; + + /** PBIOOFIR[31] + * parser03 attn + */ + (rPBIOOFIR, bit(31)) ? obus1SmpFailure_L1; + + /** PBIOOFIR[32] + * parser04 attn + */ + (rPBIOOFIR, bit(32)) ? obus2SmpFailure_L0; + + /** PBIOOFIR[33] + * parser05 attn + */ + (rPBIOOFIR, bit(33)) ? obus2SmpFailure_L1; + + /** PBIOOFIR[34] + * parser06 attn + */ + (rPBIOOFIR, bit(34)) ? obus3SmpFailure_L0; + + /** PBIOOFIR[35] + * parser07 attn + */ + (rPBIOOFIR, bit(35)) ? obus3SmpFailure_L1; + + /** PBIOOFIR[36] + * mailbox 00 special attention + */ + (rPBIOOFIR, bit(36)) ? defaultMaskedError; + + /** PBIOOFIR[37] + * mailbox 01 special attention + */ + (rPBIOOFIR, bit(37)) ? defaultMaskedError; + + /** PBIOOFIR[38] + * mailbox 02 special attention + */ + (rPBIOOFIR, bit(38)) ? defaultMaskedError; + + /** PBIOOFIR[39] + * mailbox 11 special attention + */ + (rPBIOOFIR, bit(39)) ? defaultMaskedError; + + /** PBIOOFIR[40] + * mailbox 20 special attention + */ + (rPBIOOFIR, bit(40)) ? defaultMaskedError; + + /** PBIOOFIR[41] + * mailbox 21 special attention + */ + (rPBIOOFIR, bit(41)) ? defaultMaskedError; + + /** PBIOOFIR[42] + * mailbox 30 special attention + */ + (rPBIOOFIR, bit(42)) ? defaultMaskedError; + + /** PBIOOFIR[43] + * mailbox 31 special attention + */ + (rPBIOOFIR, bit(43)) ? defaultMaskedError; + + /** PBIOOFIR[44] + * mailbox 40 special attention + */ + (rPBIOOFIR, bit(44)) ? defaultMaskedError; + + /** PBIOOFIR[45] + * mailbox 41 special attention + */ + (rPBIOOFIR, bit(45)) ? defaultMaskedError; + + /** PBIOOFIR[46] + * mailbox 50 special attention + */ + (rPBIOOFIR, bit(46)) ? defaultMaskedError; + + /** PBIOOFIR[47] + * mailbox 51 special attention + */ + (rPBIOOFIR, bit(47)) ? defaultMaskedError; + + /** PBIOOFIR[48] + * mailbox 60 special attention + */ + (rPBIOOFIR, bit(48)) ? defaultMaskedError; + + /** PBIOOFIR[49] + * mailbox 61 special attention + */ + (rPBIOOFIR, bit(49)) ? defaultMaskedError; + + /** PBIOOFIR[50] + * mailbox 70 special attention + */ + (rPBIOOFIR, bit(50)) ? defaultMaskedError; + + /** PBIOOFIR[51] + * mailbox 71 special attention + */ + (rPBIOOFIR, bit(51)) ? defaultMaskedError; + + /** PBIOOFIR[52] + * data outbound switch internal-links 01 + */ + (rPBIOOFIR, bit(52)) ? obus0SmpFailure_LALL; + + /** PBIOOFIR[53] + * data outbound switch internal - links 23 + */ + (rPBIOOFIR, bit(53)) ? obus1SmpFailure_LALL; + + /** PBIOOFIR[54] + * data outbound switch internal-links 45 + */ + (rPBIOOFIR, bit(54)) ? obus2SmpFailure_LALL; + + /** PBIOOFIR[55] + * data outbound switch internal-links 67 + */ + (rPBIOOFIR, bit(55)) ? obus3SmpFailure_LALL; + + /** PBIOOFIR[56] + * data inbound switch internal-links 01 + */ + (rPBIOOFIR, bit(56)) ? obus0SmpFailure_LALL; + + /** PBIOOFIR[57] + * data inbound switch internal-links 23 + */ + (rPBIOOFIR, bit(57)) ? obus1SmpFailure_LALL; + + /** PBIOOFIR[58] + * data inbound switch internal-links 45 + */ + (rPBIOOFIR, bit(58)) ? obus2SmpFailure_LALL; + + /** PBIOOFIR[59] + * data inbound switch internal-links 67 + */ + (rPBIOOFIR, bit(59)) ? obus3SmpFailure_LALL; + + /** PBIOOFIR[60:61] + * spare + */ + (rPBIOOFIR, bit(60|61)) ? defaultMaskedError; + + /** PBIOOFIR[62] + * scom error + */ + (rPBIOOFIR, bit(62)) ? defaultMaskedError; + + /** PBIOOFIR[63] + * scom error + */ + (rPBIOOFIR, bit(63)) ? defaultMaskedError; + +}; + +################################################################################ +# XB Chiplet FIR +################################################################################ + +rule rXB_CHIPLET_FIR +{ + CHECK_STOP: + XB_CHIPLET_CS_FIR & ~XB_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (XB_CHIPLET_RE_FIR >> 2) & ~XB_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gXB_CHIPLET_FIR + filter singlebit +{ + /** XB_CHIPLET_FIR[3] + * Attention from XB_LFIR + */ + (rXB_CHIPLET_FIR, bit(3)) ? analyzeXB_LFIR; + + /** XB_CHIPLET_FIR[4] + * Attention from IOELFIR 0 + */ + (rXB_CHIPLET_FIR, bit(4)) ? analyzeConnectedXBUS0; + + /** XB_CHIPLET_FIR[5] + * Attention from IOELFIR 1 + */ + (rXB_CHIPLET_FIR, bit(5)) ? analyzeConnectedXBUS1; + + /** XB_CHIPLET_FIR[6] + * Attention from IOELFIR 2 + */ + (rXB_CHIPLET_FIR, bit(6)) ? analyzeConnectedXBUS2; + + /** XB_CHIPLET_FIR[8] + * Attention from IOXBFIR 0 + */ + (rXB_CHIPLET_FIR, bit(8)) ? analyzeConnectedXBUS0; + + /** XB_CHIPLET_FIR[9] + * Attention from IOXBFIR 1 + */ + (rXB_CHIPLET_FIR, bit(9)) ? analyzeConnectedXBUS1; + + /** XB_CHIPLET_FIR[10] + * Attention from IOXBFIR 2 + */ + (rXB_CHIPLET_FIR, bit(10)) ? analyzeConnectedXBUS2; + + /** XB_CHIPLET_FIR[11] + * Attention from XBPPEFIR + */ + (rXB_CHIPLET_FIR, bit(11)) ? analyzeXBPPEFIR; + +}; + +################################################################################ +# XB Chiplet Unit Checkstop FIR +################################################################################ + +rule rXB_CHIPLET_UCS_FIR +{ + UNIT_CS: + XB_CHIPLET_UCS_FIR & ~(XB_CHIPLET_UCS_FIR_MASK >> 1) & `7fffffffffffffff`; +}; + +group gXB_CHIPLET_UCS_FIR + filter singlebit +{ + /** XB_CHIPLET_UCS_FIR[1] + * Attention from IOELFIR 0 + */ + (rXB_CHIPLET_UCS_FIR, bit(1)) ? analyzeConnectedXBUS0; + + /** XB_CHIPLET_UCS_FIR[2] + * Attention from IOELFIR 1 + */ + (rXB_CHIPLET_UCS_FIR, bit(2)) ? analyzeConnectedXBUS1; + + /** XB_CHIPLET_UCS_FIR[3] + * Attention from IOELFIR 2 + */ + (rXB_CHIPLET_UCS_FIR, bit(3)) ? analyzeConnectedXBUS2; + + /** XB_CHIPLET_UCS_FIR[5] + * Attention from IOXBFIR 0 + */ + (rXB_CHIPLET_UCS_FIR, bit(5)) ? analyzeConnectedXBUS0; + + /** XB_CHIPLET_UCS_FIR[6] + * Attention from IOXBFIR 1 + */ + (rXB_CHIPLET_UCS_FIR, bit(6)) ? analyzeConnectedXBUS1; + + /** XB_CHIPLET_UCS_FIR[7] + * Attention from IOXBFIR 2 + */ + (rXB_CHIPLET_UCS_FIR, bit(7)) ? analyzeConnectedXBUS2; + + /** XB_CHIPLET_UCS_FIR[8] + * Attention from XBPPEFIR + */ + (rXB_CHIPLET_UCS_FIR, bit(8)) ? analyzeXBPPEFIR; + +}; + +################################################################################ +# P9 chip XB_LFIR +################################################################################ + +rule rXB_LFIR +{ + CHECK_STOP: + XB_LFIR & ~XB_LFIR_MASK & ~XB_LFIR_ACT0 & ~XB_LFIR_ACT1; + RECOVERABLE: + XB_LFIR & ~XB_LFIR_MASK & ~XB_LFIR_ACT0 & XB_LFIR_ACT1; +}; + +group gXB_LFIR + filter singlebit, + cs_root_cause +{ + /** XB_LFIR[0] + * CFIR internal parity error + */ + (rXB_LFIR, bit(0)) ? self_th_32perDay; + + /** XB_LFIR[1] + * Chiplet Control Reg: PCB Access Error + */ + (rXB_LFIR, bit(1)) ? self_th_32perDay; + + /** XB_LFIR[2] + * Clock Controller: PCB Access Error + */ + (rXB_LFIR, bit(2)) ? self_th_32perDay; + + /** XB_LFIR[3] + * Clock Controller: Summarized Error + */ + (rXB_LFIR, bit(3)) ? self_th_32perDay; + + /** XB_LFIR[4] + * PSCOM Logic: PCB Access Error + */ + (rXB_LFIR, bit(4)) ? defaultMaskedError; + + /** XB_LFIR[5] + * PSCOM Logic: Summarized internal errors + */ + (rXB_LFIR, bit(5)) ? defaultMaskedError; + + /** XB_LFIR[6] + * Therm Logic: Summarized internal errors + */ + (rXB_LFIR, bit(6)) ? defaultMaskedError; + + /** XB_LFIR[7] + * Therm Logic: PCB Access Error + */ + (rXB_LFIR, bit(7)) ? defaultMaskedError; + + /** XB_LFIR[8] + * Therm Logic: Temperature critical trip + */ + (rXB_LFIR, bit(8)) ? defaultMaskedError; + + /** XB_LFIR[9] + * Therm Logic: Temperature fatal trip + */ + (rXB_LFIR, bit(9)) ? defaultMaskedError; + + /** XB_LFIR[10] + * UNUSED in P9 + */ + (rXB_LFIR, bit(10)) ? defaultMaskedError; + + /** XB_LFIR[11] + * Debug Logic: Scom Satelite Error + */ + (rXB_LFIR, bit(11)) ? defaultMaskedError; + + /** XB_LFIR[12] + * Scom Satellite Err - Trace0 + */ + (rXB_LFIR, bit(12)) ? defaultMaskedError; + + /** XB_LFIR[13] + * Scom Satellite Err - Trace0 + */ + (rXB_LFIR, bit(13)) ? defaultMaskedError; + + /** XB_LFIR[14] + * Scom Satellite Err - Trace1 + */ + (rXB_LFIR, bit(14)) ? defaultMaskedError; + + /** XB_LFIR[15] + * Scom Satellite Err - Trace1 + */ + (rXB_LFIR, bit(15)) ? defaultMaskedError; + + /** XB_LFIR[16:40] + * spare + */ + (rXB_LFIR, bit(16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError; + + /** XB_LFIR[41] + * Malfunction Alert or Local Checkstop + */ + (rXB_LFIR, bit(41)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 chip XBPPEFIR +################################################################################ + +rule rXBPPEFIR +{ + CHECK_STOP: + XBPPEFIR & ~XBPPEFIR_MASK & ~XBPPEFIR_ACT0 & ~XBPPEFIR_ACT1; + RECOVERABLE: + XBPPEFIR & ~XBPPEFIR_MASK & ~XBPPEFIR_ACT0 & XBPPEFIR_ACT1; + UNIT_CS: + XBPPEFIR & ~XBPPEFIR_MASK & XBPPEFIR_ACT0 & XBPPEFIR_ACT1; +}; + +group gXBPPEFIR + filter singlebit, + cs_root_cause +{ + /** XBPPEFIR[0] + * PPE general error. + */ + (rXBPPEFIR, bit(0)) ? threshold_and_mask_self; + + /** XBPPEFIR[1] + * PPE general error. + */ + (rXBPPEFIR, bit(1)) ? threshold_and_mask_self; + + /** XBPPEFIR[2] + * PPE general error. + */ + (rXBPPEFIR, bit(2)) ? threshold_and_mask_self; + + /** XBPPEFIR[3] + * PPE general error. + */ + (rXBPPEFIR, bit(3)) ? threshold_and_mask_self; + + /** XBPPEFIR[4] + * PPE halted. + */ + (rXBPPEFIR, bit(4)) ? defaultMaskedError; + + /** XBPPEFIR[5] + * PPE watchdog timer timed out + */ + (rXBPPEFIR, bit(5)) ? defaultMaskedError; + + /** XBPPEFIR[6] + * MMIO data in error. + */ + (rXBPPEFIR, bit(6)) ? defaultMaskedError; + + /** XBPPEFIR[7] + * Arb missed scrub tick. + */ + (rXBPPEFIR, bit(7)) ? threshold_and_mask_self; + + /** XBPPEFIR[8] + * Arb ary ue error. + */ + (rXBPPEFIR, bit(8)) ? self_th_1; + + /** XBPPEFIR[9] + * Arb ary ce error. + */ + (rXBPPEFIR, bit(9)) ? threshold_and_mask_self; + + /** XBPPEFIR[10] + * spare + */ + (rXBPPEFIR, bit(10)) ? defaultMaskedError; + + /** XBPPEFIR[11] + * FIR_SCOMFIR_ERROR + */ + (rXBPPEFIR, bit(11)) ? defaultMaskedError; + + /** XBPPEFIR[12] + * FIR_SCOMFIR_ERROR + */ + (rXBPPEFIR, bit(12)) ? defaultMaskedError; + +}; + +################################################################################ +# PCI0 Chiplet FIR +################################################################################ + +rule rPCI0_CHIPLET_FIR +{ + CHECK_STOP: + PCI0_CHIPLET_CS_FIR & ~PCI0_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (PCI0_CHIPLET_RE_FIR >> 2) & ~PCI0_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gPCI0_CHIPLET_FIR + filter singlebit +{ + /** PCI0_CHIPLET_FIR[3] + * Attention from PCI_LFIR 0 + */ + (rPCI0_CHIPLET_FIR, bit(3)) ? analyzeConnectedPEC0; + + /** PCI0_CHIPLET_FIR[4] + * Attention from ETUFIR 0 + */ + (rPCI0_CHIPLET_FIR, bit(4)) ? analyzeConnectedPHB0; + + /** PCI0_CHIPLET_FIR[5] + * Attention from IOPCIFIR 0 + */ + (rPCI0_CHIPLET_FIR, bit(5)) ? analyzeConnectedPEC0; + + /** PCI0_CHIPLET_FIR[6] + * Attention from PCIFIR 0 + */ + (rPCI0_CHIPLET_FIR, bit(6)) ? analyzeConnectedPHB0; + +}; + +################################################################################ +# PCI1 Chiplet FIR +################################################################################ + +rule rPCI1_CHIPLET_FIR +{ + CHECK_STOP: + PCI1_CHIPLET_CS_FIR & ~PCI1_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (PCI1_CHIPLET_RE_FIR >> 2) & ~PCI1_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gPCI1_CHIPLET_FIR + filter singlebit +{ + /** PCI1_CHIPLET_FIR[3] + * Attention from PCI_LFIR 1 + */ + (rPCI1_CHIPLET_FIR, bit(3)) ? analyzeConnectedPEC1; + + /** PCI1_CHIPLET_FIR[4] + * Attention from ETUFIR 1 + */ + (rPCI1_CHIPLET_FIR, bit(4)) ? analyzeConnectedPHB1; + + /** PCI1_CHIPLET_FIR[5] + * Attention from ETUFIR 2 + */ + (rPCI1_CHIPLET_FIR, bit(5)) ? analyzeConnectedPHB2; + + /** PCI1_CHIPLET_FIR[6] + * Attention from IOPCIFIR 1 + */ + (rPCI1_CHIPLET_FIR, bit(6)) ? analyzeConnectedPEC1; + + /** PCI1_CHIPLET_FIR[7] + * Attention from PCIFIR 1 + */ + (rPCI1_CHIPLET_FIR, bit(7)) ? analyzeConnectedPHB1; + + /** PCI1_CHIPLET_FIR[8] + * Attention from PCIFIR 2 + */ + (rPCI1_CHIPLET_FIR, bit(8)) ? analyzeConnectedPHB2; + +}; + +################################################################################ +# PCI2 Chiplet FIR +################################################################################ + +rule rPCI2_CHIPLET_FIR +{ + CHECK_STOP: + PCI2_CHIPLET_CS_FIR & ~PCI2_CHIPLET_FIR_MASK & `1fffffffffffffff`; + RECOVERABLE: + (PCI2_CHIPLET_RE_FIR >> 2) & ~PCI2_CHIPLET_FIR_MASK & `1fffffffffffffff`; +}; + +group gPCI2_CHIPLET_FIR + filter singlebit +{ + /** PCI2_CHIPLET_FIR[3] + * Attention from PCI_LFIR 2 + */ + (rPCI2_CHIPLET_FIR, bit(3)) ? analyzeConnectedPEC2; + + /** PCI2_CHIPLET_FIR[4] + * Attention from ETUFIR 3 + */ + (rPCI2_CHIPLET_FIR, bit(4)) ? analyzeConnectedPHB3; + + /** PCI2_CHIPLET_FIR[5] + * Attention from ETUFIR 4 + */ + (rPCI2_CHIPLET_FIR, bit(5)) ? analyzeConnectedPHB4; + + /** PCI2_CHIPLET_FIR[6] + * Attention from ETUFIR 5 + */ + (rPCI2_CHIPLET_FIR, bit(6)) ? analyzeConnectedPHB5; + + /** PCI2_CHIPLET_FIR[7] + * Attention from IOPCIFIR 2 + */ + (rPCI2_CHIPLET_FIR, bit(7)) ? analyzeConnectedPEC2; + + /** PCI2_CHIPLET_FIR[8] + * Attention from PCIFIR 3 + */ + (rPCI2_CHIPLET_FIR, bit(8)) ? analyzeConnectedPHB3; + + /** PCI2_CHIPLET_FIR[9] + * Attention from PCIFIR 4 + */ + (rPCI2_CHIPLET_FIR, bit(9)) ? analyzeConnectedPHB4; + + /** PCI2_CHIPLET_FIR[10] + * Attention from PCIFIR 5 + */ + (rPCI2_CHIPLET_FIR, bit(10)) ? analyzeConnectedPHB5; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "p9_common_proc_actions.rule"; +.include "axone_proc_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_proc_actions.rule b/src/usr/diag/prdf/common/plat/axone/axone_proc_actions.rule new file mode 100644 index 000000000..b6e056498 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_proc_actions.rule @@ -0,0 +1,42 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_proc_actions.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +################################################################################ +# Analyze connected +################################################################################ + +actionclass analyzeConnectedNPU0 { analyze(connected(TYPE_NPU, 0)); }; +actionclass analyzeConnectedNPU1 { analyze(connected(TYPE_NPU, 1)); }; +actionclass analyzeConnectedNPU2 { analyze(connected(TYPE_NPU, 2)); }; +actionclass analyzeConnectedOBUS1 { analyze(connected(TYPE_OBUS, 1)); }; +actionclass analyzeConnectedOBUS2 { analyze(connected(TYPE_OBUS, 2)); }; +actionclass analyzeConnectedXBUS0 { analyze(connected(TYPE_XBUS, 0)); }; +actionclass analyzeConnectedMC0 { analyze(connected(TYPE_MC, 0)); }; +actionclass analyzeConnectedMC1 { analyze(connected(TYPE_MC, 1)); }; +actionclass analyzeConnectedMI0 { analyze(connected(TYPE_MI, 0)); }; +actionclass analyzeConnectedMI1 { analyze(connected(TYPE_MI, 1)); }; +actionclass analyzeConnectedMI2 { analyze(connected(TYPE_MI, 2)); }; +actionclass analyzeConnectedMI3 { analyze(connected(TYPE_MI, 3)); }; + diff --git a/src/usr/diag/prdf/common/plat/axone/axone_xbus.rule b/src/usr/diag/prdf/common/plat/axone/axone_xbus.rule new file mode 100644 index 000000000..8c4b8a06a --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/axone_xbus.rule @@ -0,0 +1,593 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/axone_xbus.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +chip axone_xbus +{ + name "AXONE XBUS target"; + targettype TYPE_XBUS; + sigoff 0x0000; + dump DUMP_CONTENT_HW; + scomlen 64; + +# Import signatures +.include "prdfLaneRepairExtraSig.H"; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # P9 XBUS target IOXBFIR + ############################################################################ + + register IOXBFIR + { + name "P9 XBUS target IOXBFIR"; + scomaddr 0x06010c00; + reset (&, 0x06010c01); + mask (|, 0x06010c05); + capture group default; + }; + + register IOXBFIR_MASK + { + name "P9 XBUS target IOXBFIR MASK"; + scomaddr 0x06010c03; + capture group default; + }; + + register IOXBFIR_ACT0 + { + name "P9 XBUS target IOXBFIR ACT0"; + scomaddr 0x06010c06; + capture group default; + capture req nonzero("IOXBFIR"); + }; + + register IOXBFIR_ACT1 + { + name "P9 XBUS target IOXBFIR ACT1"; + scomaddr 0x06010c07; + capture group default; + capture req nonzero("IOXBFIR"); + }; + + ############################################################################ + # P9 XBUS target IOELFIR + ############################################################################ + + register IOELFIR + { + name "P9 XBUS target IOELFIR"; + scomaddr 0x06011800; + reset (&, 0x06011801); + mask (|, 0x06011805); + capture group default; + }; + + register IOELFIR_MASK + { + name "P9 XBUS target IOELFIR MASK"; + scomaddr 0x06011803; + capture group default; + }; + + register IOELFIR_ACT0 + { + name "P9 XBUS target IOELFIR ACT0"; + scomaddr 0x06011806; + capture group default; + capture req nonzero("IOELFIR"); + }; + + register IOELFIR_ACT1 + { + name "P9 XBUS target IOELFIR ACT1"; + scomaddr 0x06011807; + capture group default; + capture req nonzero("IOELFIR"); + }; + +# Include registers not defined by the xml +.include "p9_common_xbus_regs.rule"; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Summary for XBUS +################################################################################ + +rule rXBUS +{ + CHECK_STOP: + summary( 0, rIOXBFIR ) | + summary( 1, rIOELFIR ); + + RECOVERABLE: + summary( 0, rIOXBFIR ) | + summary( 1, rIOELFIR ); + + UNIT_CS: + summary( 0, rIOXBFIR ) | + summary( 1, rIOELFIR ); + +}; + +group gXBUS attntype CHECK_STOP, RECOVERABLE, UNIT_CS + filter singlebit +{ + (rXBUS, bit(0)) ? analyzeIOXBFIR; + (rXBUS, bit(1)) ? analyzeIOELFIR; +}; + +################################################################################ +# P9 XBUS target IOXBFIR +################################################################################ + +rule rIOXBFIR +{ + CHECK_STOP: + IOXBFIR & ~IOXBFIR_MASK & ~IOXBFIR_ACT0 & ~IOXBFIR_ACT1; + RECOVERABLE: + IOXBFIR & ~IOXBFIR_MASK & ~IOXBFIR_ACT0 & IOXBFIR_ACT1; + UNIT_CS: + IOXBFIR & ~IOXBFIR_MASK & IOXBFIR_ACT0 & IOXBFIR_ACT1; +}; + +group gIOXBFIR + filter singlebit, + cs_root_cause +{ + /** IOXBFIR[0] + * RX_INVALID_STATE_OR_PARITY_ERROR + */ + (rIOXBFIR, bit(0)) ? defaultMaskedError; + + /** IOXBFIR[1] + * TX_INVALID_STATE_OR_PARITY_ERROR + */ + (rIOXBFIR, bit(1)) ? defaultMaskedError; + + /** IOXBFIR[2] + * GCR_HANG_ERROR + */ + (rIOXBFIR, bit(2)) ? self_th_1; + + /** IOXBFIR[3:7] + * spare + */ + (rIOXBFIR, bit(3|4|5|6|7)) ? defaultMaskedError; + + /** IOXBFIR[8] + * RX_BUS0_TRAINING_ERROR + */ + (rIOXBFIR, bit(8)) ? defaultMaskedError; + + /** IOXBFIR[9] + * Spare lane deployed on clock group 0 + */ + (rIOXBFIR, bit(9)) ? spareDeployed_xbus_clkgrp0; + + /** IOXBFIR[10] + * Max spares exceeded on clock group 0 + */ + (rIOXBFIR, bit(10)) ? maxSparesExceeded_xbus_clkgrp0; + + /** IOXBFIR[11] + * RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR + */ + (rIOXBFIR, bit(11)) ? defaultMaskedError; + + /** IOXBFIR[12] + * Too many bus errors on clock group 0 + */ + (rIOXBFIR, bit(12)) ? tooManyBusErrors_xbus_clkgrp0; + + /** IOXBFIR[13:15] + * spare + */ + (rIOXBFIR, bit(13|14|15)) ? defaultMaskedError; + + /** IOXBFIR[16] + * RX_BUS1_TRAINING_ERROR + */ + (rIOXBFIR, bit(16)) ? defaultMaskedError; + + /** IOXBFIR[17] + * Spare lane deployed on clock group 1 + */ + (rIOXBFIR, bit(17)) ? spareDeployed_xbus_clkgrp1; + + /** IOXBFIR[18] + * Max spares exceeded on clock group 1 + */ + (rIOXBFIR, bit(18)) ? maxSparesExceeded_xbus_clkgrp1; + + /** IOXBFIR[19] + * RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR + */ + (rIOXBFIR, bit(19)) ? defaultMaskedError; + + /** IOXBFIR[20] + * Too many bus errors on clock group 1 + */ + (rIOXBFIR, bit(20)) ? tooManyBusErrors_xbus_clkgrp1; + + /** IOXBFIR[21:23] + * spare + */ + (rIOXBFIR, bit(21|22|23)) ? defaultMaskedError; + + /** IOXBFIR[24] + * RX_BUS2_TRAINING_ERROR + */ + (rIOXBFIR, bit(24)) ? defaultMaskedError; + + /** IOXBFIR[25] + * RX_BUS2_SPARE_DEPLOYED + */ + (rIOXBFIR, bit(25)) ? defaultMaskedError; + + /** IOXBFIR[26] + * RX_BUS2_MAX_SPARES_EXCEEDED + */ + (rIOXBFIR, bit(26)) ? defaultMaskedError; + + /** IOXBFIR[27] + * RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR + */ + (rIOXBFIR, bit(27)) ? defaultMaskedError; + + /** IOXBFIR[28] + * RX_BUS2_TOO_MANY_BUS_ERRORS + */ + (rIOXBFIR, bit(28)) ? defaultMaskedError; + + /** IOXBFIR[29:31] + * spare + */ + (rIOXBFIR, bit(29|30|31)) ? defaultMaskedError; + + /** IOXBFIR[32] + * RX_BUS3_TRAINING_ERROR + */ + (rIOXBFIR, bit(32)) ? defaultMaskedError; + + /** IOXBFIR[33] + * RX_BUS3_SPARE_DEPLOYED + */ + (rIOXBFIR, bit(33)) ? defaultMaskedError; + + /** IOXBFIR[34] + * RX_BUS3_MAX_SPARES_EXCEEDED + */ + (rIOXBFIR, bit(34)) ? defaultMaskedError; + + /** IOXBFIR[35] + * RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR + */ + (rIOXBFIR, bit(35)) ? defaultMaskedError; + + /** IOXBFIR[36] + * RX_BUS3_TOO_MANY_BUS_ERRORS + */ + (rIOXBFIR, bit(36)) ? defaultMaskedError; + + /** IOXBFIR[37:39] + * spare + */ + (rIOXBFIR, bit(37|38|39)) ? defaultMaskedError; + + /** IOXBFIR[40] + * RX_BUS4_TRAINING_ERROR + */ + (rIOXBFIR, bit(40)) ? defaultMaskedError; + + /** IOXBFIR[41] + * RX_BUS4_SPARE_DEPLOYED + */ + (rIOXBFIR, bit(41)) ? defaultMaskedError; + + /** IOXBFIR[42] + * RX_BUS4_MAX_SPARES_EXCEEDED + */ + (rIOXBFIR, bit(42)) ? defaultMaskedError; + + /** IOXBFIR[43] + * RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR + */ + (rIOXBFIR, bit(43)) ? defaultMaskedError; + + /** IOXBFIR[44] + * RX_BUS4_TOO_MANY_BUS_ERRORS + */ + (rIOXBFIR, bit(44)) ? defaultMaskedError; + + /** IOXBFIR[45:47] + * spare + */ + (rIOXBFIR, bit(45|46|47)) ? defaultMaskedError; + + /** IOXBFIR[48] + * SCOMFIR_ERROR + */ + (rIOXBFIR, bit(48)) ? defaultMaskedError; + + /** IOXBFIR[49] + * SCOMFIR_ERROR_CLONE + */ + (rIOXBFIR, bit(49)) ? defaultMaskedError; + +}; + +################################################################################ +# P9 XBUS target IOELFIR +################################################################################ + +rule rIOELFIR +{ + CHECK_STOP: + IOELFIR & ~IOELFIR_MASK & ~IOELFIR_ACT0 & ~IOELFIR_ACT1; + RECOVERABLE: + IOELFIR & ~IOELFIR_MASK & ~IOELFIR_ACT0 & IOELFIR_ACT1; + UNIT_CS: + IOELFIR & ~IOELFIR_MASK & IOELFIR_ACT0 & IOELFIR_ACT1; +}; + +group gIOELFIR + filter singlebit, + cs_root_cause(54,55,56,57,58,59) +{ + /** IOELFIR[0] + * link0 trained + */ + (rIOELFIR, bit(0)) ? defaultMaskedError; + + /** IOELFIR[1] + * link1 trained + */ + (rIOELFIR, bit(1)) ? defaultMaskedError; + + /** IOELFIR[2:3] + * spare + */ + (rIOELFIR, bit(2|3)) ? defaultMaskedError; + + /** IOELFIR[4] + * link0 replay threshold + */ + (rIOELFIR, bit(4)) ? defaultMaskedError; + + /** IOELFIR[5] + * link1 replay threshold + */ + (rIOELFIR, bit(5)) ? defaultMaskedError; + + /** IOELFIR[6] + * link0 crc error + */ + (rIOELFIR, bit(6)) ? threshold_and_mask_self; + + /** IOELFIR[7] + * link1 crc error + */ + (rIOELFIR, bit(7)) ? threshold_and_mask_self; + + /** IOELFIR[8] + * link0 nak received + */ + (rIOELFIR, bit(8)) ? defaultMaskedError; + + /** IOELFIR[9] + * link1 nak received + */ + (rIOELFIR, bit(9)) ? defaultMaskedError; + + /** IOELFIR[10] + * link0 replay buffer full + */ + (rIOELFIR, bit(10)) ? defaultMaskedError; + + /** IOELFIR[11] + * link1 replay buffer full + */ + (rIOELFIR, bit(11)) ? defaultMaskedError; + + /** IOELFIR[12] + * link0 sl ecc threshold + */ + (rIOELFIR, bit(12)) ? defaultMaskedError; + + /** IOELFIR[13] + * link1 sl ecc threshold + */ + (rIOELFIR, bit(13)) ? defaultMaskedError; + + /** IOELFIR[14] + * link0 sl ecc correctable + */ + (rIOELFIR, bit(14)) ? threshold_and_mask_self; + + /** IOELFIR[15] + * link1 sl ecc correctable + */ + (rIOELFIR, bit(15)) ? threshold_and_mask_self; + + /** IOELFIR[16] + * link0 sl ecc ue + */ + (rIOELFIR, bit(16)) ? threshold_and_mask_self; + + /** IOELFIR[17] + * link1 sl ecc ue + */ + (rIOELFIR, bit(17)) ? threshold_and_mask_self; + + /** IOELFIR[18:39] + * spare + */ + (rIOELFIR, bit(18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; + + /** IOELFIR[40] + * link0 tcomplete bad + */ + (rIOELFIR, bit(40)) ? defaultMaskedError; + + /** IOELFIR[41] + * link1 tcomplete bad + */ + (rIOELFIR, bit(41)) ? defaultMaskedError; + + /** IOELFIR[42:43] + * spare + */ + (rIOELFIR, bit(42|43)) ? defaultMaskedError; + + /** IOELFIR[44] + * link0 spare done + */ + (rIOELFIR, bit(44)) ? defaultMaskedError; + + /** IOELFIR[45] + * link1 spare done + */ + (rIOELFIR, bit(45)) ? defaultMaskedError; + + /** IOELFIR[46] + * link0 too many crc errors + */ + (rIOELFIR, bit(46)) ? defaultMaskedError; + + /** IOELFIR[47] + * link1 too many crc errors + */ + (rIOELFIR, bit(47)) ? defaultMaskedError; + + /** IOELFIR[48:50] + * spare + */ + (rIOELFIR, bit(48|49|50)) ? defaultMaskedError; + + /** IOELFIR[51] + * psave invalid state (internal error) + */ + (rIOELFIR, bit(51)) ? self_th_1; + + /** IOELFIR[52] + * link0 correctable array error + */ + (rIOELFIR, bit(52)) ? calloutBusInterface_th_32perDay; + + /** IOELFIR[53] + * link1 correctable array error + */ + (rIOELFIR, bit(53)) ? calloutBusInterface_th_32perDay; + + /** IOELFIR[54] + * link0 uncorrectable array error + */ + (rIOELFIR, bit(54)) ? calloutBusInterface_th_32perDay; + + /** IOELFIR[55] + * link1 uncorrectable array error + */ + (rIOELFIR, bit(55)) ? calloutBusInterface_th_32perDay; + + /** IOELFIR[56] + * link0 training failed + */ + (rIOELFIR, bit(56)) ? calloutBusInterface_th_32perDay; + + /** IOELFIR[57] + * link1 training failed + */ + (rIOELFIR, bit(57)) ? calloutBusInterface_th_32perDay; + + /** IOELFIR[58] + * link0 unrecoverable error + */ + (rIOELFIR, bit(58)) ? calloutBusInterface_th_32perDay; + + /** IOELFIR[59] + * link1 unrecoverable error + */ + (rIOELFIR, bit(59)) ? calloutBusInterface_th_32perDay; + + /** IOELFIR[60] + * link0 internal error + */ + (rIOELFIR, bit(60)) ? self_th_32perDay; + + /** IOELFIR[61] + * link1 internal error + */ + (rIOELFIR, bit(61)) ? self_th_32perDay; + + /** IOELFIR[62] + * fir scom err dup + */ + (rIOELFIR, bit(62)) ? defaultMaskedError; + + /** IOELFIR[63] + * fir scom err + */ + (rIOELFIR, bit(63)) ? defaultMaskedError; + +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the actions defined for this target +.include "p9_common_actions.rule"; +.include "p9_common_xbus_actions.rule"; + diff --git a/src/usr/diag/prdf/common/plat/axone/prdf_plat_axone.mk b/src/usr/diag/prdf/common/plat/axone/prdf_plat_axone.mk new file mode 100644 index 000000000..ea76f9121 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/axone/prdf_plat_axone.mk @@ -0,0 +1,41 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/axone/prdf_plat_axone.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2016,2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# NOTE: PRD_SRC_PATH must be defined before including this file. + +################################################################################ +# Paths common to both FSP and Hostboot +################################################################################ + +prd_vpath += ${PRD_SRC_PATH}/common/plat/axone + +prd_incpath += ${PRD_SRC_PATH}/common/plat/axone + +################################################################################ +# Object files common to both FSP and Hostboot +################################################################################ + +# plat/cumulus/ (rule plugin related) + diff --git a/src/usr/diag/prdf/common/plugins/prdfLogParse_common.C b/src/usr/diag/prdf/common/plugins/prdfLogParse_common.C index 2e72db2f4..46c05c862 100644 --- a/src/usr/diag/prdf/common/plugins/prdfLogParse_common.C +++ b/src/usr/diag/prdf/common/plugins/prdfLogParse_common.C @@ -191,6 +191,13 @@ void getTargetInfo( HUID i_chipId, TARGETING::TYPE & o_targetType, l_node, l_chip, l_chiplet ); break; + case TYPE_NPU: + l_chip = l_chip / MAX_NPU_PER_PROC; + l_chiplet = l_chiplet % MAX_NPU_PER_PROC; + snprintf( o_chipName, i_sz_chipName, "npu(n%dp%dc%d)", + l_node, l_chip, l_chiplet ); + break; + case TYPE_PEC: l_chip = l_chip / MAX_PEC_PER_PROC; l_chiplet = l_chiplet % MAX_PEC_PER_PROC; @@ -261,6 +268,20 @@ void getTargetInfo( HUID i_chipId, TARGETING::TYPE & o_targetType, l_node, l_chip, l_chiplet ); break; + case TYPE_MCC: + l_chip = l_chip / MAX_MCC_PER_PROC; + l_chiplet = l_chiplet % MAX_MCC_PER_PROC; + snprintf( o_chipName, i_sz_chipName, "mcc(n%dp%dc%d)", + l_node, l_chip, l_chiplet ); + break; + + case TYPE_OMIC: + l_chip = l_chip / MAX_OMIC_PER_PROC; + l_chiplet = l_chiplet % MAX_OMIC_PER_PROC; + snprintf( o_chipName, i_sz_chipName, "omic(n%dp%dc%d)", + l_node, l_chip, l_chiplet ); + break; + case TYPE_MEMBUF: snprintf( o_chipName, i_sz_chipName, "mb(n%dp%d)", l_node, l_chip ); diff --git a/src/usr/diag/prdf/common/plugins/prdfParserEnums.H b/src/usr/diag/prdf/common/plugins/prdfParserEnums.H index 05dde7269..78232ba68 100644 --- a/src/usr/diag/prdf/common/plugins/prdfParserEnums.H +++ b/src/usr/diag/prdf/common/plugins/prdfParserEnums.H @@ -100,10 +100,17 @@ enum PositionBounds MAX_L4_PER_MEMBUF = 1, MAX_MCC_PER_MI = 2, - MAX_OMI_PER_MCC = 2, + MAX_MCC_PER_MC = MAX_MCC_PER_MI * MAX_MI_PER_MC, + MAX_MCC_PER_PROC = MAX_MCC_PER_MC * MAX_MC_PER_PROC, + MAX_OMIC_PER_MC = 3, + MAX_OMIC_PER_PROC = MAX_OMIC_PER_MC * MAX_MC_PER_PROC, + + MAX_OMI_PER_MCC = 2, MAX_OMI_PER_OMIC = 3, + MAX_OCMB_PER_OMI = 1, + MAX_NPU_PER_PROC = 3, INVALID_POSITION_BOUND = 0xffffffff, diff --git a/src/usr/diag/prdf/common/rule/prdfRuleFiles.C b/src/usr/diag/prdf/common/rule/prdfRuleFiles.C index 0c6f7c03a..4d50ced64 100755 --- a/src/usr/diag/prdf/common/rule/prdfRuleFiles.C +++ b/src/usr/diag/prdf/common/rule/prdfRuleFiles.C @@ -61,6 +61,22 @@ namespace PRDF const char * cumulus_mi = "cumulus_mi"; const char * cumulus_dmi = "cumulus_dmi"; + // P9 Axone Chip + const char * axone_proc = "axone_proc"; + const char * axone_eq = "axone_eq"; + const char * axone_ex = "axone_ex"; + const char * axone_ec = "axone_ec"; + const char * axone_capp = "axone_capp"; + const char * axone_npu = "axone_npu"; + const char * axone_pec = "axone_pec"; + const char * axone_phb = "axone_phb"; + const char * axone_xbus = "axone_xbus"; + const char * axone_obus = "axone_obus"; + const char * axone_mc = "axone_mc"; + const char * axone_mi = "axone_mi"; + const char * axone_mcc = "axone_mcc"; + const char * axone_omic = "axone_omic"; + // Centaur Chip const char * centaur_membuf = "centaur_membuf"; const char * centaur_mba = "centaur_mba"; diff --git a/src/usr/diag/prdf/common/rule/prdfRuleFiles.H b/src/usr/diag/prdf/common/rule/prdfRuleFiles.H index ecb227184..f62f4beb0 100755 --- a/src/usr/diag/prdf/common/rule/prdfRuleFiles.H +++ b/src/usr/diag/prdf/common/rule/prdfRuleFiles.H @@ -62,6 +62,22 @@ namespace PRDF extern const char * cumulus_mi; extern const char * cumulus_dmi; + // P9 Axone Chip + extern const char * axone_proc; + extern const char * axone_eq; + extern const char * axone_ex; + extern const char * axone_ec; + extern const char * axone_capp; + extern const char * axone_npu; + extern const char * axone_pec; + extern const char * axone_phb; + extern const char * axone_xbus; + extern const char * axone_obus; + extern const char * axone_mc; + extern const char * axone_mi; + extern const char * axone_mcc; + extern const char * axone_omic; + // Centaur Chip extern const char * centaur_membuf; extern const char * centaur_mba; diff --git a/src/usr/diag/prdf/common/rule/prdf_rule.mk b/src/usr/diag/prdf/common/rule/prdf_rule.mk index 62f95a676..704210d5d 100644 --- a/src/usr/diag/prdf/common/rule/prdf_rule.mk +++ b/src/usr/diag/prdf/common/rule/prdf_rule.mk @@ -51,6 +51,22 @@ PRDR_RULE_TABLES += cumulus_mc.prf PRDR_RULE_TABLES += cumulus_mi.prf PRDR_RULE_TABLES += cumulus_dmi.prf +# P9 Axone Chip +PRDR_RULE_TABLES += axone_proc.prf +PRDR_RULE_TABLES += axone_eq.prf +PRDR_RULE_TABLES += axone_ex.prf +PRDR_RULE_TABLES += axone_ec.prf +PRDR_RULE_TABLES += axone_capp.prf +PRDR_RULE_TABLES += axone_npu.prf +PRDR_RULE_TABLES += axone_pec.prf +PRDR_RULE_TABLES += axone_phb.prf +PRDR_RULE_TABLES += axone_xbus.prf +PRDR_RULE_TABLES += axone_obus.prf +PRDR_RULE_TABLES += axone_mc.prf +PRDR_RULE_TABLES += axone_mi.prf +PRDR_RULE_TABLES += axone_mcc.prf +PRDR_RULE_TABLES += axone_omic.prf + # Centaur Chip PRDR_RULE_TABLES += centaur_membuf.prf PRDR_RULE_TABLES += centaur_mba.prf diff --git a/src/usr/diag/prdf/rule/makefile b/src/usr/diag/prdf/rule/makefile index ef13022eb..dccd386af 100755 --- a/src/usr/diag/prdf/rule/makefile +++ b/src/usr/diag/prdf/rule/makefile @@ -206,12 +206,14 @@ ${PRDR_CMP_PATH}: ${PRDR_CMP_YACC_o_PATH} ${PRDR_CMP_FLEX_o_PATH} \ vpath %.rule \ ../common/plat/p9 \ + ../common/plat/axone \ ../common/plat/centaur \ ../common/plat/cumulus \ ../common/plat/mem \ ../common/plat/nimbus PRDRPP_SEARCHDIRS = -I../common/plat/p9 \ + -I../common/plat/axone \ -I../common/plat/centaur \ -I../common/plat/cumulus \ -I../common/plat/mem \ |
