Use readSeeprom PSU chipop to get SBE seeprom image version

During an SBE update we were getting I2C collisions when trying to
access pnor on the "running" or "active" side of the seeprom. This
commit adds support for a PSU chipOp called "readSeeprom" which
allows the host to make a request to the SBE to copy a specified
chunk of pnor out to a buffer in memory which the host can access.
This commit also uses this chipOp in place of the I2C read during
the SBE update of the active seeprom side.

Change-Id: I4b639ebe6090dcc0bdbb42f13fcb12c23260a8b4
RTC: 180959
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48408
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 76 insertions, 2 deletions

diff --git a/src/include/usr/sbe/sbe_update.H b/src/include/usr/sbe/sbe_update.H
index 25d7448af..45e295c2d 100644
--- a/src/include/usr/sbe/sbe_update.H
+++ b/src/include/usr/sbe/sbe_update.H
@@ -77,12 +77,17 @@ namespace SBE
     const uint64_t SBE_VERSION_SPACE_WITH_ECC   = (256 * 9) / 8; // 256B + ECC
     const uint64_t SBE_SEEPROM_SIZE             = 64*KILOBYTE;   // 64KB
     const uint64_t SBE_SEEPROM_ECC_PAD          = SBE_SEEPROM_SIZE % 9;
+    const uint64_t SBE_SEEPROM_SIZE_WO_ECC      = ((64*KILOBYTE - SBE_SEEPROM_ECC_PAD) / 9) * 8 ;
     // SBE Version (with ECC) kept at end of fourth 64KB memory
     // Adjust end of usable memory with ECC to be a multiple of 9 bytes
     const uint64_t SBE_VERSION_SEEPROM_ADDRESS  = 4*SBE_SEEPROM_SIZE
                                                 - SBE_SEEPROM_ECC_PAD
                                                 - SBE_VERSION_SPACE_WITH_ECC;
 
+    const uint64_t SBE_SEEPROM_VERSION_READ_SIZE = 0x100; // 128 Bytes * 2  (256 decimal)
+    const uint64_t END_OF_SEEPROM_MINUS_READ_SIZE = 4*SBE_SEEPROM_SIZE_WO_ECC
+                                                  - SBE_SEEPROM_VERSION_READ_SIZE;
+
     // Used to read SBE Boot Side from processor
     // (PERV_SB_CS_SCOM 0x00050008 or PERV_SB_CS_FSI 0x2808)
     const uint64_t SBE_BOOT_SELECT_MASK = 0x0000400000000000;
@@ -478,7 +483,7 @@ namespace SBE
                                  sbeSeepromSide_t& o_bootSide);
 
     /**
-     * @brief Collects Version information from a specific SEEPROM
+     * @brief Collects Version information from a specific SEEPROM using I2C
      *
      * @param[in] i_target      Target processor to customize
      *
@@ -492,10 +497,24 @@ namespace SBE
      *
      * @return errlHndl_t    Error log handle on failure.
      */
-    errlHndl_t getSeepromSideVersion(TARGETING::Target* i_target,
+    errlHndl_t getSeepromSideVersionViaI2c(TARGETING::Target* i_target,
                                      EEPROM::eeprom_chip_types_t i_seepromSide,
                                      sbeSeepromVersionInfo_t& o_info,
                                      bool& o_seeprom_ver_ECC_fail);
+    /**
+     * @brief Collects Version information from a specific SEEPROM using PSU ChipOp
+     *
+     * @param[in] i_target        Target processor to customize
+     *
+     * @param[out] o_info         Struct containing the SBE Version Information
+     *
+     * @param[out] o_opSupported  output if sbe supports seeprom read chip op or not
+     *
+     * @return errlHndl_t    Error log handle on failure.
+     */
+    errlHndl_t getSeepromSideVersionViaChipOp(TARGETING::Target* i_target,
+                                     sbeSeepromVersionInfo_t& o_info,
+                                     bool& o_opSupported);
 
     /**
      * @brief Updates a specific SEEPROM
diff --git a/src/include/usr/sbeio/sbe_psudd.H b/src/include/usr/sbeio/sbe_psudd.H
index 5b2983c39..76603859f 100644
--- a/src/include/usr/sbeio/sbe_psudd.H
+++ b/src/include/usr/sbeio/sbe_psudd.H
@@ -102,6 +102,7 @@ class SbePsu
         //BYTE 7 options
         enum psuGenericMessageCommands
         {
+            SBE_PSU_READ_SEEPROM             = 0x03,
             SBE_PSU_SET_FFDC_ADDRESS         = 0x04,
             SBE_PSU_GENERIC_MSG_QUIESCE      = 0x05,
             SBE_CMD_CONTROL_SYSTEM_CONFIG    = 0x06,
@@ -226,6 +227,25 @@ class SbePsu
         * 0x4 - Reg 2 is non-reserved (read or write this reg)
         * 0x8 - Reg 3 is non-reserved (read or write this reg)
         */
+        enum psuReadSeepromMsgs
+        {
+            SBE_READ_SEEPROM_REQ_USED_REGS     = 0x07,
+            SBE_READ_SEEPROM_RSP_USED_REGS     = 0x01,
+        };
+
+        /**
+        * @brief non reserved word enums
+        *
+        * Shows which of the request and response msg registers are
+        * not reserved. Reserved registers do not need to be written
+        * or read.
+        *
+        * This is a 4 bit field:
+        * 0x1 - Reg 0 is non-reserved (read or write this reg)
+        * 0x2 - Reg 1 is non-reserved (read or write this reg)
+        * 0x4 - Reg 2 is non-reserved (read or write this reg)
+        * 0x8 - Reg 3 is non-reserved (read or write this reg)
+        */
         enum psuStashKeyAddrNonReservedMsgs
         {
             SBE_STASH_KEY_ADDR_REQ_USED_REGS     = 0x07,
@@ -413,6 +433,19 @@ class SbePsu
                 uint64_t cd7_setFFDCAddr_CommAddr; // mbxReg3
             } PACKED;
 
+            struct //readSeeprom
+            {
+                uint16_t cd7_readSeeprom_Reserved;
+                uint16_t cd7_readSeeprom_ControlFlags;
+                uint16_t cd7_readSeeprom_SeqId;
+                uint8_t  cd7_readSeeprom_CommandClass;
+                uint8_t  cd7_readSeeprom_Command;
+                uint32_t cd7_readSeeprom_SeepromOffset;   // mbxReg1
+                uint32_t cd7_readSeeprom_ReadSize;        // mbxReg1
+                uint64_t cd7_readSeeprom_DestinationAddr; // mbxReg2
+                uint64_t cd7_readSeeprom_MbxReg3Reserved; // mbxReg3
+            } PACKED;
+
             psuCommand(uint16_t i_controlFlags, //Mbx Reg 0 input
                        uint8_t  i_commandClass, //Mbx Reg 0 input
                        uint8_t  i_command) :    //Mbx Reg 0 input
diff --git a/src/include/usr/sbeio/sbeioif.H b/src/include/usr/sbeio/sbeioif.H
index a951fe4a4..12881c939 100644
--- a/src/include/usr/sbeio/sbeioif.H
+++ b/src/include/usr/sbeio/sbeioif.H
@@ -285,6 +285,28 @@ namespace SBEIO
                                     uint64_t i_dataSize,
                                     const char * i_hwpName);
 
+    /**
+    * @brief Sends a PSU chipOp to request Seeprom read from SBE
+    *
+    * @param[in]  i_target         Target with SBE to send read request to
+    * @param[in]  i_seepromOffset  Offset in the seeprom image where we want
+    *                              to start copying from (ignores ECC)
+    * @param[in]  i_readSize       Amount of bytes we want to copy (ignores ECC)
+    * @param[in]  i_destAddr       Address that hostboot has prepared which the
+    *                              sbe will write too
+    * @param[out] o_opSupported    Bool which tells us if the sbe supports the
+    *                              chipOp or not
+    *
+    * @return errlHndl_t Error log handle on failure.
+    *
+    */
+    errlHndl_t sendPsuReadSeeprom(TARGETING::Target * i_target,
+                                  uint32_t i_seepromOffset,
+                                  uint32_t i_readSize,
+                                  uint64_t i_destAddr,
+                                  bool   & o_opSupported);
+
+
 
 } //end namespace SBEIO