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| author | Mike Baiocchi <mbaiocch@us.ibm.com> | 2016-11-04 11:30:17 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2017-03-08 11:06:34 -0500 |
| commit | c3d233bbaf7a2f274147d16edbc080bae0ffd714 (patch) | |
| tree | 8058bc8e764135eecc21cdcd1177814dd4e180c8 /src/include/usr/intr | |
| parent | 1301e43641f7d3f315a0abc8112fa88927c9fa9a (diff) | |
| download | talos-hostboot-c3d233bbaf7a2f274147d16edbc080bae0ffd714.tar.gz talos-hostboot-c3d233bbaf7a2f274147d16edbc080bae0ffd714.zip | |
Hostboot Base TCE Support
This commit adds the base support for hostboot to enable/disable the
use of TCEs. It allows for the creation and managment of a TCE table
and also initializes the P9 processors to use this table.
Change-Id: Idb40f9df5a90d8b7e87b2f5b745cbe7e66109df2
RTC:145071
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32562
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/include/usr/intr')
| -rw-r--r-- | src/include/usr/intr/interrupt.H | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/src/include/usr/intr/interrupt.H b/src/include/usr/intr/interrupt.H index 38d0fa473..aa0e8cdab 100644 --- a/src/include/usr/intr/interrupt.H +++ b/src/include/usr/intr/interrupt.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2016 */ +/* Contributors Listed Below - COPYRIGHT 2011,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -144,6 +144,34 @@ namespace INTR MSG_INTR_ENABLE_PSI_INTR, //!< Enable PSIHB Interrupts }; + + //Derived from 15.8 PSIHB Software Interfaces of the p9_cn_psi_hb_regs.pdf + // (splintered off from the P9 Pervasive Workbook) + // -- shared with other code (like utiltce) + struct PSIHB_SW_INTERFACES_t + { + uint64_t psihbbar; //Host Bridge Base Address Register - 0x0 + uint64_t fspbar; //FSP Base Address Register - 0x8 + uint64_t fspmmr; //FSP Memory Mask Register - 0x10 + uint64_t tceaddr; //TAR - TCE Address Register - 0x18 + uint64_t psihbcr; //PSI Host Bridge Ctrl/Status Register - 0x20 + uint64_t psisemr; //PSIHB Status / Error Mask Register - 0x28 + uint64_t reserved2; //Unused / Reserved + uint64_t phbdsr; //PSIHB Debug Setting register - 0x38 + uint64_t phbscr; //PSI Host Bridge Ctrl/Status Register - 0x40 + uint64_t phbccr; //PSI Host Bridge clear ctl/status reg - 0x48 + uint64_t dmaupaddr; //DMA Upper Address Register - 0x50 + uint64_t icr; //Interrupt Control Register - 0x58 + uint64_t esbciaddr; //ESB CI Base Address - 0x60 + uint64_t esbnotifyaddr; //ESB Notification Address - 0x68 + uint64_t ivtofforig; //IVT Offset Origin Register - 0x70 + uint64_t lsiintlevel; //LSI Intr Level Register (lab use - 0x78 + uint64_t lsiintstatus; //LSI Interrupt Status register - 0x80 + uint64_t reserved3; //Unused / Reserved - 0x88 + uint64_t phbsecure; //PSI Host Bridge Secure Control reg - 0x90 + }; + + /** * Register a message queue for an interrupt type * @param[in] i_msgQ The message queue |
