Support HB running in SMF

Support SMF for P9N/P9C.  Lots of minor tweaks to make this
work, but the biggest is to run userspace in problem state
This is needed because for SMF Hostboot will need to run in S=1,
HV=0,PR=1 (and kernel in S=1, HV=1, PR=0)

This commit makes P9 HB userpsace run in HV=0 PR=1 and kernel in
HV=1, PR=0.

Change-Id: Ia4771df5e8858c6b7ae54b0746e62b283afb4bc4
RTC: 197243
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/50530
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 40 insertions, 33 deletions

diff --git a/src/include/kernel/cpumgr.H b/src/include/kernel/cpumgr.H
index 7c6421cd6..f8daf5ab3 100644
--- a/src/include/kernel/cpumgr.H
+++ b/src/include/kernel/cpumgr.H
@@ -30,6 +30,46 @@
 #include <kernel/barrier.H>
 #include <kernel/idebug.H>
 
+/** Desired value for MSR after wakeup.
+ *
+ *  bit 0 - 64 bit mode.
+ *  bit 3 - Hypervisor mode.
+ *  bit 51 - Machine-check enable
+ */
+extern const uint64_t WAKEUP_MSR_VALUE;
+
+/** Desired value for LPCR after wakeup.
+ *
+ *  bit 48 - Wake-up from hyp doorbell
+ *  bit 49 - Wake-up from external interrupt.
+ *  bit 50 - Wake-up from decrementer.
+ *  bit 51 - Wake-up from machine check.
+ *  bit 60 - LPES(0) = 1 (see ISA).
+ *  bit 61 - LPES(1) = 0 (P8 RFC02204 forces to 0)
+ *  bit 62 - HVICE - Hypervisor Virt Interrupt Conditionally Enable
+ */
+extern const uint64_t WAKEUP_LPCR_VALUE;
+
+/** Desired value for RPR after wakeup.
+ *
+ *      Priority     Us    PHYP
+ *      Very Low      0      0
+ *      Low           1      1    <--- hostboot "low"
+ *      Med Low       3      3
+ *      Med          32      7    <--- hostboot "high"
+ *      Med High     33     15
+ *      High         34     31
+ *      Very High    63     63
+ */
+extern const uint64_t WAKEUP_RPR_VALUE;
+
+/** The mask to isolate SMF enabled value
+ *
+ * bit 41 - SMF (Ultravisor) enable
+ *
+ */
+extern const uint64_t MSR_SMF_MASK;
+
 class CpuManager
 {
     public:
@@ -159,39 +199,6 @@ class CpuManager
          */
         static void critAssert(uint64_t i_failAddr);
 
-        /** Desired value for MSR after wakeup.
-         *
-         *  bit 0 - 64 bit mode.
-         *  bit 3 - Hypervisor mode.
-         *  bit 51 - Machine-check enable
-         */
-        static const uint64_t WAKEUP_MSR_VALUE =    0x9000000000001000;
-
-        /** Desired value for LPCR after wakeup.
-         *
-         *  bit 48 - Wake-up from hyp doorbell
-         *  bit 49 - Wake-up from external interrupt.
-         *  bit 50 - Wake-up from decrementer.
-         *  bit 51 - Wake-up from machine check.
-         *  bit 60 - LPES(0) = 1 (see ISA).
-         *  bit 61 - LPES(1) = 0 (P8 RFC02204 forces to 0)
-         *  bit 62 - HVICE - Hypervisor Virt Interrupt Conditionally Enable
-         */
-        static const uint64_t WAKEUP_LPCR_VALUE =   0x000000000000F00A;
-
-        /** Desired value for RPR after wakeup.
-         *
-         *      Priority     Us    PHYP
-         *      Very Low      0      0
-         *      Low           1      1    <--- hostboot "low"
-         *      Med Low       3      3
-         *      Med          32      7    <--- hostboot "high"
-         *      Med High     33     15
-         *      High         34     31
-         *      Very High    63     63
-         */
-        static const uint64_t WAKEUP_RPR_VALUE =    0x0001032021223F;
-
         /** @fn startCPU
          *  Starts the requested CPU. Default of -1 implies current CPU.
          */