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| author | Stephen Glancy <sglancy@us.ibm.com> | 2019-02-22 16:40:33 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-03-13 10:32:07 -0500 |
| commit | 2b943a5ba24f028f24fde19dac5f818280f75829 (patch) | |
| tree | 49ee1eb2e77d0ee701d318e45de4d374cf6181ec /src/import | |
| parent | c368037cb36e1e2907c96bb9be66a5cc80542b6f (diff) | |
| download | talos-hostboot-2b943a5ba24f028f24fde19dac5f818280f75829.tar.gz talos-hostboot-2b943a5ba24f028f24fde19dac5f818280f75829.zip | |
Fixes MPR read ODT values
Change-Id: Iba91d04496a020f209c9e804299ea057306438a1
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72375
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72388
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H index 613b20d46..cce5beef2 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H @@ -642,11 +642,38 @@ inline fapi2::ReturnCode mpr_read( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& const uint64_t i_mpr_loc, const uint64_t i_rank) { + // We don't know our coarse adjust at this point, so send the ODT two cycles early and hold it two cycles late + // Two is the maximum coarse adjust for the LRDIMM + constexpr uint64_t SAFETY_CYCLES = 2; + constexpr uint64_t ODT_CYCLE_LEN = 5 + SAFETY_CYCLES * 2; + mss::ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); + uint8_t l_cl = 0; + uint8_t l_cwl = 0; + uint64_t l_delay = 0; + uint8_t l_rd_odt[MAX_RANK_PER_DIMM] = {}; + const auto l_dimm_rank = mss::index(i_rank); + FAPI_TRY( mss::eff_dram_cwl(l_mca, l_cwl) ); + FAPI_TRY( mss::eff_dram_cl(l_mca, l_cl) ); + l_delay = l_cl - l_cwl - SAFETY_CYCLES; + + FAPI_TRY(mss::eff_odt_rd(i_target, &l_rd_odt[0])); FAPI_TRY( ddr4::mpr_read<fapi2::TARGET_TYPE_MCBIST>(i_target, i_mpr_loc, i_rank, l_program.iv_instructions)); + + l_program.iv_instructions[0].arr1.template insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, + MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(l_delay); + + // Holds the RD ODT's for 5 cycles + { + const auto l_ccs_value = mss::ccs::convert_odt_attr_to_ccs<fapi2::TARGET_TYPE_MCBIST>(fapi2::buffer<uint8_t> + (l_rd_odt[l_dimm_rank])); + auto l_odt = mss::ccs::odt_command<fapi2::TARGET_TYPE_MCBIST>(l_ccs_value, ODT_CYCLE_LEN); + l_program.iv_instructions.push_back(l_odt); + } + FAPI_TRY( ccs::execute(l_mcbist, l_program, l_mca) ); |
