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author | Andre A. Marin <aamarin@us.ibm.com> | 2019-03-05 22:53:02 -0600 |
---|---|---|
committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-03-13 10:31:49 -0500 |
commit | c368037cb36e1e2907c96bb9be66a5cc80542b6f (patch) | |
tree | d6faef69a84e82133173439d2ac667f0b8703b79 /src/import | |
parent | 5618f2f2b4321a8ccaf2e8603ff1271a56278dae (diff) | |
download | talos-hostboot-c368037cb36e1e2907c96bb9be66a5cc80542b6f.tar.gz talos-hostboot-c368037cb36e1e2907c96bb9be66a5cc80542b6f.zip |
Update phy_pharams structure, tests, and exp attrs
Change-Id: Ie84463e9497bf53d8cd13b14526be93d9de95506
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72070
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72086
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import')
3 files changed, 898 insertions, 532 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C index c2d4fa1e6..94d67589d 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C @@ -73,16 +73,14 @@ fapi2::ReturnCode setup_phy_params(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C for (const auto l_port : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) { fapi2::ReturnCode l_rc; - - // Create an object - auto l_set_phy_params = phy_params(l_port, l_rc); - FAPI_TRY(l_rc, "Unable to set parameters for target %s", mss::c_str(i_target)); + const phy_params l_set_phy_params(l_port, l_rc); + FAPI_TRY(l_rc, "Unable to instantiate phy_params for target %s", mss::c_str(i_target)); // Set the params by fetching them from the attributes - FAPI_TRY(l_set_phy_params.setup_DimmType(l_port, o_phy_params)); - FAPI_TRY(l_set_phy_params.setup_CsPresent(l_port, o_phy_params)); - FAPI_TRY(l_set_phy_params.setup_DramDataWidth(l_port, o_phy_params)); - FAPI_TRY(l_set_phy_params.setup_Height3DS(l_port, o_phy_params)); + FAPI_TRY(l_set_phy_params.setup_DimmType(o_phy_params)); + FAPI_TRY(l_set_phy_params.setup_CsPresent(o_phy_params)); + FAPI_TRY(l_set_phy_params.setup_DramDataWidth(o_phy_params)); + FAPI_TRY(l_set_phy_params.setup_Height3DS(o_phy_params)); FAPI_TRY(l_set_phy_params.set_ActiveDBYTE(o_phy_params)); FAPI_TRY(l_set_phy_params.set_ActiveNibble(o_phy_params)); FAPI_TRY(l_set_phy_params.set_AddrMirror(o_phy_params)); diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H index 7ab0b0c59..7ffe531ce 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H @@ -149,47 +149,47 @@ struct phy_params_t /// Declare variables to be used /// uint8_t iv_dimm_type[MAX_DIMM_PER_PORT]; - uint8_t iv_chip_select; + uint16_t iv_chip_select; uint8_t iv_dram_data_width[MAX_DIMM_PER_PORT]; - uint8_t iv_height_3DS; - uint16_t iv_dbyte_macro; - uint32_t iv_nibble; + uint16_t iv_height_3DS; + uint16_t iv_dbyte_macro[MAX_DIMM_PER_PORT]; + uint32_t iv_nibble[MAX_DIMM_PER_PORT]; uint8_t iv_addr_mirror[MAX_DIMM_PER_PORT]; uint8_t iv_column_width[MAX_DIMM_PER_PORT]; uint8_t iv_row_width[MAX_DIMM_PER_PORT]; uint32_t iv_spdcl_support; - uint8_t iv_taa_min; - uint8_t iv_rank4_mode; - uint8_t iv_ddp_compatible; - uint8_t iv_tsv8h; - uint8_t iv_mram_support; - uint8_t iv_num_pstate; + uint16_t iv_taa_min; + uint8_t iv_rank4_mode[MAX_DIMM_PER_PORT]; + uint8_t iv_ddp_compatible[MAX_DIMM_PER_PORT]; + uint8_t iv_tsv8h[MAX_DIMM_PER_PORT]; + uint8_t iv_mram_support[MAX_DIMM_PER_PORT]; + uint8_t iv_num_pstate[MAX_DIMM_PER_PORT]; uint64_t iv_frequency; - uint8_t iv_odt_impedance; - uint8_t iv_drv_impedance_pu[MSDG_MAX_PSTATE]; - uint8_t iv_drv_impedance_pd[MSDG_MAX_PSTATE]; - uint8_t iv_slew_rate[MSDG_MAX_PSTATE]; - uint8_t iv_atx_impedance; - uint8_t iv_atx_slew_rate; - uint8_t iv_ck_tx_impedance; - uint8_t iv_ck_tx_slew_rate; - uint8_t iv_alert_odt_impedance; + uint8_t iv_odt_impedance[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_drv_impedance_pu[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_drv_impedance_pd[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_slew_rate[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_atx_impedance[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_atx_slew_rate[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_ck_tx_impedance[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_ck_tx_slew_rate[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_alert_odt_impedance[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_dram_rtt_nom[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_dram_rtt_wr[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_dram_rtt_park[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_dram_dic[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; - uint8_t iv_dram_preamble; - uint8_t iv_phy_equalization; + uint8_t iv_dram_preamble[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_phy_equalization[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_init_vref_dq; uint16_t iv_init_phy_vref; - uint8_t iv_odt_wr_map_cs; - uint8_t iv_odt_rd_map_cs; - uint8_t iv_geardown_mode[MAX_DIMM_PER_PORT]; + uint8_t iv_odt_wr_map_cs[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_odt_rd_map_cs[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_geardown_mode[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_ca_latency_adder[MAX_DIMM_PER_PORT]; uint8_t iv_bist_cal_mode[MAX_DIMM_PER_PORT]; uint8_t iv_bist_ca_parity_latency[MAX_DIMM_PER_PORT]; - uint8_t iv_rcd_dic; - uint8_t iv_rcd_voltage_ctrl; + uint16_t iv_rcd_dic; + uint16_t iv_rcd_voltage_ctrl; uint8_t iv_f0rc7x[MAX_DIMM_PER_PORT]; uint8_t iv_f1rc00[MAX_DIMM_PER_PORT]; uint16_t iv_rcd_slew_rate; @@ -205,82 +205,90 @@ struct phy_params_t class phy_params { private: + + fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> iv_target; phy_params_t iv_params; public: - /// - /// @brief Delete default constructor - /// + + /// default constructor is deleted phy_params() = delete; /// /// @brief Constructor to fetch attributes /// /// @brief fetch the attributes and initialize it to the params - /// @param[in] i_port the fapi2 target + /// @param[in] i_target the fapi2 target /// @param[in,out] o_rc the fapi2 output /// - phy_params(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port, fapi2::ReturnCode o_rc) + phy_params(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + fapi2::ReturnCode o_rc): + iv_target(i_target) { // Fetch attributes and populate the member variables - FAPI_TRY(mss::attr::get_dimm_type(i_port, iv_params.iv_dimm_type)); - FAPI_TRY(mss::attr::get_exp_chip_select(i_port, iv_params.iv_chip_select)); - FAPI_TRY(mss::attr::get_dram_width(i_port, iv_params.iv_dram_data_width)); - FAPI_TRY(mss::attr::get_3ds_height(i_port, iv_params.iv_height_3DS)); - FAPI_TRY(mss::attr::get_byte_enables(i_port, iv_params.iv_dbyte_macro)); - FAPI_TRY(mss::attr::get_nibble_enables(i_port, iv_params.iv_nibble)); - FAPI_TRY(mss::attr::get_exp_dram_address_mirroring(i_port, iv_params.iv_addr_mirror)); - FAPI_TRY(mss::attr::get_dram_column_bits(i_port, iv_params.iv_column_width)); - FAPI_TRY(mss::attr::get_dram_row_bits(i_port, iv_params.iv_row_width)); - FAPI_TRY(mss::attr::get_exp_spd_cl(i_port, iv_params.iv_spdcl_support)); - FAPI_TRY(mss::attr::get_taa_min(i_port, iv_params.iv_taa_min)); - FAPI_TRY(mss::attr::get_rank4_mode(i_port, iv_params.iv_rank4_mode)); - FAPI_TRY(mss::attr::get_ddp_compatibility(i_port, iv_params.iv_ddp_compatible)); - FAPI_TRY(mss::attr::get_tsv8h_support(i_port, iv_params.iv_tsv8h)); - FAPI_TRY(mss::attr::get_mram_support(i_port, iv_params.iv_mram_support)); - FAPI_TRY(mss::attr::get_pstates(i_port, iv_params.iv_num_pstate)); - FAPI_TRY(mss::attr::get_freq(i_port, iv_params.iv_frequency)); - FAPI_TRY(mss::attr::get_si_mc_drv_imp_cntl(i_port, iv_params.iv_odt_impedance)); - FAPI_TRY(mss::attr::get_si_mc_drv_imp_dq_dqs_pull_up(i_port, iv_params.iv_drv_impedance_pu)); - FAPI_TRY(mss::attr::get_si_mc_drv_imp_dq_dqs_pull_down(i_port, iv_params.iv_drv_impedance_pd)); - FAPI_TRY(mss::attr::get_si_mc_drv_slew_rate_dq_dqs(i_port, iv_params.iv_slew_rate)); - FAPI_TRY(mss::attr::get_si_mc_drv_imp_cmd_addr(i_port, iv_params.iv_atx_impedance)); - FAPI_TRY(mss::attr::get_si_mc_drv_slew_rate_cmd_addr(i_port, iv_params.iv_atx_slew_rate)); - FAPI_TRY(mss::attr::get_si_mc_drv_imp_clk(i_port, iv_params.iv_ck_tx_impedance)); - FAPI_TRY(mss::attr::get_si_mc_drv_slew_rate_clk(i_port, iv_params.iv_ck_tx_slew_rate)); - FAPI_TRY(mss::attr::get_si_mc_rcv_imp_alert_n(i_port, iv_params.iv_alert_odt_impedance)); - FAPI_TRY(mss::attr::get_si_dram_rtt_nom(i_port, iv_params.iv_dram_rtt_nom)); - FAPI_TRY(mss::attr::get_si_dram_rtt_wr(i_port, iv_params.iv_dram_rtt_wr)); - FAPI_TRY(mss::attr::get_si_dram_rtt_park(i_port, iv_params.iv_dram_rtt_park)); - FAPI_TRY(mss::attr::get_si_dram_drv_imp_dq_dqs(i_port, iv_params.iv_dram_dic)); - FAPI_TRY(mss::attr::get_si_dram_preamble(i_port, iv_params.iv_dram_preamble)); - FAPI_TRY(mss::attr::get_exp_phy_equalization(i_port, iv_params.iv_phy_equalization)); - FAPI_TRY(mss::attr::get_exp_init_vref_dq(i_port, iv_params.iv_init_vref_dq)); - FAPI_TRY(mss::attr::get_exp_init_phy_vref(i_port, iv_params.iv_init_phy_vref)); - FAPI_TRY(mss::attr::get_exp_odt_map_cs_wr(i_port, iv_params.iv_odt_wr_map_cs)); - FAPI_TRY(mss::attr::get_exp_odt_map_cs_rd(i_port, iv_params.iv_odt_rd_map_cs)); - FAPI_TRY(mss::attr::get_geardown_mode(i_port, iv_params.iv_geardown_mode)); - FAPI_TRY(mss::attr::get_dimm_ddr4_f0rc0f(i_port, iv_params.iv_ca_latency_adder)); - FAPI_TRY(mss::attr::get_cs_cmd_latency(i_port, iv_params.iv_bist_cal_mode)); - FAPI_TRY(mss::attr::get_ca_parity_latency(i_port, iv_params.iv_bist_ca_parity_latency)); - FAPI_TRY(mss::attr::get_exp_rcd_dic(i_port, iv_params.iv_rcd_dic)); - FAPI_TRY(mss::attr::get_exp_rcd_voltage_ctrl(i_port, iv_params.iv_rcd_voltage_ctrl)); - FAPI_TRY(mss::attr::get_dimm_ddr4_f0rc7x(i_port, iv_params.iv_f0rc7x)); - FAPI_TRY(mss::attr::get_dimm_ddr4_f1rc00(i_port, iv_params.iv_f1rc00)); - FAPI_TRY(mss::attr::get_exp_rcd_slew_rate(i_port, iv_params.iv_rcd_slew_rate)); - FAPI_TRY(mss::attr::get_exp_firmware_emulation_mode(i_port, iv_params.iv_firmware_mode)); + FAPI_TRY(mss::attr::get_dimm_type(i_target, iv_params.iv_dimm_type)); + FAPI_TRY(mss::attr::get_exp_cs_present(i_target, iv_params.iv_chip_select)); + FAPI_TRY(mss::attr::get_dram_width(i_target, iv_params.iv_dram_data_width)); + FAPI_TRY(mss::attr::get_exp_3ds_height(i_target, iv_params.iv_height_3DS)); + FAPI_TRY(mss::attr::get_byte_enables(i_target, iv_params.iv_dbyte_macro)); + FAPI_TRY(mss::attr::get_nibble_enables(i_target, iv_params.iv_nibble)); + FAPI_TRY(mss::attr::get_exp_dram_address_mirroring(i_target, iv_params.iv_addr_mirror)); + FAPI_TRY(mss::attr::get_dram_column_bits(i_target, iv_params.iv_column_width)); + FAPI_TRY(mss::attr::get_dram_row_bits(i_target, iv_params.iv_row_width)); + FAPI_TRY(mss::attr::get_exp_spd_cl_supported(i_target, iv_params.iv_spdcl_support)); + FAPI_TRY(mss::attr::get_exp_spd_taa_min(i_target, iv_params.iv_taa_min)); + FAPI_TRY(mss::attr::get_four_rank_mode(i_target, iv_params.iv_rank4_mode)); + FAPI_TRY(mss::attr::get_ddp_compatibility(i_target, iv_params.iv_ddp_compatible)); + FAPI_TRY(mss::attr::get_tsv_8h_support(i_target, iv_params.iv_tsv8h)); + FAPI_TRY(mss::attr::get_mram_support(i_target, iv_params.iv_mram_support)); + FAPI_TRY(mss::attr::get_pstates(i_target, iv_params.iv_num_pstate)); + FAPI_TRY(mss::attr::get_freq(i_target, iv_params.iv_frequency)); + FAPI_TRY(mss::attr::get_si_mc_rcv_imp_dq_dqs(i_target, iv_params.iv_odt_impedance)); + FAPI_TRY(mss::attr::get_si_mc_drv_imp_dq_dqs_pull_up(i_target, iv_params.iv_drv_impedance_pu)); + FAPI_TRY(mss::attr::get_si_mc_drv_imp_dq_dqs_pull_down(i_target, iv_params.iv_drv_impedance_pd)); + FAPI_TRY(mss::attr::get_si_mc_drv_slew_rate_dq_dqs(i_target, iv_params.iv_slew_rate)); + FAPI_TRY(mss::attr::get_si_mc_drv_imp_cmd_addr(i_target, iv_params.iv_atx_impedance)); + FAPI_TRY(mss::attr::get_si_mc_drv_slew_rate_cmd_addr(i_target, iv_params.iv_atx_slew_rate)); + FAPI_TRY(mss::attr::get_si_mc_drv_imp_clk(i_target, iv_params.iv_ck_tx_impedance)); + FAPI_TRY(mss::attr::get_si_mc_drv_slew_rate_clk(i_target, iv_params.iv_ck_tx_slew_rate)); + FAPI_TRY(mss::attr::get_si_mc_rcv_imp_alert_n(i_target, iv_params.iv_alert_odt_impedance)); + FAPI_TRY(mss::attr::get_si_dram_rtt_nom(i_target, iv_params.iv_dram_rtt_nom)); + FAPI_TRY(mss::attr::get_si_dram_rtt_wr(i_target, iv_params.iv_dram_rtt_wr)); + FAPI_TRY(mss::attr::get_si_dram_rtt_park(i_target, iv_params.iv_dram_rtt_park)); + FAPI_TRY(mss::attr::get_si_dram_drv_imp_dq_dqs(i_target, iv_params.iv_dram_dic)); + FAPI_TRY(mss::attr::get_si_dram_preamble(i_target, iv_params.iv_dram_preamble)); + FAPI_TRY(mss::attr::get_si_mc_rcv_eq_dq_dqs(i_target, iv_params.iv_phy_equalization)); + FAPI_TRY(mss::attr::get_exp_init_vref_dq(i_target, iv_params.iv_init_vref_dq)); + FAPI_TRY(mss::attr::get_exp_init_phy_vref(i_target, iv_params.iv_init_phy_vref)); + FAPI_TRY(mss::attr::get_si_odt_wr(i_target, iv_params.iv_odt_wr_map_cs)); + FAPI_TRY(mss::attr::get_si_odt_rd(i_target, iv_params.iv_odt_rd_map_cs)); + FAPI_TRY(mss::attr::get_si_geardown_mode(i_target, iv_params.iv_geardown_mode)); + FAPI_TRY(mss::attr::get_dimm_ddr4_f0rc0f(i_target, iv_params.iv_ca_latency_adder)); + FAPI_TRY(mss::attr::get_cs_cmd_latency(i_target, iv_params.iv_bist_cal_mode)); + FAPI_TRY(mss::attr::get_ca_parity_latency(i_target, iv_params.iv_bist_ca_parity_latency)); + FAPI_TRY(mss::attr::get_exp_rcd_dic(i_target, iv_params.iv_rcd_dic)); + FAPI_TRY(mss::attr::get_exp_rcd_voltage_ctrl(i_target, iv_params.iv_rcd_voltage_ctrl)); + FAPI_TRY(mss::attr::get_dimm_ddr4_f0rc7x(i_target, iv_params.iv_f0rc7x)); + FAPI_TRY(mss::attr::get_dimm_ddr4_f1rc00(i_target, iv_params.iv_f1rc00)); + FAPI_TRY(mss::attr::get_exp_rcd_slew_rate(i_target, iv_params.iv_rcd_slew_rate)); + FAPI_TRY(mss::attr::get_exp_firmware_emulation_mode(i_target, iv_params.iv_firmware_mode)); fapi_try_exit: o_rc = fapi2::current_err; } /// - /// @brief Constructor for UTs + /// @brief Constructor /// - /// @brief Set params as per the value initialized for the UT - /// @param[in] i_phy_params - data struct for UT + /// @brief Set params as per the value initialized (useful for testing) + /// @param[in] i_target the fapi2 target + /// @param[in] i_phy_params explorer specific data structure /// - phy_params(const phy_params_t& i_phy_params): iv_params(i_phy_params) {} + phy_params(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + const phy_params_t& i_phy_params): + iv_target(i_target), + iv_params(i_phy_params) + {} /// /// @brief Destructor @@ -289,12 +297,10 @@ class phy_params /// /// @brief user_input_msdg structure setup for parameter DimmType - /// @param[in] i_port the fapi2 target /// @param[in,out] io_phy_params the phy params data struct /// @return FAPI2_RC_SUCCESS iff okay /// - fapi2::ReturnCode setup_DimmType(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port, - user_input_msdg& io_phy_params) const + fapi2::ReturnCode setup_DimmType(user_input_msdg& io_phy_params) const { switch (iv_params.iv_dimm_type[0]) { @@ -311,14 +317,14 @@ class phy_params break; default: - const auto& l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(i_port); + const auto& l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(iv_target); FAPI_ASSERT(false, fapi2::MSS_EXP_DRAMINIT_UNSUPPORTED_DIMM_TYPE(). set_OCMB_TARGET(l_ocmb). - set_PORT(i_port). + set_PORT(iv_target). set_TYPE(iv_params.iv_dimm_type[0]), "%s DIMM0 is not a supported DIMM type (%d)", - mss::c_str(i_port), iv_params.iv_dimm_type[0]); + mss::c_str(iv_target), iv_params.iv_dimm_type[0]); break; } @@ -330,12 +336,10 @@ class phy_params /// /// @brief user_input_msdg structure setup for parameter CsPresent - /// @param[in] i_port the fapi2 target /// @param[in,out] io_phy_params the phy params data struct /// @return FAPI2_RC_SUCCESS iff okay /// - fapi2::ReturnCode setup_CsPresent(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port, - user_input_msdg& io_phy_params) const + fapi2::ReturnCode setup_CsPresent(user_input_msdg& io_phy_params) const { io_phy_params.CsPresent = iv_params.iv_chip_select; return fapi2::FAPI2_RC_SUCCESS; @@ -343,12 +347,10 @@ class phy_params /// /// @brief user_input_msdg structure setup for parameter DramDataWidth - /// @param[in] i_port the fapi2 target /// @param[in,out] io_phy_params the phy params data struct /// @return FAPI2_RC_SUCCESS iff okay /// - fapi2::ReturnCode setup_DramDataWidth(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port, - user_input_msdg& io_phy_params) const + fapi2::ReturnCode setup_DramDataWidth(user_input_msdg& io_phy_params) const { switch (iv_params.iv_dram_data_width[0]) { @@ -365,14 +367,14 @@ class phy_params break; default: - const auto& l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(i_port); + const auto& l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(iv_target); FAPI_ASSERT(false, fapi2::MSS_EXP_DRAMINIT_UNSUPPORTED_DRAM_WIDTH(). set_OCMB_TARGET(l_ocmb). - set_PORT(i_port). + set_PORT(iv_target). set_DATA_WIDTH(iv_params.iv_dram_data_width[0]), "%s DRAM Data Width of DIMM0 is not a supported (%d)", - mss::c_str(i_port), iv_params.iv_dram_data_width[0]); + mss::c_str(iv_target), iv_params.iv_dram_data_width[0]); break; } @@ -384,40 +386,38 @@ class phy_params /// /// @brief user_input_msdg structure setup for parameter Height3DS - /// @param[in] i_port the fapi2 target /// @param[in,out] io_phy_params the phy params data struct /// @return FAPI2_RC_SUCCESS iff okay /// - fapi2::ReturnCode setup_Height3DS(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port, - user_input_msdg& io_phy_params) const + fapi2::ReturnCode setup_Height3DS(user_input_msdg& io_phy_params) const { switch (iv_params.iv_height_3DS) { - case fapi2::ENUM_ATTR_MEM_EFF_3DS_HEIGHT_PLANAR: + case fapi2::ENUM_ATTR_MEM_EXP_3DS_HEIGHT_PLANAR: io_phy_params.Height3DS = MSDG_PLANAR; break; - case fapi2::ENUM_ATTR_MEM_EFF_3DS_HEIGHT_H2: + case fapi2::ENUM_ATTR_MEM_EXP_3DS_HEIGHT_H2: io_phy_params.Height3DS = MSDG_H2; break; - case fapi2::ENUM_ATTR_MEM_EFF_3DS_HEIGHT_H4: + case fapi2::ENUM_ATTR_MEM_EXP_3DS_HEIGHT_H4: io_phy_params.Height3DS = MSDG_H4; break; - case fapi2::ENUM_ATTR_MEM_EFF_3DS_HEIGHT_H8: + case fapi2::ENUM_ATTR_MEM_EXP_3DS_HEIGHT_H8: io_phy_params.Height3DS = MSDG_H8; break; default: - const auto& l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(i_port); + const auto l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(iv_target); FAPI_ASSERT(false, fapi2::MSS_EXP_DRAMINIT_UNSUPPORTED_3DS_HEIGHT(). set_OCMB_TARGET(l_ocmb). - set_PORT(i_port). + set_PORT(iv_target). set_HEIGHT(iv_params.iv_height_3DS), "%s 3DS Height is not a supported (%d)", - mss::c_str(i_port), iv_params.iv_height_3DS); + mss::c_str(iv_target), iv_params.iv_height_3DS); break; } @@ -434,7 +434,8 @@ class phy_params /// fapi2::ReturnCode set_ActiveDBYTE(user_input_msdg& io_phy_params) const { - io_phy_params.ActiveDBYTE = iv_params.iv_dbyte_macro; + // TK add checks for same DIMM/RANK info + io_phy_params.ActiveDBYTE = iv_params.iv_dbyte_macro[0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -445,7 +446,7 @@ class phy_params /// fapi2::ReturnCode set_ActiveNibble(user_input_msdg& io_phy_params) const { - io_phy_params.ActiveNibble = iv_params.iv_nibble; + io_phy_params.ActiveNibble = iv_params.iv_nibble[0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -511,7 +512,7 @@ class phy_params /// fapi2::ReturnCode set_Rank4Mode(user_input_msdg& io_phy_params) const { - io_phy_params.Rank4Mode = iv_params.iv_rank4_mode; + io_phy_params.Rank4Mode = iv_params.iv_rank4_mode[0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -522,7 +523,7 @@ class phy_params /// fapi2::ReturnCode set_DDPCompatible(user_input_msdg& io_phy_params) const { - io_phy_params.DDPCompatible = iv_params.iv_ddp_compatible; + io_phy_params.DDPCompatible = iv_params.iv_ddp_compatible[0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -533,7 +534,7 @@ class phy_params /// fapi2::ReturnCode set_TSV8HSupport(user_input_msdg& io_phy_params) const { - io_phy_params.TSV8HSupport = iv_params.iv_tsv8h; + io_phy_params.TSV8HSupport = iv_params.iv_tsv8h[0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -544,7 +545,7 @@ class phy_params /// fapi2::ReturnCode set_MRAMSupport(user_input_msdg& io_phy_params) const { - io_phy_params.MRAMSupport = iv_params.iv_mram_support; + io_phy_params.MRAMSupport = iv_params.iv_mram_support[0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -555,7 +556,7 @@ class phy_params /// fapi2::ReturnCode set_NumPStates(user_input_msdg& io_phy_params) const { - io_phy_params.NumPStates = iv_params.iv_num_pstate; + io_phy_params.NumPStates = iv_params.iv_num_pstate[0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -577,7 +578,7 @@ class phy_params /// fapi2::ReturnCode set_PhyOdtImpedance(user_input_msdg& io_phy_params) const { - io_phy_params.PhyOdtImpedance[0] = iv_params.iv_odt_impedance; + io_phy_params.PhyOdtImpedance[0] = iv_params.iv_odt_impedance[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -588,7 +589,7 @@ class phy_params /// fapi2::ReturnCode set_PhyDrvImpedancePU(user_input_msdg& io_phy_params) const { - io_phy_params.PhyDrvImpedancePU[0] = iv_params.iv_drv_impedance_pu[0]; + io_phy_params.PhyDrvImpedancePU[0] = iv_params.iv_drv_impedance_pu[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -599,7 +600,7 @@ class phy_params /// fapi2::ReturnCode set_PhyDrvImpedancePD(user_input_msdg& io_phy_params) const { - io_phy_params.PhyDrvImpedancePD[0] = iv_params.iv_drv_impedance_pd[0]; + io_phy_params.PhyDrvImpedancePD[0] = iv_params.iv_drv_impedance_pd[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -610,7 +611,7 @@ class phy_params /// fapi2::ReturnCode set_PhySlewRate(user_input_msdg& io_phy_params) const { - io_phy_params.PhySlewRate[0] = iv_params.iv_slew_rate[0]; + io_phy_params.PhySlewRate[0] = iv_params.iv_slew_rate[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -621,7 +622,7 @@ class phy_params /// fapi2::ReturnCode set_ATxImpedance(user_input_msdg& io_phy_params) const { - io_phy_params.ATxImpedance = iv_params.iv_atx_impedance; + io_phy_params.ATxImpedance = iv_params.iv_atx_impedance[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -632,7 +633,7 @@ class phy_params /// fapi2::ReturnCode set_ATxSlewRate(user_input_msdg& io_phy_params) const { - io_phy_params.ATxSlewRate = iv_params.iv_atx_slew_rate; + io_phy_params.ATxSlewRate = iv_params.iv_atx_slew_rate[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -643,7 +644,7 @@ class phy_params /// fapi2::ReturnCode set_CKTxImpedance(user_input_msdg& io_phy_params) const { - io_phy_params.CKTxImpedance = iv_params.iv_ck_tx_impedance; + io_phy_params.CKTxImpedance = iv_params.iv_ck_tx_impedance[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -654,7 +655,7 @@ class phy_params /// fapi2::ReturnCode set_CKTxSlewRate(user_input_msdg& io_phy_params) const { - io_phy_params.CKTxSlewRate = iv_params.iv_ck_tx_slew_rate; + io_phy_params.CKTxSlewRate = iv_params.iv_ck_tx_slew_rate[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -665,7 +666,7 @@ class phy_params /// fapi2::ReturnCode set_AlertOdtImpedance(user_input_msdg& io_phy_params) const { - io_phy_params.AlertOdtImpedance = iv_params.iv_alert_odt_impedance; + io_phy_params.AlertOdtImpedance = iv_params.iv_alert_odt_impedance[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -729,7 +730,7 @@ class phy_params /// fapi2::ReturnCode set_DramWritePreamble(user_input_msdg& io_phy_params) const { - fapi2::buffer<uint8_t> l_dram_preamble_buf(iv_params.iv_dram_preamble); + fapi2::buffer<uint8_t> l_dram_preamble_buf(iv_params.iv_dram_preamble[0][0]); io_phy_params.DramWritePreamble[0] = l_dram_preamble_buf.getBit<fapi2::ENUM_ATTR_MEM_SI_DRAM_PREAMBLE_WRITE_PREAMBLE_BIT>(); return fapi2::FAPI2_RC_SUCCESS; @@ -742,7 +743,7 @@ class phy_params /// fapi2::ReturnCode set_DramReadPreamble(user_input_msdg& io_phy_params) const { - fapi2::buffer<uint8_t> l_dram_preamble_buf(iv_params.iv_dram_preamble); + fapi2::buffer<uint8_t> l_dram_preamble_buf(iv_params.iv_dram_preamble[0][0]); io_phy_params.DramReadPreamble[0] = l_dram_preamble_buf.getBit<fapi2::ENUM_ATTR_MEM_SI_DRAM_PREAMBLE_READ_PREAMBLE_BIT>(); return fapi2::FAPI2_RC_SUCCESS; @@ -755,7 +756,7 @@ class phy_params /// fapi2::ReturnCode set_PhyEqualization(user_input_msdg& io_phy_params) const { - io_phy_params.PhyEqualization = iv_params.iv_phy_equalization; + io_phy_params.PhyEqualization = iv_params.iv_phy_equalization[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -790,7 +791,7 @@ class phy_params /// fapi2::ReturnCode set_OdtWrMapCs(user_input_msdg& io_phy_params) const { - io_phy_params.OdtWrMapCs[0] = iv_params.iv_odt_wr_map_cs; + io_phy_params.OdtWrMapCs[0] = iv_params.iv_odt_wr_map_cs[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -801,7 +802,7 @@ class phy_params /// fapi2::ReturnCode set_OdtRdMapCs(user_input_msdg& io_phy_params) const { - io_phy_params.OdtRdMapCs[0] = iv_params.iv_odt_rd_map_cs; + io_phy_params.OdtRdMapCs[0] = iv_params.iv_odt_rd_map_cs[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -812,7 +813,7 @@ class phy_params /// fapi2::ReturnCode set_Geardown(user_input_msdg& io_phy_params) const { - io_phy_params.Geardown[0] = iv_params.iv_geardown_mode[0]; + io_phy_params.Geardown[0] = iv_params.iv_geardown_mode[0][0]; return fapi2::FAPI2_RC_SUCCESS; } diff --git a/src/import/generic/memory/lib/mss_generic_attribute_getters.H b/src/import/generic/memory/lib/mss_generic_attribute_getters.H index dc22d4fb0..bce94f55f 100644 --- a/src/import/generic/memory/lib/mss_generic_attribute_getters.H +++ b/src/import/generic/memory/lib/mss_generic_attribute_getters.H @@ -83,8 +83,8 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note [Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin to -/// the Module Package Data (DQ) Pinout +/// @note ARRAY[Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin +/// to the Module Package Data (DQ) Pinout /// inline fapi2::ReturnCode get_mem_vpd_dq_map(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[72]) @@ -102,62 +102,14 @@ fapi_try_exit: } /// -/// @brief ATTR_MEM_GEARDOWN_MODE getter -/// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel -/// will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none -/// -inline fapi2::ReturnCode get_geardown_mode(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) -{ - uint8_t l_value[2] = {}; - const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_GEARDOWN_MODE, l_port, l_value) ); - o_value = l_value[mss::index(i_target)]; - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_GEARDOWN_MODE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_GEARDOWN_MODE getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t&[] array reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel -/// will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none -/// -inline fapi2::ReturnCode get_geardown_mode(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[2]) -{ - uint8_t l_value[2] = {}; - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_GEARDOWN_MODE, i_target, l_value) ); - memcpy(o_array, &l_value, 2); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_GEARDOWN_MODE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// /// @brief ATTR_MEM_DIMM_DDR4_F0RC0F getter /// @param[in] const ref to the TARGET_TYPE_DIMM /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from -/// 00 to 04. No need to calculate; User can override with desired experimental value. -/// creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC0F - Command Latency Adder Control Word; Default value - 04. Values +/// Range from 00 to 04. No need to calculate; User can override with desired experimental +/// value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc0f(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { @@ -180,9 +132,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from -/// 00 to 04. No need to calculate; User can override with desired experimental value. -/// creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC0F - Command Latency Adder Control Word; Default value - 04. Values +/// Range from 00 to 04. No need to calculate; User can override with desired experimental +/// value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc0f(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) @@ -205,9 +157,8 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: -/// none +/// @note ARRAY[DIMM] CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. +/// Each memory channel will have a value. /// inline fapi2::ReturnCode get_cs_cmd_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { @@ -230,9 +181,8 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: -/// none +/// @note ARRAY[DIMM] CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. +/// Each memory channel will have a value. /// inline fapi2::ReturnCode get_cs_cmd_latency(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) @@ -255,9 +205,8 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: -/// none +/// @note ARRAY[DIMM] C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. +/// Each memory channel will have a value. /// inline fapi2::ReturnCode get_ca_parity_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { @@ -280,9 +229,8 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: -/// none +/// @note ARRAY[DIMM] C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. +/// Each memory channel will have a value. /// inline fapi2::ReturnCode get_ca_parity_latency(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) @@ -305,9 +253,8 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range from 0-8. -/// No need to calculate; User can override with desired experimental value. creator: -/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range +/// from 0-8. No need to calculate; User can override with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { @@ -330,9 +277,8 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range from 0-8. -/// No need to calculate; User can override with desired experimental value. creator: -/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range +/// from 0-8. No need to calculate; User can override with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc02(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) @@ -355,10 +301,9 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default value - -/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD -/// byte 137, 1st Nibble for CS and CA. creator: mss_eff_cnfg consumer: mss_dram_init -/// firmware notes: none +/// @note ARRAY[DIMM] F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default +/// value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from +/// SPD byte 137, 1st Nibble for CS and CA. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { @@ -381,10 +326,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default value - -/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD -/// byte 137, 1st Nibble for CS and CA. creator: mss_eff_cnfg consumer: mss_dram_init -/// firmware notes: none +/// @note ARRAY[DIMM] F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default +/// value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from +/// SPD byte 137, 1st Nibble for CS and CA. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc03(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) @@ -407,10 +351,9 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default value -/// - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD -/// byte 137, 2nd Nibble for ODT and CKE. creator: mss_eff_cnfg consumer: mss_dram_init -/// firmware notes: none +/// @note ARRAY[DIMM] F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default +/// value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from +/// SPD byte 137, 2nd Nibble for ODT and CKE. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { @@ -433,10 +376,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default value -/// - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD -/// byte 137, 2nd Nibble for ODT and CKE. creator: mss_eff_cnfg consumer: mss_dram_init -/// firmware notes: none +/// @note ARRAY[DIMM] F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default +/// value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from +/// SPD byte 137, 2nd Nibble for ODT and CKE. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc04(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) @@ -459,9 +401,9 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC05 - Clock Driver Characteristics Control Word; Default value - 0x05 (Moderate -/// Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble -/// for CK. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC05 - Clock Driver Characteristics Control Word; Default value - +/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD +/// byte 138, 2nd Nibble for CK. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { @@ -484,9 +426,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC05 - Clock Driver Characteristics Control Word; Default value - 0x05 (Moderate -/// Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble -/// for CK. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC05 - Clock Driver Characteristics Control Word; Default value - +/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD +/// byte 138, 2nd Nibble for CK. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc05(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) @@ -509,10 +451,9 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. +/// @note ARRAY[DIMM] Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. /// Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User -/// can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init -/// firmware notes: none +/// can override with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc0b(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { @@ -535,10 +476,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. +/// @note ARRAY[DIMM] Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. /// Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User -/// can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init -/// firmware notes: none +/// can override with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc0b(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) @@ -561,9 +501,9 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 -/// to 3F.No need to calculate; User can override with desired experimental value. creator: -/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range +/// from 00 to 3F. No need to calculate; User can override with desired experimental +/// value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc1x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { @@ -586,9 +526,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 -/// to 3F.No need to calculate; User can override with desired experimental value. creator: -/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range +/// from 00 to 3F. No need to calculate; User can override with desired experimental +/// value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc1x(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) @@ -611,9 +551,8 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need -/// to calculate; User can override with desired experimental value. creator: mss_eff_cnfg -/// consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to +/// FF.No need to calculate. User can override with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc7x(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { @@ -636,9 +575,8 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need -/// to calculate; User can override with desired experimental value. creator: mss_eff_cnfg -/// consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to +/// FF.No need to calculate. User can override with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc7x(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) @@ -661,10 +599,9 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value -/// - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired -/// experimental value. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: -/// none +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f1rc00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { @@ -687,10 +624,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value -/// - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired -/// experimental value. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: -/// none +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f1rc00(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t (&o_array)[2]) @@ -708,205 +644,201 @@ fapi_try_exit: } /// -/// @brief ATTR_MEM_VREF_DQ_TRAIN_VALUE getter +/// @brief ATTR_MEM_DIMM_DDR4_F1RC02 getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t&[] array reference to store the value +/// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: -/// none +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default +/// value - 00. Values Range from 00 to 0F. No need to calculate; User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_vref_dq_train_value(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t (&o_array)[4]) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { - uint8_t l_value[2][4] = {}; + uint8_t l_value[2] = {}; const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_VALUE, l_port, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC02, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC02: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_VREF_DQ_TRAIN_VALUE getter +/// @brief ATTR_MEM_DIMM_DDR4_F1RC02 getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: -/// none +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default +/// value - 00. Values Range from 00 to 0F. No need to calculate; User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_vref_dq_train_value(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[2][4]) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc02(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) { - uint8_t l_value[2][4] = {}; + uint8_t l_value[2] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_VALUE, i_target, l_value) ); - memcpy(o_array, &l_value, 8); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC02, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC02: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_VREF_DQ_TRAIN_RANGE getter +/// @brief ATTR_MEM_DIMM_DDR4_F1RC03 getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t&[] array reference to store the value +/// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: -/// none +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_vref_dq_train_range(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t (&o_array)[4]) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { - uint8_t l_value[2][4] = {}; + uint8_t l_value[2] = {}; const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_RANGE, l_port, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC03, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC03: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_VREF_DQ_TRAIN_RANGE getter +/// @brief ATTR_MEM_DIMM_DDR4_F1RC03 getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: -/// none +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_vref_dq_train_range(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[2][4]) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc03(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) { - uint8_t l_value[2][4] = {}; + uint8_t l_value[2] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_RANGE, i_target, l_value) ); - memcpy(o_array, &l_value, 8); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC03, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC03: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_PSTATES getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @brief ATTR_MEM_DIMM_DDR4_F1RC04 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Number of p-states used Always set NumPStates to 1 for Explorer. -/// -inline fapi2::ReturnCode get_pstates(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_PSTATES, i_target, o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_PSTATES: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_BYTE_ENABLES getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint16_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Enable/Disable DBYTE macro (clock gating and IO tri-state) 10-bit bitmap Right aligned +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_byte_enables(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint16_t& o_value) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_BYTE_ENABLES, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC04, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_BYTE_ENABLES: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC04: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_NIBBLE_ENABLES getter +/// @brief ATTR_MEM_DIMM_DDR4_F1RC04 getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint32_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Account/Ignore training/dfi_bist result on the selected nibble. 20-bit bitmap Right -/// aligned +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_nibble_enables(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint32_t& o_value) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc04(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) { + uint8_t l_value[2] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_NIBBLE_ENABLES, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC04, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_NIBBLE_ENABLES: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC04: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_TAA_MIN getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @brief ATTR_MEM_DIMM_DDR4_F1RC05 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Timing value used to calculate CAS Latency +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_taa_min(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) { + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_TAA_MIN, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC05, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_TAA_MIN: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC05: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_RANK_FOUR_MODE getter +/// @brief ATTR_MEM_DIMM_DDR4_F1RC05 getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DIMM Rank 4 mode enable +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_rank4_mode(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc05(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) { + uint8_t l_value[2] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_RANK_FOUR_MODE, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC05, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_RANK_FOUR_MODE: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC05: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } @@ -2503,89 +2435,6 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief ATTR_MEM_EFF_MRAM_SUPPORT getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Supports MRAM or not -/// -inline fapi2::ReturnCode get_mram_support(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_MRAM_SUPPORT, i_target, o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_EFF_MRAM_SUPPORT: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_EFF_3DS_HEIGHT getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note ARRAY[DIMM] Primary SDRAM Package Type. Decodes Byte 6. This byte defines the primary -/// set of SDRAMs. Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = -/// 3DS -/// -inline fapi2::ReturnCode get_3ds_height(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_3DS_HEIGHT, i_target, o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_EFF_3DS_HEIGHT: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_EFF_DDP_COMPATIBLE getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DDP Compatibility -/// -inline fapi2::ReturnCode get_ddp_compatibility(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DDP_COMPATIBLE, i_target, o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_EFF_DDP_COMPATIBLE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_EFF_TSV8H_SUPPORT getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note TSVH8 Support -/// -inline fapi2::ReturnCode get_tsv8h_support(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_TSV8H_SUPPORT, i_target, o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_EFF_TSV8H_SUPPORT: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - /// /// @brief ATTR_MEM_EFF_VOLT_VDDR getter @@ -2895,21 +2744,51 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_DRAM_PREAMBLE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Number of clocks used for read/write preamble. Calibration only +/// uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. +/// The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit +/// 3 for READ preamble, and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK preamble +/// for both READ and WRITE +/// +inline fapi2::ReturnCode get_si_dram_preamble(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_PREAMBLE, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_DRAM_PREAMBLE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_DRAM_PREAMBLE getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble -/// (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. The value of "0" means -/// 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for READ preamble, -/// and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK preamble for both READ -/// and WRITE +/// @note Array[DIMM][RANK] Number of clocks used for read/write preamble. Calibration only +/// uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. +/// The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit +/// 3 for READ preamble, and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK preamble +/// for both READ and WRITE /// inline fapi2::ReturnCode get_si_dram_preamble(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_PREAMBLE, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_PREAMBLE, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3060,18 +2939,285 @@ fapi_try_exit: } /// +/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note ARRAY[DIMM][RANK] vrefdq_train value. This is for DDR4 MRS6. +/// +inline fapi2::ReturnCode get_si_vref_dq_train_value(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note ARRAY[DIMM][RANK] vrefdq_train value. This is for DDR4 MRS6. +/// +inline fapi2::ReturnCode get_si_vref_dq_train_value(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note ARRAY[DIMM][RANK] vrefdq_train range. This is for DDR4 MRS6. +/// +inline fapi2::ReturnCode get_si_vref_dq_train_range(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note ARRAY[DIMM][RANK] vrefdq_train range. This is for DDR4 MRS6. +/// +inline fapi2::ReturnCode get_si_vref_dq_train_range(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_GEARDOWN_MODE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note ARRAY[DIMM][RANK] Gear Down Mode. This is for DDR4 MRS3. Each memory channel will +/// have a value. +/// +inline fapi2::ReturnCode get_si_geardown_mode(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_GEARDOWN_MODE, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_GEARDOWN_MODE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_GEARDOWN_MODE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note ARRAY[DIMM][RANK] Gear Down Mode. This is for DDR4 MRS3. Each memory channel will +/// have a value. +/// +inline fapi2::ReturnCode get_si_geardown_mode(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_GEARDOWN_MODE, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_GEARDOWN_MODE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_DQ_DQS getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Tx drive impedance for DQ/DQS of all ranks in ohms +/// +inline fapi2::ReturnCode get_si_mc_drv_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_DQ_DQS, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_DQ_DQS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_DQ_DQS getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Tx drive impedance for DQ/DQS of all ranks in ohms +/// +inline fapi2::ReturnCode get_si_mc_drv_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_DQ_DQS, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_DQ_DQS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Receiver Equalization for Data and Data +/// Strobe Lines. +/// +inline fapi2::ReturnCode get_si_mc_rcv_eq_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Receiver Equalization for Data and Data +/// Strobe Lines. +/// +inline fapi2::ReturnCode get_si_mc_rcv_eq_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Equalization for Data and Data Strobe +/// Lines. +/// +inline fapi2::ReturnCode get_si_mc_drv_eq_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// /// @brief ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Equalization for Data and Data Strobe Lines. +/// @note Array[DIMM][RANK] Memory Controller side Drive Equalization for Data and Data Strobe +/// Lines. /// inline fapi2::ReturnCode get_si_mc_drv_eq_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3082,17 +3228,43 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_IMP_CLK getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Clock in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CLK, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CLK: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_CLK getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Clock in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_clk(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CLK, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CLK, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3103,18 +3275,45 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Address, Bank Address, +/// Bank Group and Activate Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_imp_cmd_addr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and -/// Activate Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Address, Bank Address, +/// Bank Group and Activate Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_cmd_addr(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3125,18 +3324,45 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_IMP_CNTL getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Clock Enable, ODT, +/// Parity, and Reset Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CNTL, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CNTL: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_CNTL getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset -/// Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Clock Enable, ODT, +/// Parity, and Reset Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_cntl(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CNTL, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CNTL, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3147,17 +3373,45 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_IMP_CSCID getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Chip Select and Chip +/// ID Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_imp_cscid(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CSCID, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CSCID: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_CSCID getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Chip Select and Chip +/// ID Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_cscid(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CSCID, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CSCID, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3169,20 +3423,20 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Drive Impedance Pull Down for Data and Data -/// Strobe Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Down for Data and +/// Data Strobe Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_dq_dqs_pull_down(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN, l_port, l_value) ); - o_value = l_value[mss::index(i_target)]; + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -3197,16 +3451,16 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Drive Impedance Pull Down for Data and Data -/// Strobe Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Down for Data and +/// Data Strobe Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_dq_dqs_pull_down(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[1]) + uint8_t (&o_array)[2][4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN, i_target, l_value) ); - memcpy(o_array, &l_value, 1); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3218,20 +3472,20 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Drive Impedance Pull Up for Data and Data Strobe -/// Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Up for Data and Data +/// Strobe Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_dq_dqs_pull_up(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP, l_port, l_value) ); - o_value = l_value[mss::index(i_target)]; + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -3246,16 +3500,16 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Drive Impedance Pull Up for Data and Data Strobe -/// Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Up for Data and Data +/// Strobe Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_dq_dqs_pull_up(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[1]) + uint8_t (&o_array)[2][4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP, i_target, l_value) ); - memcpy(o_array, &l_value, 1); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3266,17 +3520,43 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Clock in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_slew_rate_clk(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Slew Rate for Clock in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Clock in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_slew_rate_clk(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3287,18 +3567,45 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Address, Bank Address, +/// Bank Group and Activate Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_slew_rate_cmd_addr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Slew Rate for Address, Bank Address, Bank Group and -/// Activate Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Address, Bank Address, +/// Bank Group and Activate Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_slew_rate_cmd_addr(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3309,18 +3616,45 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Clock Enable, ODT, +/// Parity, and Reset Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_slew_rate_cntl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Slew Rate for Clock Enable, ODT, Parity, and Reset -/// Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Clock Enable, ODT, +/// Parity, and Reset Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_slew_rate_cntl(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3331,17 +3665,45 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Chip Select and Chip +/// ID Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_slew_rate_cscid(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Slew Rate for Chip Select and Chip ID Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Chip Select and Chip +/// ID Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_slew_rate_cscid(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3353,20 +3715,20 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Drive Slew Rate for Data and Data Strobe Lines -/// in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Data and Data Strobe +/// Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_slew_rate_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS, l_port, l_value) ); - o_value = l_value[mss::index(i_target)]; + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -3381,16 +3743,16 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Drive Slew Rate for Data and Data Strobe Lines -/// in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Data and Data Strobe +/// Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_slew_rate_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[1]) + uint8_t (&o_array)[2][4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS, i_target, l_value) ); - memcpy(o_array, &l_value, 1); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3400,22 +3762,25 @@ fapi_try_exit: } /// -/// @brief ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @brief ATTR_MEM_SI_MC_RCV_IMP_ALERT_N getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Receiver Equalization for Data and Data Strobe Lines. +/// @note Memory Controller side Receiver Impedance. Alert_N line in Ohms. /// -inline fapi2::ReturnCode get_si_mc_rcv_eq_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode get_si_mc_rcv_imp_alert_n(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[4]) { + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_ALERT_N, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_SI_MC_RCV_IMP_ALERT_N: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } @@ -3423,16 +3788,18 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_RCV_IMP_ALERT_N getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Memory Controller side Receiver Impedance. Alert_N line in Ohms. /// inline fapi2::ReturnCode get_si_mc_rcv_imp_alert_n(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_ALERT_N, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_ALERT_N, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3444,20 +3811,20 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Receiver Impedance. Data and Data Strobe Lines -/// in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Receiver Impedance. Data and Data Strobe +/// Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t& o_value) + uint8_t (&o_array)[4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS, l_port, l_value) ); - o_value = l_value[mss::index(i_target)]; + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -3472,16 +3839,16 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Receiver Impedance. Data and Data Strobe Lines -/// in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Receiver Impedance. Data and Data Strobe +/// Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_rcv_imp_dq_dqs(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[1]) + uint8_t (&o_array)[2][4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS, i_target, l_value) ); - memcpy(o_array, &l_value, 1); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: |