diff options
author | Jennifer A. Stofer <stofer@us.ibm.com> | 2019-01-31 11:16:33 -0600 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-05 17:07:14 -0600 |
commit | d9535e0964076972f2d868ccd6e5121c02f27196 (patch) | |
tree | 9f52476ac22ca5c976d0b8f55cebea74b0ffc88f /src/import/generic | |
parent | 8d0bb9d30bd0794ba572ad50238d13c18c9c0aef (diff) | |
download | talos-hostboot-d9535e0964076972f2d868ccd6e5121c02f27196.tar.gz talos-hostboot-d9535e0964076972f2d868ccd6e5121c02f27196.zip |
Revert "Adds exp_draminit_mc"
This reverts commit 7a9e1cebc8cf1304102f6032cf65a8bb781005c1.
Change-Id: Id86cd49977c4311e89d37186cfa302abc7877cfb
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71146
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71182
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/generic')
5 files changed, 1 insertions, 490 deletions
diff --git a/src/import/generic/memory/lib/utils/index.H b/src/import/generic/memory/lib/utils/index.H index dc60b8c19..828dc3fa6 100644 --- a/src/import/generic/memory/lib/utils/index.H +++ b/src/import/generic/memory/lib/utils/index.H @@ -91,19 +91,6 @@ inline size_t index(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target) } /// -/// @brief Return an attribute array index from a OCMB target -/// @param[in] i_target a MEM_PORT target representing the OCMB in question -/// @return size_t the attribute array index. -/// -template<> -inline size_t index(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target) -{ - typedef procTraits<proc_type::AXONE> TT; - // We may need to revisit this later if we get an OCMB that has more than one port. - return mss::pos(i_target) % TT::EXP_PORTS_PER_OCMB; -} - -/// /// @brief Return an attribute array index from a rank number /// @param[in] i_rank uint64_t a rank number DIMM0 {0, 1, 2, 3} DIMM1 {0, 1, 2, 3} /// @return size_t the attribute array index. diff --git a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H index f3c98567b..bb3725d94 100644 --- a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H +++ b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H @@ -22,396 +22,3 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ - -/// -/// @file gen_mss_port.H -/// @brief Code to support ports -/// -// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: HB:FSP - - -#ifndef _GEN_MSS_PORT_H_ -#define _GEN_MSS_PORT_H_ - -#include <fapi2.H> -#include <generic/memory/lib/utils/shared/mss_generic_consts.H> -#include <generic/memory/lib/utils/mc/gen_mss_port_traits.H> -#include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/c_str.H> - -namespace mss -{ - -/// -/// @brief ATTR_MSS_MVPD_FWMS getter declare -/// @param[in] const ref to the fapi2::Target<fapi2::TargetType> -/// @param[out] uint32_t* memory to store the value -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Mark store records from MPVD Lx -/// keyword -/// -template< mss::mc_type MC, fapi2::TargetType T> -inline fapi2::ReturnCode mvpd_fwms(const fapi2::Target< T>& i_target, uint32_t (&o_array)[8]); - -/// -/// @brief Enable power management -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode enable_power_management( const fapi2::Target<T>& i_target ) -{ - //Enable Power management based off of mrw_power_control_requested - FAPI_INF("%s Enable Power min max domains", mss::c_str(i_target)); - - bool is_pwr_cntrl = true; - fapi2::buffer<uint64_t> l_data; - uint8_t l_pwr_cntrl = 0; - - // Get the value from attribute and write it to scom register - FAPI_TRY(fapi2::getScom(i_target, TT::MBARPC0Q_REG, l_data)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), - l_pwr_cntrl)); - - is_pwr_cntrl = ((l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_POWER_DOWN) - || (l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_PD_AND_STR) - || (l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_PD_AND_STR_CLK_STOP)); - - l_data.writeBit< TT::CFG_MIN_MAX_DOMAINS_ENABLE>(is_pwr_cntrl); - FAPI_TRY( fapi2::putScom(i_target, TT::MBARPC0Q_REG, l_data) ); - - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Set the IML init complete bit -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode change_iml_complete( const fapi2::Target<T>& i_target, states i_state ) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_DBG("Change the IML init complete bit to high for %s %s", (i_state == HIGH ? "high" : "low"), - mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB6Q_REG, l_data) ); - l_data.writeBit<TT::CFG_INIT_COMPLETE>(i_state); - FAPI_TRY( mss::putScom(i_target, TT::FARB6Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Read the read ECC Control register -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[out] o_buffer the buffer to write the register data into -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode read_recr_register( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_buffer ) -{ - FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, o_buffer) ); - - FAPI_INF( "Read ECC Control register is 0x%016lx for %s", uint64_t(o_buffer), mss::c_str(i_target) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write to RECR register -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_buffer the buffer that holds the register data to write -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode write_recr_register( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_buffer ) -{ - FAPI_INF( "Change Read ECC Control register to 0x%016lx for %s", i_buffer, mss::c_str(i_target) ); - - FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, i_buffer) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get the tce correction enable value from RECR -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_data the data buffer containing the RECR register -/// @param[out] o_value TCE_CORRECTION_ENABLE value (on or off) -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -void get_tce_correction( const fapi2::buffer<uint64_t>& i_data, mss::states& o_value ) -{ - o_value = i_data.template getBit<TT::RECR_TCE_CORRECTION>() ? mss::states::ON : mss::states::OFF; - - FAPI_INF( "TCE_CORRECTION_ENABLE: %lu", o_value ); -} - -/// -/// @brief Sets tce correction enable in buffer -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in,out] io_data the target data buffer -/// @param[in] i_value TCE_CORRECTION_ENABLE value (on or off) to set -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -void set_tce_correction( fapi2::buffer<uint64_t>& io_data, const mss::states i_value ) -{ - FAPI_INF( "Set TCE_CORRECTION_ENABLE to %lu", i_value); - - io_data.template writeBit<TT::RECR_TCE_CORRECTION>(i_value); -} - -/// -/// @brief Setup TCE correction -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode setup_tce_correction (const fapi2::Target<T>& i_target) -{ - constexpr uint64_t MNFG_REPAIRS_DISABLED_ATTR = 56; - fapi2::buffer<uint64_t> l_data; - fapi2::buffer<uint64_t> l_mnfg_buffer; - mss::states l_state = mss::OFF; - - FAPI_TRY( mss::read_recr_register(i_target, l_data ), "%s: Failed read_recr_register", mss::c_str(i_target)); - - // Check for manufacturing disable dram repair flag to disable TCE correction - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MNFG_FLAGS, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_mnfg_buffer), - "%s: Failed mnfg_flags check", mss::c_str(i_target) ); - l_state = ( l_mnfg_buffer.getBit<MNFG_REPAIRS_DISABLED_ATTR>() ) ? mss::OFF : mss::ON; - mss::set_tce_correction<T>(l_data, l_state); - - FAPI_TRY( mss::write_recr_register(i_target, l_data), "%s: Failed write_recr_register", mss::c_str(i_target)); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Change the state of the port_fail_disable bit -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// @note Disable Port Fail after recurring RCD errors. -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode change_port_fail_disable( const fapi2::Target<T>& i_target, states i_state ) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_DBG("Change port fail disable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) ); - l_data.writeBit<TT::PORT_FAIL_DISABLE>(i_state); - FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Change the state of the dfi init start bit -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode change_dfi_init_start( const fapi2::Target<T>& i_target, states i_state ) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_DBG("Change rcd recovery disable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) ); - l_data.writeBit<TT::DFI_INIT_START>(i_state); - FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Change the state of the addr_mux_sel bit -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode change_addr_mux_sel( const fapi2::Target<T>& i_target, states i_state ) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_DBG("Change addr_mux_sel to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) ); - l_data.writeBit<TT::CFG_CCS_ADDR_MUX_SEL>(i_state); - FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Change the state of the MC Refresh enable bit -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode change_refresh_enable( const fapi2::Target<T>& i_target, states i_state ) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_DBG("Change refresh enable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::REFRESH_REG, l_data) ); - l_data.writeBit<TT::REFRESH_ENABLE>(i_state); - FAPI_TRY( mss::putScom(i_target, TT::REFRESH_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Enable periodic zq cal -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode enable_zq_cal( const fapi2::Target<T>& i_target ) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_DBG("Enable periodic zq cal for %s", mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB9Q_REG, l_data) ); - l_data.writeBit<TT::CFG_ZQ_PER_CAL_ENABLE>(mss::HIGH); - FAPI_TRY( mss::putScom(i_target, TT::FARB9Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Enable Read ECC checking -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode enable_read_ecc( const fapi2::Target<T>& i_target ) -{ - fapi2::buffer<uint64_t> l_data; - - uint8_t l_sim = 0; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_sim) ); - - FAPI_DBG("Enable Read ECC %s", mss::c_str(i_target)); - - FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) ); - l_data.clearBit<TT::ECC_CHECK_DISABLE>(); - l_data.clearBit<TT::ECC_CORRECT_DISABLE>(); - - // VBU tests assume good ECC and we don't have good ECC (since we're not writing everything) - // so we can't run with address checking. Disable address checking in sim. - l_data.writeBit<TT::ECC_USE_ADDR_HASH>(l_sim ? 0 : 1); - - // The preferred operating mode is 11 (INVERT_DATA_TOGGLE_CHECKS) which stores data complemented - // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power) but - // still flips the inversion of check bits to aid RAS. Per Brad Michael 12/15 - // Leave un-inverted for sim. This allows the DIMM loader to write 0's and effect good ECC - l_data.insertFromRight<TT::RECR_MBSECCQ_DATA_INVERSION, TT::RECR_MBSECCQ_DATA_INVERSION_LEN>(l_sim ? 0b00 : 0b11); - - // bits: 60 MBSTRQ_CFG_MAINT_RCE_WITH_CE - // cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus. - - FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Apply mark store bits from module VPD -/// @tparam MC the memory controller type -/// @tparam T, the fapi2 target type of the target -/// @tparam TT, the class traits for the port -/// @param[in] i_target A target representing a port -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode apply_mark_store( const fapi2::Target<T>& i_target ) -{ - FAPI_INF("Enable marks from MVPD %s", mss::c_str(i_target)); - - uint32_t l_fwms[MARK_STORE_COUNT]; - - FAPI_TRY( mss::mvpd_fwms<MC>(i_target, l_fwms) ); - - for (size_t l_mark = 0; l_mark < MARK_STORE_COUNT; ++l_mark) - { - if (l_fwms[l_mark] != 0) - { - fapi2::buffer<uint64_t> l_fwms_data; - // This assumes the attribute contents are in the same format as the register fields, - // ending just before the EXIT_1 bit - l_fwms_data.insertFromRight < TT::FWMS0_MARK, TT::FWMS0_EXIT_1 - TT::FWMS0_MARK + 1 > (l_fwms[l_mark]); - FAPI_TRY( mss::putScom(i_target, TT::FWMS_REG + l_mark, l_fwms_data) ); - } - } - -fapi_try_exit: - return fapi2::current_err; -} - -}// ns mss - -#endif diff --git a/src/import/generic/memory/lib/utils/mc/gen_mss_port_traits.H b/src/import/generic/memory/lib/utils/mc/gen_mss_port_traits.H index a5bdb2b77..3d1dea5e6 100644 --- a/src/import/generic/memory/lib/utils/mc/gen_mss_port_traits.H +++ b/src/import/generic/memory/lib/utils/mc/gen_mss_port_traits.H @@ -22,33 +22,3 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ - -/// -/// @file gen_mss_port_traits.H -/// @brief Contains the port traits definition -/// -// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: HB:FSP - -#ifndef _GEN_MSS_PORT_TRAITS_H_ -#define _GEN_MSS_PORT_TRAITS_H_ - -#include <fapi2.H> - -namespace mss -{ - -/// -/// @class Traits and policy class for port -/// @tparam MC the memory controller type -/// @tparam fapi2::TargetType port type -/// -template< mss::mc_type MC, fapi2::TargetType T > -class portTraits; - -} // ns mss - -#endif diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index 41e36ca55..d017933bb 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -82,7 +82,6 @@ enum conversions enum generic_sizes { NUM_MAX_FREQS = 5, ///< Used for ATTR_MAX_ALLOWED_DIMM_FREQ - MARK_STORE_COUNT = 8, ///< Elements in a VPD mark/store array }; /// @@ -189,30 +188,6 @@ enum ddr_dimm_speeds DDR5_MAX_SPEED = 4800, }; -enum states -{ - LOW = 0, - HIGH = 1, - START = 1, - STOP = 0, - START_N = 0, - STOP_N = 1, - ON = 1, - OFF = 0, - ON_N = 0, - OFF_N = 1, - YES = 1, - NO = 0, - YES_N = 0, - NO_N = 1, - // Uses "_" in the name for INVALID as INVALID is defined as a macro in the - // FSP code. If we just use INVALID as an enum name, then the preprocessor - // compile phase changes it to be the macro. - _INVALID_ = 0xFF, - NO_CHIP_SELECT_ACTIVE = 0xFF, -}; - - namespace spd { @@ -316,20 +291,6 @@ struct procTraits<proc_type::NIMBUS> }; }; -/// -/// @brief Trait classes for proc_type - AXONE specialization -/// -/// TODO: Need to add mc_type -template< > -struct procTraits<proc_type::AXONE> -{ - enum - { - EXP_PORTS_PER_OCMB = 1, - }; -}; - - }// mss #endif diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml index faf8a75fb..ba699ad18 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml @@ -22,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<attributes> +<attributes> <attribute> <id>ATTR_MEM_MRW_IS_PLANAR</id> <targetType>TARGET_TYPE_OCMB_CHIP</targetType> @@ -38,18 +38,4 @@ <mssAccessorName>mem_mrw_is_planar</mssAccessorName> </attribute> - <attribute> - <id>ATTR_MSS_MRW_POWER_CONTROL_REQUESTED</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Memory power control settings programmed during IPL - Used by OCC when exiting idle power-save mode - </description> - <valueType>uint8</valueType> - <enum>OFF = 0x00, POWER_DOWN = 0x01, PD_AND_STR = 0x02, PD_AND_STR_CLK_STOP = 0x03</enum> - <platInit/> - <default>OFF</default> - <initToZero/> - <mssAccessorName>mrw_power_control_requested</mssAccessorName> - </attribute> </attributes> |