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author | Jennifer A. Stofer <stofer@us.ibm.com> | 2019-01-31 11:16:33 -0600 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-05 17:07:14 -0600 |
commit | d9535e0964076972f2d868ccd6e5121c02f27196 (patch) | |
tree | 9f52476ac22ca5c976d0b8f55cebea74b0ffc88f /src/import | |
parent | 8d0bb9d30bd0794ba572ad50238d13c18c9c0aef (diff) | |
download | talos-hostboot-d9535e0964076972f2d868ccd6e5121c02f27196.tar.gz talos-hostboot-d9535e0964076972f2d868ccd6e5121c02f27196.zip |
Revert "Adds exp_draminit_mc"
This reverts commit 7a9e1cebc8cf1304102f6032cf65a8bb781005c1.
Change-Id: Id86cd49977c4311e89d37186cfa302abc7877cfb
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71146
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71182
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import')
16 files changed, 319 insertions, 609 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C index c69ae7656..2c579a4ef 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C @@ -268,13 +268,13 @@ fapi2::ReturnCode pda_vref_latch( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& } // Disable refresh - FAPI_TRY( mss::change_refresh_enable<mss::mc_type::NIMBUS>(l_mca, states::LOW) ); + FAPI_TRY( mss::change_refresh_enable(l_mca, states::LOW) ); // execute_wr_vref_latch(l_container) FAPI_TRY( mss::ddr4::pda::execute_wr_vref_latch(l_container) ) // Enable refresh - FAPI_TRY( mss::change_refresh_enable<mss::mc_type::NIMBUS>(l_mca, states::HIGH) ); + FAPI_TRY( mss::change_refresh_enable(l_mca, states::HIGH) ); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C index 31d9977b7..034927ffa 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C @@ -130,7 +130,7 @@ fapi2::ReturnCode after_memdiags( const fapi2::Target<TARGET_TYPE_MCBIST>& i_tar FAPI_TRY( mss::putScom(p, MCA_ACTION1, l_aue_buffer) ); // Note: We also want to include the following setup RCD recovery and port fail - FAPI_TRY( mss::change_port_fail_disable<mss::mc_type::NIMBUS>(p, mss::LOW) ); + FAPI_TRY( mss::change_port_fail_disable(p, mss::LOW) ); FAPI_TRY( mss::change_rcd_recovery_disable(p, mss::LOW) ); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C index 0488fd579..97e7fa229 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C @@ -72,7 +72,7 @@ constexpr uint64_t BIT_SPARE_7 = 15; // 7: SPARE template<> fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) { - typedef portTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA> TT; + typedef portTraits<fapi2::TARGET_TYPE_MCA> TT; uint32_t l_memcal_interval = 0; uint32_t l_zqcal_interval = 0; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index 1b66d66bf..c2023ae27 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -25,7 +25,7 @@ /// /// @file port.H -/// @brief Code to support ports +/// @brief Code to support ports (phy _ mc for certain operations) /// // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> @@ -38,41 +38,35 @@ #include <fapi2.H> -#include <lib/mss_attribute_accessors.H> -#include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/mc/gen_mss_port.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> +#include <lib/mss_attribute_accessors.H> #include <lib/utils/mss_nimbus_conversions.H> #include <lib/shared/mss_const.H> +#include <generic/memory/lib/utils/scom.H> #include <lib/dimm/rank.H> +#include <generic/memory/lib/utils/c_str.H> #include <lib/mcbist/address.H> namespace mss { -/// -/// @brief ATTR_MSS_MVPD_FWMS getter -/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> -/// @param[out] uint32_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (G) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Mark store records from MPVD Lx -/// keyword -/// -template<> -inline fapi2::ReturnCode mvpd_fwms<mss::mc_type::NIMBUS>(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - uint32_t (&o_array)[mss::MARK_STORE_COUNT]) -{ - return mvpd_fwms(i_target, &o_array[0]); -} +// I have a dream that port code can be shared among controllers. So, I drive the +// engine from a set of traits. This might be folly. Allow me to dream. BRS +template< fapi2::TargetType T > +class portTraits; +// Centaur port traits +template<> +class portTraits<fapi2::TARGET_TYPE_MBA> +{ + public: +}; // Nimbus port traits template<> -class portTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA> +class portTraits<fapi2::TARGET_TYPE_MCA> { public: static constexpr uint64_t FARB5Q_REG = MCA_MBA_FARB5Q; @@ -84,7 +78,6 @@ class portTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA> static constexpr uint64_t CAL2Q_REG = MCA_MBA_CAL2Q; static constexpr uint64_t CAL3Q_REG = MCA_MBA_CAL3Q; static constexpr uint64_t DSM0Q_REG = MCA_MBA_DSM0Q; - static constexpr uint64_t FWMS_REG = MCA_FWMS0; // Danger Will Robinson <wave robot arms> MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0 uses PHY rank ordinal numbers // which are different between PHYs. So if you're playing with this register, be sure to map rank numbers. @@ -119,9 +112,6 @@ class portTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA> CFG_DDR_RESETN = MCA_MBA_FARB5Q_CFG_DDR_RESETN, CFG_CCS_ADDR_MUX_SEL = MCA_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL, - FWMS0_MARK = MCA_FWMS0_MARK, - FWMS0_EXIT_1 = MCA_FWMS0_EXIT_1, - REFRESH_ENABLE = MCA_MBAREF0Q_CFG_REFRESH_ENABLE, ECC_CHECK_DISABLE = MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT, @@ -241,8 +231,6 @@ class portTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA> RECR_ENABLE_UE_NOISE_WINDOW = MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW, RECR_TCE_CORRECTION = MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, RECR_READ_POINTER_DLY = MCA_RECR_MBSECCQ_READ_POINTER_DELAY, - RECR_MBSECCQ_DATA_INVERSION = MCA_RECR_MBSECCQ_DATA_INVERSION, - RECR_MBSECCQ_DATA_INVERSION_LEN = MCA_RECR_MBSECCQ_DATA_INVERSION_LEN, RECR_READ_POINTER_DLY_LEN = MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN, DSM0Q_RDTAG_DLY = MCA_MBA_DSM0Q_CFG_RDTAG_DLY, DSM0Q_RDTAG_DLY_LEN = MCA_MBA_DSM0Q_CFG_RDTAG_DLY_LEN, @@ -283,8 +271,43 @@ class portTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA> }; }; +/// +/// @brief Read the read ECC Control register +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[out] o_buffer the buffer to write the register data into +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T, typename TT = portTraits<T> > +fapi2::ReturnCode read_recr_register( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_buffer ) +{ + FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, o_buffer) ); + FAPI_INF( "Read ECC Control register is 0x%016lx for %s", uint64_t(o_buffer), mss::c_str(i_target) ); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write to RECR register +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_buffer the buffer that holds the register data to write +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T, typename TT = portTraits<T> > +fapi2::ReturnCode write_recr_register( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_buffer ) +{ + FAPI_INF( "Change Read ECC Control register to 0x%016lx for %s", i_buffer, mss::c_str(i_target) ); + + FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, i_buffer) ); + +fapi_try_exit: + return fapi2::current_err; +} /// /// @brief Get the read pointer delay value from RECR @@ -293,7 +316,7 @@ class portTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA> /// @param[in] i_data the data buffer containing the RECR register /// @param[out] o_delay READ_POINTER_DLY value (in cycles) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > void get_read_pointer_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_delay ) { i_data.template extractToRight<TT::RECR_READ_POINTER_DLY, TT::RECR_READ_POINTER_DLY_LEN>(o_delay); @@ -308,7 +331,7 @@ void get_read_pointer_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_ /// @param[in,out] io_data the target data buffer /// @param[in] i_delay READ_POINTER_DLY value (in cycles) to set /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > void set_read_pointer_delay( fapi2::buffer<uint64_t>& io_data, const uint64_t i_delay ) { FAPI_INF( "Set READ_POINTER_DLY to %d", i_delay); @@ -316,6 +339,35 @@ void set_read_pointer_delay( fapi2::buffer<uint64_t>& io_data, const uint64_t i_ io_data.template insertFromRight<TT::RECR_READ_POINTER_DLY, TT::RECR_READ_POINTER_DLY_LEN>(i_delay); } +/// +/// @brief Get the tce correction enable value from RECR +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_data the data buffer containing the RECR register +/// @param[out] o_value TCE_CORRECTION_ENABLE value (on or off) +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > +void get_tce_correction( const fapi2::buffer<uint64_t>& i_data, mss::states& o_value ) +{ + o_value = i_data.template getBit<TT::RECR_TCE_CORRECTION>() ? mss::states::ON : mss::states::OFF; + + FAPI_INF( "TCE_CORRECTION_ENABLE: %lu", o_value ); +} + +/// +/// @brief Sets tce correction enable in buffer +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in,out] io_data the target data buffer +/// @param[in] i_value TCE_CORRECTION_ENABLE value (on or off) to set +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > +void set_tce_correction( fapi2::buffer<uint64_t>& io_data, const mss::states i_value ) +{ + FAPI_INF( "Set TCE_CORRECTION_ENABLE to %lu", i_value); + + io_data.template writeBit<TT::RECR_TCE_CORRECTION>(i_value); +} /// /// @brief Get the enable_ue_noise_window value from buffer @@ -324,7 +376,7 @@ void set_read_pointer_delay( fapi2::buffer<uint64_t>& io_data, const uint64_t i_ /// @param[in] i_data the data buffer containing the RECR register /// @param[out] o_value ENABLE_UE_NOISE_WINDOW value (on or off) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > void get_enable_ue_noise_window( const fapi2::buffer<uint64_t>& i_data, mss::states& o_value ) { o_value = (i_data.template getBit<TT::RECR_ENABLE_UE_NOISE_WINDOW>()) ? mss::states::ON : mss::states::OFF; @@ -339,7 +391,7 @@ void get_enable_ue_noise_window( const fapi2::buffer<uint64_t>& i_data, mss::sta /// @param[in,out] io_data the target data buffer /// @param[in] i_value ENABLE_UE_NOISE_WINDOW value (on or off) to set /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > void set_enable_ue_noise_window( fapi2::buffer<uint64_t>& io_data, const mss::states i_value ) { FAPI_INF( "Set ENABLE_UE_NOISE_WINDOW to %lu", i_value); @@ -355,7 +407,7 @@ void set_enable_ue_noise_window( fapi2::buffer<uint64_t>& io_data, const mss::st /// @param[in] i_target the target /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > fapi2::ReturnCode setup_read_pointer_delay (const fapi2::Target<T>& i_target) { constexpr uint64_t MNFG_REPAIRS_DISABLED_ATTR = 56; @@ -363,17 +415,15 @@ fapi2::ReturnCode setup_read_pointer_delay (const fapi2::Target<T>& i_target) fapi2::buffer<uint64_t> l_mnfg_buffer; mss::states l_state = mss::OFF; - FAPI_TRY( mss::read_recr_register<mss::mc_type::NIMBUS>(i_target, l_data ), "%s: Failed read_recr_register", - mss::c_str(i_target)); + FAPI_TRY( mss::read_recr_register(i_target, l_data ), "%s: Failed read_recr_register", mss::c_str(i_target)); mss::set_read_pointer_delay(l_data, mss::ON); // Check for manufacturing disable dram repair flag to disable TCE correction FAPI_TRY( mss::mnfg_flags(l_mnfg_buffer), "%s: Failed mnfg_flags check", mss::c_str(i_target) ); l_state = ( l_mnfg_buffer.getBit<MNFG_REPAIRS_DISABLED_ATTR>() ) ? mss::OFF : mss::ON; - mss::set_tce_correction<mss::mc_type::NIMBUS, T>(l_data, l_state); + mss::set_tce_correction(l_data, l_state); - FAPI_TRY( mss::write_recr_register<mss::mc_type::NIMBUS>(i_target, l_data), "%s: Failed write_recr_register", - mss::c_str(i_target)); + FAPI_TRY( mss::write_recr_register(i_target, l_data), "%s: Failed write_recr_register", mss::c_str(i_target)); fapi_try_exit: return fapi2::current_err; @@ -388,7 +438,7 @@ fapi_try_exit: /// @param[out] o_delay the buffer to write the register data into /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode read_dsm0q_register( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_delay ) { FAPI_TRY( mss::getScom(i_target, TT::DSM0Q_REG, o_delay) ); @@ -407,7 +457,7 @@ fapi_try_exit: /// @param[in] i_delay the buffer that holds the register data to write /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode write_dsm0q_register( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t> i_delay ) { FAPI_INF( "Change Data State machine register to %d for %s", i_delay, mss::c_str(i_target) ); @@ -425,7 +475,7 @@ fapi_try_exit: /// @param[in] i_data the data buffer containing the DSM0Q register /// @param[out] o_delay WRDONE_DLY value (in cycles) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > void get_wrdone_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_delay ) { i_data.template extractToRight<TT::DSM0Q_WRDONE_DLY, TT::DSM0Q_WRDONE_DLY_LEN>(o_delay); @@ -440,7 +490,7 @@ void get_wrdone_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_delay /// @param[in] i_delay WRDONE_DLY value (in cycles) to set /// @param[in,out] io_data the target data buffer /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > void set_wrdone_delay( const uint64_t i_delay, fapi2::buffer<uint64_t>& io_data ) { FAPI_INF( "Set WRDONE_DLY to %d ", i_delay); @@ -456,7 +506,7 @@ void set_wrdone_delay( const uint64_t i_delay, fapi2::buffer<uint64_t>& io_data /// @param[in] i_delay WRDONE_DLY value (in cycles) to set /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode change_wrdone_delay( const fapi2::Target<T>& i_target, const uint64_t i_delay ) { fapi2::buffer<uint64_t> l_data; @@ -480,7 +530,7 @@ fapi_try_exit: /// @param[in] i_data the data buffer containing the DSM0Q register /// @param[out] o_delay RDTAG_DLY value (in cycles) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > void get_rdtag_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_delay ) { i_data.template extractToRight<TT::DSM0Q_RDTAG_DLY, TT::DSM0Q_RDTAG_DLY_LEN>(o_delay); @@ -495,7 +545,7 @@ void get_rdtag_delay( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_delay ) /// @param[in] i_delay RDTAG_DLY value (in cycles) to set /// @param[in,out] io_data the target data buffer /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > void set_rdtag_delay( const uint64_t i_delay, fapi2::buffer<uint64_t>& io_data ) { FAPI_DBG( "Set RDTAG_DLY to %d ", i_delay); @@ -512,7 +562,7 @@ void set_rdtag_delay( const uint64_t i_delay, fapi2::buffer<uint64_t>& io_data ) /// @param[in] i_delay new RDTAG_DLY value (in cycles) to set /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode change_rdtag_delay( const fapi2::Target<T>& i_target, const uint64_t i_delay ) { fapi2::buffer<uint64_t> l_data; @@ -537,7 +587,7 @@ fapi_try_exit: /// @param[out] o_time the buffer to read the register data into /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode read_farb0q_register( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_time ) { FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, o_time) ); @@ -556,7 +606,7 @@ fapi_try_exit: /// @param[in] i_delay the buffer containing the data to be written /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode write_farb0q_register( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t> i_time ) { FAPI_INF( "Change FARB0Q_REG to 0x%016lx for %s", uint64_t(i_time), mss::c_str(i_target) ); @@ -574,7 +624,7 @@ fapi_try_exit: /// @param[in] i_data the data buffer containing the FARB0Q register /// @param[out] o_time RCD_PROTECT_TIME value (in cycles) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > void get_rcd_protect_time( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_time ) { i_data.template extractToRight<TT::FARB0Q_RCD_PROTECTION_TIME, TT::FARB0Q_RCD_PROTECTION_TIME_LEN>(o_time); @@ -590,7 +640,7 @@ void get_rcd_protect_time( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_ti /// @param[in] i_delay RCD Protect Time value (in cycles) to set /// @param[in,out] io_data the target data buffer /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits<T> > void set_rcd_protect_time( const uint64_t i_time, fapi2::buffer<uint64_t>& io_data ) { FAPI_DBG( "Set RCD_PROTECT_TIME to %d ", i_time); @@ -606,7 +656,7 @@ void set_rcd_protect_time( const uint64_t i_time, fapi2::buffer<uint64_t>& io_da /// @param[in] i_time RCD Protect Time value (in cycles) to set /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode change_rcd_protect_time( const fapi2::Target<T>& i_target, const uint64_t i_time ) { fapi2::buffer<uint64_t> l_data; @@ -623,6 +673,28 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Change the state of the port_fail_disable bit +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note Disable Port Fail after recurring RCD errors. +/// +template< fapi2::TargetType T, typename TT = portTraits<T> > +fapi2::ReturnCode change_port_fail_disable( const fapi2::Target<T>& i_target, states i_state ) +{ + fapi2::buffer<uint64_t> l_data; + + FAPI_DBG("Change port fail disable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); + FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) ); + l_data.writeBit<TT::PORT_FAIL_DISABLE>(i_state); + FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} /// /// @brief Change the state of the RCD recovery bit @@ -632,7 +704,7 @@ fapi_try_exit: /// @param[in] i_state the state /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode change_rcd_recovery_disable( const fapi2::Target<T>& i_target, states i_state ) { fapi2::buffer<uint64_t> l_data; @@ -654,7 +726,7 @@ fapi_try_exit: /// @param[in] i_state the state /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode change_oe_always_on( const fapi2::Target<T>& i_target, states i_state ) { fapi2::buffer<uint64_t> l_data; @@ -668,6 +740,50 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Change the state of the addr_mux_sel bit +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T, typename TT = portTraits<T> > +fapi2::ReturnCode change_addr_mux_sel( const fapi2::Target<T>& i_target, states i_state ) +{ + fapi2::buffer<uint64_t> l_data; + + FAPI_DBG("Change addr_mux_sel to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); + FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) ); + l_data.writeBit<TT::CFG_CCS_ADDR_MUX_SEL>(i_state); + FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + + +/// +/// @brief Change the state of the MC Refresh enable bit +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T, typename TT = portTraits<T> > +fapi2::ReturnCode change_refresh_enable( const fapi2::Target<T>& i_target, states i_state ) +{ + fapi2::buffer<uint64_t> l_data; + + FAPI_DBG("Change refresh enable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); + FAPI_TRY( mss::getScom(i_target, TT::REFRESH_REG, l_data) ); + l_data.writeBit<TT::REFRESH_ENABLE>(i_state); + FAPI_TRY( mss::putScom(i_target, TT::REFRESH_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} /// /// @brief Enable the MC Periodic calibration functionality @@ -676,7 +792,7 @@ fapi_try_exit: /// @param[in] i_target the target /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<T>& i_target ); /// @@ -687,6 +803,45 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<T>& i_target ); template<> fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ); +/// +/// @brief Enable Read ECC checking +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T, typename TT = portTraits<T> > +fapi2::ReturnCode enable_read_ecc( const fapi2::Target<T>& i_target ) +{ + fapi2::buffer<uint64_t> l_data; + + uint8_t l_sim = 0; + FAPI_TRY( mss::is_simulation(l_sim) ); + + FAPI_DBG("Enable Read ECC %s", mss::c_str(i_target)); + + FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) ); + l_data.clearBit<TT::ECC_CHECK_DISABLE>(); + l_data.clearBit<TT::ECC_CORRECT_DISABLE>(); + + // VBU tests assume good ECC and we don't have good ECC (since we're not writing everything) + // so we can't run with address checking. Disable address checking in sim. + l_data.writeBit<TT::ECC_USE_ADDR_HASH>(l_sim ? 0 : 1); + + // The preferred operating mode is 11 (INVERT_DATA_TOGGLE_CHECKS) which stores data complemented + // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power) but + // still flips the inversion of check bits to aid RAS. Per Brad Michael 12/15 + // Leave un-inverted for sim. This allows the DIMM loader to write 0's and effect good ECC + l_data.insertFromRight<MCA_RECR_MBSECCQ_DATA_INVERSION, MCA_RECR_MBSECCQ_DATA_INVERSION_LEN>(l_sim ? 0b00 : 0b11); + + // bits: 60 MBSTRQ_CFG_MAINT_RCE_WITH_CE + // cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus. + + FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} // // We expect to come in to draminit with the following setup: @@ -705,7 +860,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MC // This is in this header as it's hoped to be able to be shared. Seems to make more // Might make more sense in p9_mss_draminit.C ... BRS /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > inline fapi2::ReturnCode draminit_entry_invariant( const fapi2::Target<T>& i_target ) { fapi2::buffer<uint64_t> l_data; @@ -734,7 +889,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if and only if ok /// @note this might need a port id added for Centaur/MBA controllers /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode drive_mem_clks( const fapi2::Target<T>& i_target, const uint64_t i_pclk, const uint64_t i_nclk ) { fapi2::buffer<uint64_t> l_data; @@ -763,7 +918,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if and only if ok /// @note this might need a port id added for Centaur/MBA controllers /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode ddr_resetn( const fapi2::Target<T>& i_target, const bool i_state ) { fapi2::buffer<uint64_t> l_data; @@ -796,13 +951,43 @@ fapi_try_exit: } /// +/// @brief Apply mark store bits from module VPD +/// @tparam T, the fapi2 target type of the target +/// @tparam TT, the class traits for the port +/// @param[in] i_target A target representing a port +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T, typename TT = portTraits<T> > +fapi2::ReturnCode apply_mark_store( const fapi2::Target<T>& i_target ) +{ + FAPI_INF("Enable marks from MVPD"); + + uint32_t l_fwms[MARK_STORE_COUNT]; + + FAPI_TRY( mss::mvpd_fwms(i_target, &(l_fwms[0])) ); + + for (size_t l_mark = 0; l_mark < MARK_STORE_COUNT; ++l_mark) + { + if (l_fwms[l_mark] != 0) + { + fapi2::buffer<uint64_t> l_fwms_data; + l_fwms_data.insertFromRight < MCA_FWMS0_MARK, MCA_FWMS0_EXIT_1 - MCA_FWMS0_MARK + 1 > (l_fwms[l_mark]); + FAPI_TRY( mss::putScom(i_target, MCA_FWMS0 + l_mark, l_fwms_data) ); + } + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief Reset the ZCAL config register. /// @warning This maps PHY rank numbers per target /// @tparam T, the fapi2 target type of the target /// @param[in] i_target A target representing a port /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits<mss::mc_type::NIMBUS, T> > +template< fapi2::TargetType T, typename TT = portTraits<T> > fapi2::ReturnCode reset_zqcal_config( const fapi2::Target<T>& i_target ) { fapi2::buffer<uint64_t> l_phy_zqcal_config; @@ -831,7 +1016,7 @@ fapi_try_exit: /// inline fapi2::ReturnCode configure_wrq(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const mss::states i_state) { - typedef portTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA> TT; + typedef portTraits<fapi2::TARGET_TYPE_MCA> TT; fapi2::buffer<uint64_t> l_data; @@ -879,7 +1064,7 @@ fapi_try_exit: /// inline fapi2::ReturnCode configure_rrq(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const mss::states i_state) { - typedef portTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA> TT; + typedef portTraits<fapi2::TARGET_TYPE_MCA> TT; fapi2::buffer<uint64_t> l_data; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index 75ea83e39..4a452ded7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -14178,6 +14178,28 @@ fapi_try_exit: } /// +/// @brief ATTR_MSS_MRW_POWER_CONTROL_REQUESTED getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Memory power control settings programmed during IPL Used by OCC when exiting +/// idle power-save +/// mode +/// +inline fapi2::ReturnCode mrw_power_control_requested(uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_POWER_CONTROL_REQUESTED: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// /// @brief ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED getter /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) @@ -21304,51 +21326,6 @@ fapi_try_exit: } -/// -/// @brief ATTR_MEM_MRW_IS_PLANAR getter -/// @param[in] const ref to the TARGET_TYPE_OCMB_CHIP -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (PROC_CHIP) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Indicates if the DIMM connected to this controller are in a planar -/// configuration -/// -inline fapi2::ReturnCode mem_mrw_is_planar(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_MRW_IS_PLANAR, i_target, o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MEM_MRW_IS_PLANAR: 0x%lx", - uint64_t(fapi2::current_err)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MSS_MRW_POWER_CONTROL_REQUESTED getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory power control settings programmed during IPL Used by OCC when exiting -/// idle power-save -/// mode -/// -inline fapi2::ReturnCode mrw_power_control_requested(uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), - o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_POWER_CONTROL_REQUESTED: 0x%lx (system target)", - uint64_t(fapi2::current_err)); - return fapi2::current_err; -} - - } #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index ea7748d2d..7c89b99a6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -74,6 +74,7 @@ enum sizes NUM_LRDIMM_TRAINING_PATTERNS = 5, ///< Used for ATTR_MSS_LRDIMM_TRAINING_PATTERN + MARK_STORE_COUNT = 8, ///< Elements in a VPD mark/store array BAD_DQ_BYTE_COUNT = 10, ///< Elements in a BAD_DQ_BITMAP attribute array ROW_REPAIR_BYTE_COUNT = 4, ///< Elements in a ROW_REPAIR_DATA attribute array. @@ -215,6 +216,29 @@ enum ffdc_function_codes MREP_CALL_OUT = 131, }; +enum states +{ + LOW = 0, + HIGH = 1, + START = 1, + STOP = 0, + START_N = 0, + STOP_N = 1, + ON = 1, + OFF = 0, + ON_N = 0, + OFF_N = 1, + YES = 1, + NO = 0, + YES_N = 0, + NO_N = 1, + // Uses "_" in the name for INVALID as INVALID is defined as a macro in the + // FSP code. If we just use INVALID as an enum name, then the preprocessor + // compile phase changes it to be the macro. + _INVALID_ = 0xFF, + NO_CHIP_SELECT_ACTIVE = 0xFF, +}; + // Static consts describing the bits used in the cal_step_enable attribute // These are bit positions. 0 is the left most bit. enum cal_steps : uint64_t diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C index e7c46f515..1e3e8b7b5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C @@ -208,9 +208,9 @@ fapi2::ReturnCode broadcast_out_of_sync( const fapi2::Target<fapi2::TARGET_TYPE_ fapi2::buffer<uint64_t> l_recr_buffer; // Set UE noise window for workaround - mss::read_recr_register<mss::mc_type::NIMBUS>(p, l_recr_buffer); + mss::read_recr_register(p, l_recr_buffer); mss::set_enable_ue_noise_window(l_recr_buffer, i_value); - mss::write_recr_register<mss::mc_type::NIMBUS>(p, l_recr_buffer); + mss::write_recr_register(p, l_recr_buffer); } fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C index d205e1107..f5d6aaefd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C @@ -41,7 +41,6 @@ #include <lib/utils/mss_nimbus_conversions.H> #include <lib/dimm/bcw_load.H> #include <lib/workarounds/dqs_align_workarounds.H> -#include <lib/mc/port.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; @@ -173,7 +172,7 @@ extern "C" // before the RCD/MRS CCSs for (const auto& p : l_mcas) { - FAPI_TRY( mss::change_addr_mux_sel<mss::mc_type::NIMBUS>(p, mss::LOW), + FAPI_TRY( change_addr_mux_sel(p, mss::LOW), "%s Failed change_addr_mux_sel in p9_mss_draminit", mss::c_str(i_target) ); } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index 91e8ff18e..af11935bf 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -114,11 +114,11 @@ extern "C" // mode prior to running memory diagnostics. This step may be superfluous but not harmful.) // Note: addr_mux_sel is set low in p9_mss_draminit(), however that might be a work-around so we // set it low here kind of like belt-and-suspenders. BRS - FAPI_TRY( mss::change_addr_mux_sel<mss::mc_type::NIMBUS>(p, mss::LOW), + FAPI_TRY( mss::change_addr_mux_sel(p, mss::LOW), "%s Failed to change_addr_mux_sel", mss::c_str(i_target) ); // Re-enable port fails. Turned off in draminit_training - FAPI_TRY( mss::change_port_fail_disable<mss::mc_type::NIMBUS>(p, mss::OFF ), + FAPI_TRY( mss::change_port_fail_disable(p, mss::OFF ), "%s Failed to change_port_fail_disable", mss::c_str(i_target) ); // MC work around for OE bug (seen in periodics + PHY) @@ -131,8 +131,7 @@ extern "C" // Start the refresh engines by setting MBAREF0Q(0) = “1”. Note that the remaining bits in // MBAREF0Q should retain their initialization values. - FAPI_TRY( mss::change_refresh_enable<mss::mc_type::NIMBUS>(p, mss::HIGH), "%s Failed change_refresh_enable", - mss::c_str(i_target) ); + FAPI_TRY( mss::change_refresh_enable(p, mss::HIGH), "%s Failed change_refresh_enable", mss::c_str(i_target) ); // Power management is handled in the init file. (or should be BRS) @@ -140,10 +139,10 @@ extern "C" FAPI_TRY( mss::enable_periodic_cal(p), "%s Failed enable_periodic_cal", mss::c_str(i_target) ); // Step Six: Setup Control Bit ECC - FAPI_TRY( mss::enable_read_ecc<mss::mc_type::NIMBUS>(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); + FAPI_TRY( mss::enable_read_ecc(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); // apply marks from MVPD - FAPI_TRY( mss::apply_mark_store<mss::mc_type::NIMBUS>(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); + FAPI_TRY( mss::apply_mark_store(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); } // At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked. diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index 5fbedcf7c..e4084b461 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -144,7 +144,7 @@ extern "C" // Disable port fails as it doesn't appear the MC handles initial cal timeouts // correctly (cal_length.) BRS, see conversation with Brad Michael - FAPI_TRY( mss::change_port_fail_disable<mss::mc_type::NIMBUS>(p, mss::ON ), "Error in p9_mss_draminit_training" ); + FAPI_TRY( mss::change_port_fail_disable(p, mss::ON ), "Error in p9_mss_draminit_training" ); // The following registers must be configured to the correct operating environment: diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml index 2e8fb7167..609ca575b 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml @@ -242,6 +242,21 @@ </attribute> <attribute> + <id>ATTR_MSS_MRW_POWER_CONTROL_REQUESTED</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Memory power control settings programmed during IPL + Used by OCC when exiting idle power-save mode + </description> + <valueType>uint8</valueType> + <enum>OFF = 0x00, POWER_DOWN = 0x01, PD_AND_STR = 0x02, PD_AND_STR_CLK_STOP = 0x03</enum> + <platInit/> + <default>OFF</default> + <initToZero/> + <mssAccessorName>mrw_power_control_requested</mssAccessorName> + </attribute> + + <attribute> <id>ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> diff --git a/src/import/generic/memory/lib/utils/index.H b/src/import/generic/memory/lib/utils/index.H index dc60b8c19..828dc3fa6 100644 --- a/src/import/generic/memory/lib/utils/index.H +++ b/src/import/generic/memory/lib/utils/index.H @@ -91,19 +91,6 @@ inline size_t index(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target) } /// -/// @brief Return an attribute array index from a OCMB target -/// @param[in] i_target a MEM_PORT target representing the OCMB in question -/// @return size_t the attribute array index. -/// -template<> -inline size_t index(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target) -{ - typedef procTraits<proc_type::AXONE> TT; - // We may need to revisit this later if we get an OCMB that has more than one port. - return mss::pos(i_target) % TT::EXP_PORTS_PER_OCMB; -} - -/// /// @brief Return an attribute array index from a rank number /// @param[in] i_rank uint64_t a rank number DIMM0 {0, 1, 2, 3} DIMM1 {0, 1, 2, 3} /// @return size_t the attribute array index. diff --git a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H index f3c98567b..bb3725d94 100644 --- a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H +++ b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H @@ -22,396 +22,3 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ - -/// -/// @file gen_mss_port.H -/// @brief Code to support ports -/// -// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: HB:FSP - - -#ifndef _GEN_MSS_PORT_H_ -#define _GEN_MSS_PORT_H_ - -#include <fapi2.H> -#include <generic/memory/lib/utils/shared/mss_generic_consts.H> -#include <generic/memory/lib/utils/mc/gen_mss_port_traits.H> -#include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/c_str.H> - -namespace mss -{ - -/// -/// @brief ATTR_MSS_MVPD_FWMS getter declare -/// @param[in] const ref to the fapi2::Target<fapi2::TargetType> -/// @param[out] uint32_t* memory to store the value -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Mark store records from MPVD Lx -/// keyword -/// -template< mss::mc_type MC, fapi2::TargetType T> -inline fapi2::ReturnCode mvpd_fwms(const fapi2::Target< T>& i_target, uint32_t (&o_array)[8]); - -/// -/// @brief Enable power management -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode enable_power_management( const fapi2::Target<T>& i_target ) -{ - //Enable Power management based off of mrw_power_control_requested - FAPI_INF("%s Enable Power min max domains", mss::c_str(i_target)); - - bool is_pwr_cntrl = true; - fapi2::buffer<uint64_t> l_data; - uint8_t l_pwr_cntrl = 0; - - // Get the value from attribute and write it to scom register - FAPI_TRY(fapi2::getScom(i_target, TT::MBARPC0Q_REG, l_data)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), - l_pwr_cntrl)); - - is_pwr_cntrl = ((l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_POWER_DOWN) - || (l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_PD_AND_STR) - || (l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_PD_AND_STR_CLK_STOP)); - - l_data.writeBit< TT::CFG_MIN_MAX_DOMAINS_ENABLE>(is_pwr_cntrl); - FAPI_TRY( fapi2::putScom(i_target, TT::MBARPC0Q_REG, l_data) ); - - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Set the IML init complete bit -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode change_iml_complete( const fapi2::Target<T>& i_target, states i_state ) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_DBG("Change the IML init complete bit to high for %s %s", (i_state == HIGH ? "high" : "low"), - mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB6Q_REG, l_data) ); - l_data.writeBit<TT::CFG_INIT_COMPLETE>(i_state); - FAPI_TRY( mss::putScom(i_target, TT::FARB6Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Read the read ECC Control register -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[out] o_buffer the buffer to write the register data into -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode read_recr_register( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_buffer ) -{ - FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, o_buffer) ); - - FAPI_INF( "Read ECC Control register is 0x%016lx for %s", uint64_t(o_buffer), mss::c_str(i_target) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write to RECR register -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_buffer the buffer that holds the register data to write -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode write_recr_register( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_buffer ) -{ - FAPI_INF( "Change Read ECC Control register to 0x%016lx for %s", i_buffer, mss::c_str(i_target) ); - - FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, i_buffer) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get the tce correction enable value from RECR -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_data the data buffer containing the RECR register -/// @param[out] o_value TCE_CORRECTION_ENABLE value (on or off) -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -void get_tce_correction( const fapi2::buffer<uint64_t>& i_data, mss::states& o_value ) -{ - o_value = i_data.template getBit<TT::RECR_TCE_CORRECTION>() ? mss::states::ON : mss::states::OFF; - - FAPI_INF( "TCE_CORRECTION_ENABLE: %lu", o_value ); -} - -/// -/// @brief Sets tce correction enable in buffer -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in,out] io_data the target data buffer -/// @param[in] i_value TCE_CORRECTION_ENABLE value (on or off) to set -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -void set_tce_correction( fapi2::buffer<uint64_t>& io_data, const mss::states i_value ) -{ - FAPI_INF( "Set TCE_CORRECTION_ENABLE to %lu", i_value); - - io_data.template writeBit<TT::RECR_TCE_CORRECTION>(i_value); -} - -/// -/// @brief Setup TCE correction -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode setup_tce_correction (const fapi2::Target<T>& i_target) -{ - constexpr uint64_t MNFG_REPAIRS_DISABLED_ATTR = 56; - fapi2::buffer<uint64_t> l_data; - fapi2::buffer<uint64_t> l_mnfg_buffer; - mss::states l_state = mss::OFF; - - FAPI_TRY( mss::read_recr_register(i_target, l_data ), "%s: Failed read_recr_register", mss::c_str(i_target)); - - // Check for manufacturing disable dram repair flag to disable TCE correction - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MNFG_FLAGS, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_mnfg_buffer), - "%s: Failed mnfg_flags check", mss::c_str(i_target) ); - l_state = ( l_mnfg_buffer.getBit<MNFG_REPAIRS_DISABLED_ATTR>() ) ? mss::OFF : mss::ON; - mss::set_tce_correction<T>(l_data, l_state); - - FAPI_TRY( mss::write_recr_register(i_target, l_data), "%s: Failed write_recr_register", mss::c_str(i_target)); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Change the state of the port_fail_disable bit -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// @note Disable Port Fail after recurring RCD errors. -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode change_port_fail_disable( const fapi2::Target<T>& i_target, states i_state ) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_DBG("Change port fail disable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) ); - l_data.writeBit<TT::PORT_FAIL_DISABLE>(i_state); - FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Change the state of the dfi init start bit -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode change_dfi_init_start( const fapi2::Target<T>& i_target, states i_state ) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_DBG("Change rcd recovery disable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) ); - l_data.writeBit<TT::DFI_INIT_START>(i_state); - FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Change the state of the addr_mux_sel bit -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode change_addr_mux_sel( const fapi2::Target<T>& i_target, states i_state ) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_DBG("Change addr_mux_sel to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) ); - l_data.writeBit<TT::CFG_CCS_ADDR_MUX_SEL>(i_state); - FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Change the state of the MC Refresh enable bit -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode change_refresh_enable( const fapi2::Target<T>& i_target, states i_state ) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_DBG("Change refresh enable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::REFRESH_REG, l_data) ); - l_data.writeBit<TT::REFRESH_ENABLE>(i_state); - FAPI_TRY( mss::putScom(i_target, TT::REFRESH_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Enable periodic zq cal -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode enable_zq_cal( const fapi2::Target<T>& i_target ) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_DBG("Enable periodic zq cal for %s", mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB9Q_REG, l_data) ); - l_data.writeBit<TT::CFG_ZQ_PER_CAL_ENABLE>(mss::HIGH); - FAPI_TRY( mss::putScom(i_target, TT::FARB9Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Enable Read ECC checking -/// @tparam MC the memory controller type -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode enable_read_ecc( const fapi2::Target<T>& i_target ) -{ - fapi2::buffer<uint64_t> l_data; - - uint8_t l_sim = 0; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_sim) ); - - FAPI_DBG("Enable Read ECC %s", mss::c_str(i_target)); - - FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) ); - l_data.clearBit<TT::ECC_CHECK_DISABLE>(); - l_data.clearBit<TT::ECC_CORRECT_DISABLE>(); - - // VBU tests assume good ECC and we don't have good ECC (since we're not writing everything) - // so we can't run with address checking. Disable address checking in sim. - l_data.writeBit<TT::ECC_USE_ADDR_HASH>(l_sim ? 0 : 1); - - // The preferred operating mode is 11 (INVERT_DATA_TOGGLE_CHECKS) which stores data complemented - // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power) but - // still flips the inversion of check bits to aid RAS. Per Brad Michael 12/15 - // Leave un-inverted for sim. This allows the DIMM loader to write 0's and effect good ECC - l_data.insertFromRight<TT::RECR_MBSECCQ_DATA_INVERSION, TT::RECR_MBSECCQ_DATA_INVERSION_LEN>(l_sim ? 0b00 : 0b11); - - // bits: 60 MBSTRQ_CFG_MAINT_RCE_WITH_CE - // cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus. - - FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Apply mark store bits from module VPD -/// @tparam MC the memory controller type -/// @tparam T, the fapi2 target type of the target -/// @tparam TT, the class traits for the port -/// @param[in] i_target A target representing a port -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< mss::mc_type MC, fapi2::TargetType T, typename TT = portTraits<MC, T> > -fapi2::ReturnCode apply_mark_store( const fapi2::Target<T>& i_target ) -{ - FAPI_INF("Enable marks from MVPD %s", mss::c_str(i_target)); - - uint32_t l_fwms[MARK_STORE_COUNT]; - - FAPI_TRY( mss::mvpd_fwms<MC>(i_target, l_fwms) ); - - for (size_t l_mark = 0; l_mark < MARK_STORE_COUNT; ++l_mark) - { - if (l_fwms[l_mark] != 0) - { - fapi2::buffer<uint64_t> l_fwms_data; - // This assumes the attribute contents are in the same format as the register fields, - // ending just before the EXIT_1 bit - l_fwms_data.insertFromRight < TT::FWMS0_MARK, TT::FWMS0_EXIT_1 - TT::FWMS0_MARK + 1 > (l_fwms[l_mark]); - FAPI_TRY( mss::putScom(i_target, TT::FWMS_REG + l_mark, l_fwms_data) ); - } - } - -fapi_try_exit: - return fapi2::current_err; -} - -}// ns mss - -#endif diff --git a/src/import/generic/memory/lib/utils/mc/gen_mss_port_traits.H b/src/import/generic/memory/lib/utils/mc/gen_mss_port_traits.H index a5bdb2b77..3d1dea5e6 100644 --- a/src/import/generic/memory/lib/utils/mc/gen_mss_port_traits.H +++ b/src/import/generic/memory/lib/utils/mc/gen_mss_port_traits.H @@ -22,33 +22,3 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ - -/// -/// @file gen_mss_port_traits.H -/// @brief Contains the port traits definition -/// -// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: HB:FSP - -#ifndef _GEN_MSS_PORT_TRAITS_H_ -#define _GEN_MSS_PORT_TRAITS_H_ - -#include <fapi2.H> - -namespace mss -{ - -/// -/// @class Traits and policy class for port -/// @tparam MC the memory controller type -/// @tparam fapi2::TargetType port type -/// -template< mss::mc_type MC, fapi2::TargetType T > -class portTraits; - -} // ns mss - -#endif diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index 41e36ca55..d017933bb 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -82,7 +82,6 @@ enum conversions enum generic_sizes { NUM_MAX_FREQS = 5, ///< Used for ATTR_MAX_ALLOWED_DIMM_FREQ - MARK_STORE_COUNT = 8, ///< Elements in a VPD mark/store array }; /// @@ -189,30 +188,6 @@ enum ddr_dimm_speeds DDR5_MAX_SPEED = 4800, }; -enum states -{ - LOW = 0, - HIGH = 1, - START = 1, - STOP = 0, - START_N = 0, - STOP_N = 1, - ON = 1, - OFF = 0, - ON_N = 0, - OFF_N = 1, - YES = 1, - NO = 0, - YES_N = 0, - NO_N = 1, - // Uses "_" in the name for INVALID as INVALID is defined as a macro in the - // FSP code. If we just use INVALID as an enum name, then the preprocessor - // compile phase changes it to be the macro. - _INVALID_ = 0xFF, - NO_CHIP_SELECT_ACTIVE = 0xFF, -}; - - namespace spd { @@ -316,20 +291,6 @@ struct procTraits<proc_type::NIMBUS> }; }; -/// -/// @brief Trait classes for proc_type - AXONE specialization -/// -/// TODO: Need to add mc_type -template< > -struct procTraits<proc_type::AXONE> -{ - enum - { - EXP_PORTS_PER_OCMB = 1, - }; -}; - - }// mss #endif diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml index faf8a75fb..ba699ad18 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml @@ -22,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<attributes> +<attributes> <attribute> <id>ATTR_MEM_MRW_IS_PLANAR</id> <targetType>TARGET_TYPE_OCMB_CHIP</targetType> @@ -38,18 +38,4 @@ <mssAccessorName>mem_mrw_is_planar</mssAccessorName> </attribute> - <attribute> - <id>ATTR_MSS_MRW_POWER_CONTROL_REQUESTED</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - Memory power control settings programmed during IPL - Used by OCC when exiting idle power-save mode - </description> - <valueType>uint8</valueType> - <enum>OFF = 0x00, POWER_DOWN = 0x01, PD_AND_STR = 0x02, PD_AND_STR_CLK_STOP = 0x03</enum> - <platInit/> - <default>OFF</default> - <initToZero/> - <mssAccessorName>mrw_power_control_requested</mssAccessorName> - </attribute> </attributes> |