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| author | Louis Stermole <stermole@us.ibm.com> | 2019-05-31 15:58:41 -0400 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-06-11 12:40:03 -0500 |
| commit | d6e85c3e9c5bbe44f38eb26475d3125e6c7fa76b (patch) | |
| tree | 37a342e97ffb820327dd7c64471413732e19d5ce /src/import/generic/memory/lib | |
| parent | f702a3b2f6b688707968c25e44a9ae12381874c5 (diff) | |
| download | talos-hostboot-d6e85c3e9c5bbe44f38eb26475d3125e6c7fa76b.tar.gz talos-hostboot-d6e85c3e9c5bbe44f38eb26475d3125e6c7fa76b.zip | |
Add reset of FORCE_STR to exp_draminit_mc
Along with the corresponding update in exp_scominit, allows for
the PHY to perform a read latency training step to assist with
latency characterization and optimization.
JIRA EDBC-439
Change-Id: Ie12d785b9f9f7739e1435e9875797d237cbf6f1c
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78190
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78206
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/generic/memory/lib')
| -rw-r--r-- | src/import/generic/memory/lib/utils/mc/gen_mss_port.H | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H index 94e3fa6bf..1e776b49e 100644 --- a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H +++ b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H @@ -294,6 +294,19 @@ fapi_try_exit: /// +/// @brief Change the state of the force_str bit +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits<MC> > +fapi2::ReturnCode change_force_str( const fapi2::Target<T>& i_target, const states i_state ); + + +/// /// @brief Change the state of the MC Refresh enable bit /// @tparam MC the memory controller type /// @tparam T the fapi2 target type of the target |
