Fix exp_draminit phy_params

Change-Id: I624caa1310920daf172d6681e7c760442236070f
git-coreq:hostboot:I624caa1310920daf172d6681e7c760442236070f
CMVC-Coreq: 1086224
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78469
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78516
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

4 files changed, 21 insertions, 21 deletions

diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H
index cd904ef9b..213293fdd 100644
--- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H
+++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H
@@ -489,26 +489,26 @@ class decoder<mss::spd::device_type::DDR4, DDR4_CUSTOM_MICROCHIP, R > : public b
         }
 
         ///
-        /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_RANGE
+        /// @brief Decodes Host RD VREF DQ -> INIT_PHY_VREF
         /// @param[out] o_output encoding from SPD
         /// @return FAPI2_RC_SUCCESS if okay
         ///
-        virtual fapi2::ReturnCode wr_vref_dq_range(uint8_t& o_output) const override
+        virtual fapi2::ReturnCode init_phy_vref(uint8_t& o_output) const override
         {
-            FAPI_TRY(( reader<fields_t::WR_VREF_DQ_RANGE, R>(iv_target, iv_data, o_output)) );
+            FAPI_TRY( (reader<fields_t::INIT_PHY_VREF, R>(iv_target, iv_data, o_output)) );
 
         fapi_try_exit:
             return fapi2::current_err;
         }
 
         ///
-        /// @brief Decodes Host RD VREF DQ -> PHY_VREF_PERCENT
+        /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_RANGE
         /// @param[out] o_output encoding from SPD
         /// @return FAPI2_RC_SUCCESS if okay
         ///
-        virtual fapi2::ReturnCode phy_vref_percent(uint8_t& o_output) const
+        virtual fapi2::ReturnCode wr_vref_dq_range(uint8_t& o_output) const override
         {
-            FAPI_TRY( (reader<fields_t::PHY_VREF_PERCENT, R>(iv_target, iv_data, o_output)) );
+            FAPI_TRY(( reader<fields_t::WR_VREF_DQ_RANGE, R>(iv_target, iv_data, o_output)) );
 
         fapi_try_exit:
             return fapi2::current_err;
diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H
index d59aac75f..9a1415a75 100644
--- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H
+++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H
@@ -244,16 +244,16 @@ class fields<mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>
             PHY_EQUALIZATION_LEN = 2,
 
             // Byte 44: Initial WR VREF DQ setting
-            WR_VREF_DQ_BYTE = 44,
+            INIT_VREF_DQ_BYTE = 44,
             WR_VREF_DQ_RANGE_START = 1,
             WR_VREF_DQ_RANGE_LEN = 1,
             WR_VREF_DQ_VALUE_START = 2,
             WR_VREF_DQ_VALUE_LEN = 6,
 
             // Byte 45: Host RD VREF DQ
-            RD_VREF_DQ_BYTE = 45,
-            PHY_VREF_PERCENT_START = 1,
-            PHY_VREF_PERCENT_LEN = 7,
+            INIT_PHY_VREF_BYTE = 45,
+            INIT_PHY_VREF_START = 1,
+            INIT_PHY_VREF_LEN = 7,
 
             // Byte 46: ODT WR Map CS Byte1
             ODT_WR_MAP1_BYTE = 46,
@@ -554,12 +554,12 @@ class fields<mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>
         // Byte 43: PHY Equalization
         static constexpr field_t PHY_EQUALIZATION{PHY_EQUALIZATION_BYTE, PHY_EQUALIZATION_START, PHY_EQUALIZATION_LEN};
 
-        // Byte 44: Initial WR VREF DQ setting
-        static constexpr field_t WR_VREF_DQ_RANGE{WR_VREF_DQ_BYTE, WR_VREF_DQ_RANGE_START, WR_VREF_DQ_RANGE_LEN};
-        static constexpr field_t WR_VREF_DQ_VALUE{WR_VREF_DQ_BYTE, WR_VREF_DQ_VALUE_START, WR_VREF_DQ_VALUE_LEN};
+        // Byte 44: Initial VREF DQ setting
+        static constexpr field_t WR_VREF_DQ_RANGE{INIT_VREF_DQ_BYTE, WR_VREF_DQ_RANGE_START, WR_VREF_DQ_RANGE_LEN};
+        static constexpr field_t WR_VREF_DQ_VALUE{INIT_VREF_DQ_BYTE, WR_VREF_DQ_VALUE_START, WR_VREF_DQ_VALUE_LEN};
 
-        // Byte 45: Host RD VREF DQ
-        static constexpr field_t PHY_VREF_PERCENT{RD_VREF_DQ_BYTE, PHY_VREF_PERCENT_START, PHY_VREF_PERCENT_LEN};
+        // Byte 45: Initial PHY VREF setting
+        static constexpr field_t INIT_PHY_VREF{INIT_PHY_VREF_BYTE, INIT_PHY_VREF_START, INIT_PHY_VREF_LEN};
 
         // Byte 46: ODT WR Map CS Byte1
         static constexpr field_t ODT_WR_MAP_RANK3{ODT_WR_MAP1_BYTE, ODT_WR_MAP_RANK3_START, ODT_WR_MAP_RANK3_LEN};
diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H
index 784dba0f6..1acdc554d 100644
--- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H
+++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H
@@ -784,7 +784,7 @@ class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUS
 /// @note valid for all revs
 ///
 template< mss::spd::rev R >
-class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::PHY_VREF_PERCENT, R >
+class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::INIT_PHY_VREF, R >
 {
     public:
 
diff --git a/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H b/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H
index 8427b5b88..df0dbed5e 100644
--- a/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H
+++ b/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H
@@ -492,7 +492,7 @@ class base_decoder
         }
 
         ///
-        /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_RANGE
+        /// @brief Decodes Initial VREF DQ setting -> WR_VREF_DQ_RANGE
         /// @param[out] o_output encoding from SPD
         /// @return FAPI2_RC_SUCCESS if okay
         ///
@@ -503,22 +503,22 @@ class base_decoder
         }
 
         ///
-        /// @brief Decodes Host RD VREF DQ -> PHY_VREF_PERCENT
+        /// @brief Decodes Initial VREF DQ setting -> WR_VREF_DQ_VALUE
         /// @param[out] o_output encoding from SPD
         /// @return FAPI2_RC_SUCCESS if okay
         ///
-        virtual fapi2::ReturnCode phy_vref_percent(uint8_t& o_output) const
+        virtual fapi2::ReturnCode wr_vref_dq_value(uint8_t& o_output) const
         {
             o_output = 0;
             return fapi2::FAPI2_RC_SUCCESS;
         }
 
         ///
-        /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_VALUE
+        /// @brief Decodes Initial PHY VREF -> INIT_PHY_VREF
         /// @param[out] o_output encoding from SPD
         /// @return FAPI2_RC_SUCCESS if okay
         ///
-        virtual fapi2::ReturnCode wr_vref_dq_value(uint8_t& o_output) const
+        virtual fapi2::ReturnCode init_phy_vref(uint8_t& o_output) const
         {
             o_output = 0;
             return fapi2::FAPI2_RC_SUCCESS;