diff options
19 files changed, 570 insertions, 407 deletions
diff --git a/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H b/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H index bca66bed1..aab5715b2 100644 --- a/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H +++ b/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H @@ -75,7 +75,7 @@ enum exp_struct_sizes /// @brief The host command structure /// @note The HOST uses 64 Byte Command Information Unit (IU) for sending commands to Firmware /// -typedef struct +typedef struct __attribute__((packed)) { // Command Header uint8_t cmd_id; // Command type @@ -88,14 +88,15 @@ typedef struct uint32_t padding[CMD_PADDING_SIZE]; // Fill up to the size of one cache line uint8_t command_argument[ARGUMENT_SIZE]; // Additional parameters associated with the command uint32_t cmd_header_crc; // CRC of 64 bytes of command header -} host_fw_command_struct; +} +host_fw_command_struct; /// /// @class host_fw_response_struct /// @brief The firmware response structure /// @note The Firmware uses 64 Byte Response Information Unit (IU) for sending responses to HOST /// -typedef struct +typedef struct __attribute__((packed)) { // Response Header uint8_t response_id; // Response ID - same as Command ID @@ -107,7 +108,8 @@ typedef struct uint32_t padding[RSP_PADDING_SIZE]; // Fill up to the size of one cache line uint8_t response_argument[ARGUMENT_SIZE]; // Additional parameters associated with the response uint32_t response_header_crc; // CRC of 64 bytes of reponse header -} host_fw_response_struct; +} +host_fw_response_struct; /// @@ -115,7 +117,7 @@ typedef struct /// @brief PHY initialization parameters /// @note PHY FW module requires certain parameters from HOST software /// -typedef struct user_input_msdg +typedef struct __attribute__((packed)) user_input_msdg { uint32_t version_number; @@ -166,7 +168,7 @@ typedef struct user_input_msdg // 0 = No Address Mirror. uint16_t AddrMirror; - // DRAM Column Addr Width (Valid value: 5,6,7,10) + // DRAM Column Addr Width (Valid value: 10) uint16_t ColumnAddrWidth; // DRAM Row Addr Width (Valid value: 14,15,16,17,18) @@ -595,7 +597,7 @@ typedef struct user_input_msdg /// @brief The sensor cache structure /// @note The data in the sensor cache is returned in 2 32-byte packets /// -typedef struct +typedef struct __attribute__((packed)) { /* * Packet 0 @@ -636,14 +638,15 @@ typedef struct uint8_t initial_packet1; // initial_packet1[0] '1' on first packet1 return, otherwise '0' // // initial_packet1[1:7] Reserved uint8_t reserved1[SENSOR_CACHE_PADDING_SIZE_1]; -} sensor_cache_struct; +} +sensor_cache_struct; /// /// @class user_response_timing_msdg_t /// @brief Contains the command to command timing training results /// -typedef struct user_response_timing_msdg +typedef struct __attribute__((packed)) user_response_timing_msdg { uint16_t DFIMRL_DDRCLK_trained; // Training result of DFIMRL_DDRCLK parameter (by mrlTraining step). // DFIMRL_DDRCLK: Max Read Latency counted by DDR Clock. dfi_rddata is returned (14 + DFIMRL_DDRCLK) cycles after dfi_rddata_en is asserted. @@ -667,7 +670,7 @@ typedef struct user_response_timing_msdg /// @class user_response_error_msdg /// @brief Contains the lane failure results /// -typedef struct user_response_error_msdg +typedef struct __attribute__((packed)) user_response_error_msdg { uint16_t Failure_Lane[TRAINING_RESPONSE_NUM_LANES]; // error code of DQ[n] on Rank 3,2,1 & 0. Rank 0 is in LS Nibble. //Failure status of training. Each uint16_t field contains the training error code of all 4 ranks on 1 DQ lane. @@ -689,7 +692,7 @@ typedef struct user_response_error_msdg /// @class user_response_mrs_msdg_t /// @brief MRS response structure /// -typedef struct user_response_mrs_msdg_t +typedef struct __attribute__((packed)) user_response_mrs_msdg_t { uint16_t MR0; // Value of DDR mode register MR0 for all ranks, all devices uint16_t MR1[TRAINING_RESPONSE_NUM_RANKS]; // Value of DDR mode register MR1 for each rank (up to 4 ranks) @@ -705,7 +708,7 @@ typedef struct user_response_mrs_msdg_t /// @class user_response_rc_msdg_t /// @brief RCD response structure /// -typedef struct user_response_rc_msdg_t +typedef struct __attribute__((packed)) user_response_rc_msdg_t { uint8_t F0RC_D0[TRAINING_RESPONSE_NUM_RC]; // RCD control words for DIMM0; Invalid for UDIMM // F0RC_D0[15:0] BIT [3:0]: 4-bit value of F0RC00~F0RC0F @@ -725,7 +728,7 @@ typedef struct user_response_rc_msdg_t /// @class user_response_msdg_t /// @brief Microchip response structure /// -typedef struct user_response_msdg +typedef struct __attribute__((packed)) user_response_msdg { uint32_t version_number; user_response_timing_msdg_t tm_resp; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C index 5e140b120..9157b1583 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C @@ -457,19 +457,36 @@ fapi2::ReturnCode host_fw_response_struct_from_little_endian(std::vector<uint8_t host_fw_response_struct& o_response) { uint32_t l_idx = 0; + + uint8_t l_response_id = 0; + uint8_t l_response_flags = 0; + uint16_t l_request_identifier = 0; + uint32_t l_response_length = 0; + uint32_t l_response_crc = 0; + uint32_t l_host_work_area = 0; + uint32_t l_response_header_crc = 0; + FAPI_TRY(correctMMIOEndianForStruct(i_data)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.response_id)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.response_flags)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.request_identifier)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.response_length)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.response_crc)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.host_work_area)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_response_id)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_response_flags)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_request_identifier)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_response_length)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_response_crc)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_host_work_area)); FAPI_TRY(readCrctEndianArray(i_data, RSP_PADDING_SIZE, l_idx, o_response.padding)); FAPI_TRY(readCrctEndianArray(i_data, ARGUMENT_SIZE, l_idx, o_response.response_argument)); + o_response.response_id = l_response_id; + o_response.response_flags = l_response_flags; + o_response.request_identifier = l_request_identifier; + o_response.response_length = l_response_length; + o_response.response_crc = l_response_crc; + o_response.host_work_area = l_host_work_area; + o_crc = crc32_gen(i_data, l_idx); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.response_header_crc)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_response_header_crc)); + o_response.response_header_crc = l_response_header_crc; fapi_try_exit: return fapi2::current_err; @@ -636,25 +653,58 @@ fapi_try_exit: fapi2::ReturnCode sensor_cache_struct_from_little_endian(std::vector<uint8_t>& i_data, sensor_cache_struct& o_data) { + // Local variables to avoid error in passing packed struct fields by reference uint32_t l_idx = 0; + uint16_t l_status = 0; + uint16_t l_ocmb_dts = 0; + uint16_t l_mem_dts0 = 0; + uint16_t l_mem_dts1 = 0; + uint32_t l_mba_reads = 0; + uint32_t l_mba_writes = 0; + uint32_t l_mba_activations = 0; + uint32_t l_mba_powerups = 0; + uint8_t l_self_timed_refresh = 0; + uint32_t l_frame_count = 0; + uint32_t l_mba_arrival_histo_base = 0; + uint32_t l_mba_arrival_histo_low = 0; + uint32_t l_mba_arrival_histo_med = 0; + uint32_t l_mba_arrival_histo_high = 0; + uint8_t l_initial_packet1 = 0; FAPI_TRY(correctMMIOEndianForStruct(i_data)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.status)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.ocmb_dts)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mem_dts0)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mem_dts1)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_reads)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_writes)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_activations)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_powerups)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.self_timed_refresh)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_status)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_ocmb_dts)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mem_dts0)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mem_dts1)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_reads)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_writes)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_activations)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_powerups)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_self_timed_refresh)); FAPI_TRY(readCrctEndianArray(i_data, SENSOR_CACHE_PADDING_SIZE_0, l_idx, o_data.reserved0)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.frame_count)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_arrival_histo_base)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_arrival_histo_low)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_arrival_histo_med)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_arrival_histo_high)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.initial_packet1)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_frame_count)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_arrival_histo_base)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_arrival_histo_low)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_arrival_histo_med)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_arrival_histo_high)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_initial_packet1)); + + o_data.frame_count = l_frame_count; + o_data.mba_arrival_histo_base = l_mba_arrival_histo_base; + o_data.mba_arrival_histo_low = l_mba_arrival_histo_low; + o_data.mba_arrival_histo_med = l_mba_arrival_histo_med; + o_data.mba_arrival_histo_high = l_mba_arrival_histo_high; + o_data.initial_packet1 = l_initial_packet1; + o_data.status = l_status; + o_data.ocmb_dts = l_ocmb_dts; + o_data.mem_dts0 = l_mem_dts0; + o_data.mem_dts1 = l_mem_dts1; + o_data.mba_reads = l_mba_reads; + o_data.mba_writes = l_mba_writes; + o_data.mba_activations = l_mba_activations; + o_data.mba_powerups = l_mba_powerups; + o_data.self_timed_refresh = l_self_timed_refresh; + FAPI_TRY(readCrctEndianArray(i_data, SENSOR_CACHE_PADDING_SIZE_1, l_idx, o_data.reserved1)); fapi_try_exit: diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H index aa6328646..ff72e2e65 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H @@ -83,6 +83,56 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::ATTR_EFF_BASE_CASE> {} /// /// @brief Traits for attr_engine /// @class attrEngineTraits +/// @note attr_eff_engine_fields, ADDRESS_MIRROR specialization +/// +template<> +struct attrEngineTraits<exp::attr_eff_engine_fields, exp::ADDRESS_MIRROR> +{ + using attr_type = fapi2::ATTR_MEM_EXP_DRAM_ADDRESS_MIRRORING_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EXP_DRAM_ADDRESS_MIRRORING_TargetType; + static constexpr exp::ffdc_codes FFDC_CODE = exp::SET_EXP_DRAM_ADDRESS_MIRRORING; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_exp_dram_address_mirroring(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_exp_dram_address_mirroring(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.address_mirroring(o_setting); + } +}; + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits /// @note attr_eff_engine_fields, BYTE_ENABLES specialization /// template<> @@ -504,57 +554,6 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::MRAM_SUPPORT> /// /// @brief Traits for attr_engine /// @class attrEngineTraits -/// @note attr_eff_engine_fields, HEIGHT_3DS specialization -/// -template<> -struct attrEngineTraits<exp::attr_eff_engine_fields, exp::HEIGHT_3DS> -{ - using attr_type = fapi2::ATTR_MEM_EXP_3DS_HEIGHT_Type; - using attr_integral_type = std::remove_all_extents<attr_type>::type; - static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EXP_3DS_HEIGHT_TargetType; - static constexpr exp::ffdc_codes FFDC_CODE = exp::SET_3DS_HEIGHT; - - /// - /// @brief attribute getter - /// @param[in] i_target the fapi2 target - /// @param[out] o_setting array to populate - /// @return FAPI2_RC_SUCCESS iff okay - /// - static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, - attr_type& o_setting) - { - return mss::attr::get_exp_3ds_height(i_target, o_setting); - } - - /// - /// @brief attribute setter - /// @param[in] i_target the fapi2 target - /// @param[in] i_setting array to set - /// @return FAPI2_RC_SUCCESS iff okay - /// - static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - attr_type& i_setting) - { - return mss::attr::set_exp_3ds_height(i_target, i_setting); - } - - /// - /// @brief Computes setting for attribute - /// @param[in] i_spd_data EFD data - /// @param[out] o_setting value we want to set attr with - /// @return FAPI2_RC_SUCCESS iff okay - /// - static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, - attr_integral_type& o_setting) - { - - return fapi2::FAPI2_RC_SUCCESS; - } -}; - -/// -/// @brief Traits for attr_engine -/// @class attrEngineTraits /// @note attr_eff_engine_fields, SPD_CL_SUPPORTED specialization /// template<> diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C index d649e50c4..a0b62b533 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C @@ -116,25 +116,63 @@ fapi_try_exit: } /// -/// @brief Processes the Host RD VREF DQ +/// @brief Processes the Host INIT RD VREF DQ /// @param[in] i_target the target on which to operate /// @param[in] i_efd_data the EFD data to process /// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// @note this is pulled in for exp_draminit. The individual fields are pulled into the SI engine /// -fapi2::ReturnCode host_rd_vref_dq(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +fapi2::ReturnCode init_vref_dq(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) { + // See Byte 44 of SPD Document (Bit 6 from right = Bit 1 from left) + static const uint8_t VREF_RANGE_BIT_LEFT_ALGINED = 1; + // Get the data - uint8_t l_vref = 0; - const auto& l_port = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target); + uint8_t l_phy_vref[mss::exp::sizes::MAX_RANK_PER_DIMM] = {0}; + + uint8_t l_range = 0; + uint8_t l_value = 0; + fapi2::buffer<uint8_t> l_combined_vref; + + FAPI_TRY(mss::attr::get_exp_init_vref_dq(i_target, l_phy_vref)); + + // Piece together the field + FAPI_TRY(i_efd_data->wr_vref_dq_range(l_range)); + FAPI_TRY(i_efd_data->wr_vref_dq_value(l_value)); + + l_combined_vref = l_value; + l_combined_vref.writeBit<VREF_RANGE_BIT_LEFT_ALGINED>(l_range); + + // Insert + l_phy_vref[i_efd_data->get_rank()] = l_combined_vref; + + // Set the attribute + FAPI_TRY(mss::attr::set_exp_init_vref_dq(i_target, l_phy_vref)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the Host INIT PHY VREF +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode init_phy_vref(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_phy_vref[mss::exp::sizes::MAX_RANK_PER_DIMM] = {0}; - FAPI_TRY(mss::attr::get_exp_init_vref_dq(l_port, l_vref)); + FAPI_TRY(mss::attr::get_exp_init_phy_vref(i_target, l_phy_vref)); // Update the values - FAPI_TRY(i_efd_data->phy_vref_percent(l_vref)); + FAPI_TRY(i_efd_data->init_phy_vref(l_phy_vref[i_efd_data->get_rank()])); // Set the attribute - FAPI_TRY(mss::attr::set_exp_init_vref_dq(l_port, l_vref)); + FAPI_TRY(mss::attr::set_exp_init_phy_vref(i_target, l_phy_vref)); fapi_try_exit: return fapi2::current_err; @@ -220,7 +258,8 @@ fapi_try_exit: fapi2::ReturnCode process(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) { - FAPI_TRY(host_rd_vref_dq(i_target, i_efd_data)); + FAPI_TRY(init_vref_dq(i_target, i_efd_data)); + FAPI_TRY(init_phy_vref(i_target, i_efd_data)); FAPI_TRY(cs_cmd_latency(i_target, i_efd_data)); FAPI_TRY(ca_parity_latency(i_target, i_efd_data)); FAPI_TRY(dfimrl_ddrclk(i_target, i_efd_data)); diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.H index e7c13efaa..2f7c5cc14 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.H @@ -53,13 +53,23 @@ namespace efd { /// -/// @brief Processes the CAC delay A side +/// @brief Processes the Host INIT RD VREF DQ /// @param[in] i_target the target on which to operate /// @param[in] i_efd_data the EFD data to process /// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// @note this is pulled in for exp_draminit. The individual fields are pulled into the SI engine /// -fapi2::ReturnCode cac_delay_a(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); +fapi2::ReturnCode init_vref_dq(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the Host INIT PHY VREF +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode init_phy_vref(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); /// /// @brief Processes the CAC delay A side @@ -67,17 +77,17 @@ fapi2::ReturnCode cac_delay_a(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_ta /// @param[in] i_efd_data the EFD data to process /// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully /// -fapi2::ReturnCode cac_delay_b(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, +fapi2::ReturnCode cac_delay_a(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); /// -/// @brief Processes the Host RD VREF DQ +/// @brief Processes the CAC delay A side /// @param[in] i_target the target on which to operate /// @param[in] i_efd_data the EFD data to process /// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully /// -fapi2::ReturnCode host_rd_vref_dq(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); +fapi2::ReturnCode cac_delay_b(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); /// /// @brief Processes the CS command latency diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H index 4309c7fe4..fac27601b 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H @@ -161,9 +161,9 @@ struct phy_params_t /// uint32_t iv_version_number; uint8_t iv_dimm_type[MAX_DIMM_PER_PORT]; - uint16_t iv_chip_select; + uint8_t iv_chip_select[MAX_DIMM_PER_PORT]; uint8_t iv_dram_data_width[MAX_DIMM_PER_PORT]; - uint16_t iv_height_3DS; + uint16_t iv_height_3DS[MAX_DIMM_PER_PORT]; uint16_t iv_dbyte_macro[MAX_DIMM_PER_PORT]; uint32_t iv_nibble[MAX_DIMM_PER_PORT]; uint8_t iv_addr_mirror[MAX_DIMM_PER_PORT]; @@ -194,8 +194,8 @@ struct phy_params_t uint8_t iv_dram_dic[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_dram_preamble[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_phy_equalization[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; - uint8_t iv_init_vref_dq; - uint16_t iv_init_phy_vref; + uint8_t iv_init_vref_dq[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_init_phy_vref[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_odt_wr_map_cs[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_odt_rd_map_cs[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_geardown_mode[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; @@ -244,9 +244,9 @@ class phy_params uint8_t l_master_ranks[MAX_DIMM_PER_PORT] = {}; // Fetch attributes and populate the member variables FAPI_TRY(mss::attr::get_dimm_type(i_target, iv_params.iv_dimm_type)); - FAPI_TRY(mss::attr::get_exp_cs_present(i_target, iv_params.iv_chip_select)); + FAPI_TRY(mss::attr::get_dimm_ranks_configed(i_target, iv_params.iv_chip_select)); FAPI_TRY(mss::attr::get_dram_width(i_target, iv_params.iv_dram_data_width)); - FAPI_TRY(mss::attr::get_exp_3ds_height(i_target, iv_params.iv_height_3DS)); + FAPI_TRY(mss::attr::get_3ds_height(i_target, iv_params.iv_height_3DS)); FAPI_TRY(mss::attr::get_byte_enables(i_target, iv_params.iv_dbyte_macro)); FAPI_TRY(mss::attr::get_nibble_enables(i_target, iv_params.iv_nibble)); FAPI_TRY(mss::attr::get_exp_dram_address_mirroring(i_target, iv_params.iv_addr_mirror)); @@ -378,7 +378,14 @@ class phy_params /// fapi2::ReturnCode setup_CsPresent(user_input_msdg& io_phy_params) const { - io_phy_params.CsPresent = iv_params.iv_chip_select; + fapi2::buffer<uint8_t> l_cs_present(iv_params.iv_chip_select[0]); + + // Flip buffer (Needs to be right aligned, currently 0bXXXX0000) + l_cs_present.reverse(); + + // Now extend to 16 bits for phy_params struct + io_phy_params.CsPresent = static_cast<uint16_t>(l_cs_present); + return fapi2::FAPI2_RC_SUCCESS; } @@ -428,21 +435,21 @@ class phy_params /// fapi2::ReturnCode setup_Height3DS(user_input_msdg& io_phy_params) const { - switch (iv_params.iv_height_3DS) + switch (iv_params.iv_height_3DS[0]) { - case fapi2::ENUM_ATTR_MEM_EXP_3DS_HEIGHT_PLANAR: + case fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_PLANAR: io_phy_params.Height3DS = MSDG_PLANAR; break; - case fapi2::ENUM_ATTR_MEM_EXP_3DS_HEIGHT_H2: + case fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H2: io_phy_params.Height3DS = MSDG_H2; break; - case fapi2::ENUM_ATTR_MEM_EXP_3DS_HEIGHT_H4: + case fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H4: io_phy_params.Height3DS = MSDG_H4; break; - case fapi2::ENUM_ATTR_MEM_EXP_3DS_HEIGHT_H8: + case fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H8: io_phy_params.Height3DS = MSDG_H8; break; @@ -452,9 +459,9 @@ class phy_params fapi2::MSS_EXP_DRAMINIT_UNSUPPORTED_3DS_HEIGHT(). set_OCMB_TARGET(l_ocmb). set_PORT(iv_target). - set_HEIGHT(iv_params.iv_height_3DS), + set_HEIGHT(iv_params.iv_height_3DS[0]), "%s 3DS Height is not a supported (%d)", - mss::c_str(iv_target), iv_params.iv_height_3DS); + mss::c_str(iv_target), iv_params.iv_height_3DS[0]); break; } @@ -604,7 +611,8 @@ class phy_params /// fapi2::ReturnCode set_Frequency(user_input_msdg& io_phy_params) const { - io_phy_params.Frequency[0] = static_cast<uint16_t>(iv_params.iv_frequency); + // Divide by 2 to convert from DRAM freq to MEMCLK freq + io_phy_params.Frequency[0] = static_cast<uint16_t>(iv_params.iv_frequency / 2); return fapi2::FAPI2_RC_SUCCESS; } @@ -804,7 +812,7 @@ class phy_params /// fapi2::ReturnCode set_InitVrefDQ(user_input_msdg& io_phy_params) const { - io_phy_params.InitVrefDQ[0] = iv_params.iv_init_vref_dq; + io_phy_params.InitVrefDQ[0] = iv_params.iv_init_vref_dq[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -815,9 +823,7 @@ class phy_params /// fapi2::ReturnCode set_InitPhyVref(user_input_msdg& io_phy_params) const { - // Attr Vref = percentage of VDDQ, Receiver Vref = VDDQ*PhyVref[6:0]/128 - // conversion is attr_value * 128 / 100 - io_phy_params.InitPhyVref[0] = iv_params.iv_init_phy_vref * 128 / 100; + io_phy_params.InitPhyVref[0] = iv_params.iv_init_phy_vref[0][0]; return fapi2::FAPI2_RC_SUCCESS; } diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C index 0418b59d1..14b6f5e36 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C @@ -102,27 +102,43 @@ fapi2::ReturnCode read_training_response(const fapi2::Target<fapi2::TARGET_TYPE_ // True if we pass // We assert at the end to avoid LOTS of fapi asserts uint32_t l_idx = 0; - bool l_pass = readLE(i_data, l_idx, o_resp.version_number); + + uint32_t l_version_number = 0; + bool l_pass = readLE(i_data, l_idx, l_version_number); + o_resp.version_number = l_version_number; + + uint16_t l_DFIMRL_DDRCLK_trained = 0; // Reads in the timing portion of the training response - l_pass &= readLE(i_data, l_idx, o_resp.tm_resp.DFIMRL_DDRCLK_trained); + l_pass &= readLE(i_data, l_idx, l_DFIMRL_DDRCLK_trained); l_pass &= readLEArray(i_data, TIMING_RESPONSE_2D_ARRAY_SIZE, l_idx, &o_resp.tm_resp.CDD_RR[0][0]); l_pass &= readLEArray(i_data, TIMING_RESPONSE_2D_ARRAY_SIZE, l_idx, &o_resp.tm_resp.CDD_WW[0][0]); l_pass &= readLEArray(i_data, TIMING_RESPONSE_2D_ARRAY_SIZE, l_idx, &o_resp.tm_resp.CDD_RW[0][0]); l_pass &= readLEArray(i_data, TIMING_RESPONSE_2D_ARRAY_SIZE, l_idx, &o_resp.tm_resp.CDD_WR[0][0]); + // Write to user_response_msdg + o_resp.tm_resp.DFIMRL_DDRCLK_trained = l_DFIMRL_DDRCLK_trained; + // Error response l_pass &= readLEArray(i_data, 80, l_idx, o_resp.err_resp.Failure_Lane); + uint16_t l_MR0 = 0; + uint16_t l_MR3 = 0; + uint16_t l_MR4 = 0; + // MRS response - l_pass &= readLE(i_data, l_idx, o_resp.mrs_resp.MR0); + l_pass &= readLE(i_data, l_idx, l_MR0); l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RANKS, l_idx, o_resp.mrs_resp.MR1); l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RANKS, l_idx, o_resp.mrs_resp.MR2); - l_pass &= readLE(i_data, l_idx, o_resp.mrs_resp.MR3); - l_pass &= readLE(i_data, l_idx, o_resp.mrs_resp.MR4); + l_pass &= readLE(i_data, l_idx, l_MR3); + l_pass &= readLE(i_data, l_idx, l_MR4); l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RANKS, l_idx, o_resp.mrs_resp.MR5); l_pass &= readLEArray(i_data, TRAINING_RESPONSE_MR6_SIZE, l_idx, &o_resp.mrs_resp.MR6[0][0]); + o_resp.mrs_resp.MR0 = l_MR0; + o_resp.mrs_resp.MR3 = l_MR3; + o_resp.mrs_resp.MR4 = l_MR4; + // Register Control Word (RCW) response l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RC, l_idx, o_resp.rc_resp.F0RC_D0); l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RC, l_idx, o_resp.rc_resp.F1RC_D0); diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H index 0678d94af..89e1be775 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H @@ -106,11 +106,11 @@ enum attr_eff_engine_fields TSV_8H_SUPPORT = 6, PSTATES = 7, MRAM_SUPPORT = 8, - HEIGHT_3DS = 9, - SPD_CL_SUPPORTED = 10, + SPD_CL_SUPPORTED = 9, + ADDRESS_MIRROR = 10, // Dispatcher set to last enum value - ATTR_EFF_DISPATCHER = SPD_CL_SUPPORTED, + ATTR_EFF_DISPATCHER = ADDRESS_MIRROR, }; /// @@ -138,6 +138,7 @@ enum ffdc_codes READ_CRCT_ENDIAN = 0x0005, READ_TRAINING_RESPONSE_STRUCT = 0x0006, + SET_EXP_DRAM_ADDRESS_MIRRORING = 0x1040, SET_BYTE_ENABLES = 0x1041, SET_NIBBLE_ENABLES = 0x1042, SET_TAA_MIN = 0x1043, @@ -147,9 +148,8 @@ enum ffdc_codes SET_VREF_DQ_TRAIN_RANGE = 0x1047, SET_PSTATES = 0x1048, SET_MRAM_SUPPORT = 0x1049, - SET_3DS_HEIGHT = 0x1050, - SET_SPD_CL_SUPPORTED = 0x1051, - SET_SERDES_FREQ = 0x1052, + SET_SPD_CL_SUPPORTED = 0x1050, + SET_SERDES_FREQ = 0x1051, }; /// diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml index 53d061536..65f900633 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml @@ -146,18 +146,6 @@ <!-- user_input_msdg attribute overrides start --> <attribute> - <id>ATTR_MEM_EXP_CS_PRESENT</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Indicate presence of DRAM at each Chip Select for PHY - </description> - <initToZero></initToZero> - <valueType>uint16</valueType> - <writeable/> - <mssAccessorName>exp_cs_present</mssAccessorName> - </attribute> - - <attribute> <id>ATTR_MEM_EXP_INIT_VREF_DQ</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> @@ -166,6 +154,7 @@ <valueType>uint8</valueType> <initToZero></initToZero> <writeable/> + <array>2 4</array> <mssAccessorName>exp_init_vref_dq</mssAccessorName> </attribute> @@ -175,9 +164,10 @@ <description> Initial DQ Vref setting of PHY before training </description> - <valueType>uint16</valueType> + <valueType>uint8</valueType> <initToZero></initToZero> <writeable/> + <array>2 4</array> <mssAccessorName>exp_init_phy_vref</mssAccessorName> </attribute> @@ -233,19 +223,6 @@ </attribute> <attribute> - <id>ATTR_MEM_EXP_3DS_HEIGHT</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Explorer setting for 3DS stack - </description> - <initToZero></initToZero> - <valueType>uint16</valueType> - <enum>PLANAR = 0, H2 = 2, H4 = 4, H8 = 8</enum> - <writeable/> - <mssAccessorName>exp_3ds_height</mssAccessorName> - </attribute> - - <attribute> <id>ATTR_MEM_EXP_SPD_CL_SUPPORTED</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> diff --git a/src/import/generic/memory/lib/data_engine/attr_engine_traits.H b/src/import/generic/memory/lib/data_engine/attr_engine_traits.H index cc61ea602..807170ceb 100644 --- a/src/import/generic/memory/lib/data_engine/attr_engine_traits.H +++ b/src/import/generic/memory/lib/data_engine/attr_engine_traits.H @@ -402,6 +402,138 @@ struct attrEngineTraits<attr_eff_engine_fields, DRAM_WIDTH> } }; +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @note attr_si_engine_fields, COLUMN_ADDR_BITS specialization +/// +template<> +struct attrEngineTraits<attr_eff_engine_fields, COLUMN_ADDR_BITS> +{ + using attr_type = fapi2::ATTR_MEM_EFF_DRAM_COLUMN_BITS_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DRAM_COLUMN_BITS_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_COL_ADDR_BITS; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_dram_column_bits(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_dram_column_bits(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_efd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_ADDR_COL_MAP = + { + {0b001, fapi2::ENUM_ATTR_MEM_EFF_DRAM_COLUMN_BITS_NUM10}, + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + + attr_integral_type l_value = 0; + FAPI_TRY(i_spd_data.column_address_bits(l_value)) + + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_dimm, DRAM_ADDR_COL_MAP, SET_COL_ADDR_BITS, l_value, o_setting)); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @note attr_si_engine_fields, ROW_ADDR_BITS specialization +/// +template<> +struct attrEngineTraits<attr_eff_engine_fields, ROW_ADDR_BITS> +{ + using attr_type = fapi2::ATTR_MEM_EFF_DRAM_ROW_BITS_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DRAM_ROW_BITS_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_ROW_ADDR_BITS; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_dram_row_bits(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_dram_row_bits(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_efd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_ADDR_ROW_MAP = + { + {0b010, fapi2::ENUM_ATTR_MEM_EFF_DRAM_ROW_BITS_NUM14}, + {0b011, fapi2::ENUM_ATTR_MEM_EFF_DRAM_ROW_BITS_NUM15}, + {0b100, fapi2::ENUM_ATTR_MEM_EFF_DRAM_ROW_BITS_NUM16}, + {0b101, fapi2::ENUM_ATTR_MEM_EFF_DRAM_ROW_BITS_NUM17}, + {0b110, fapi2::ENUM_ATTR_MEM_EFF_DRAM_ROW_BITS_NUM18}, + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + + attr_integral_type l_value = 0; + FAPI_TRY(i_spd_data.row_address_bits(l_value)) + + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_dimm, DRAM_ADDR_ROW_MAP, SET_ROW_ADDR_BITS, l_value, o_setting)); + + fapi_try_exit: + return fapi2::current_err; + } +}; + // // SI parameters // @@ -1162,107 +1294,24 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_DRV_IMP_DQ_DQS> static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, attr_integral_type& o_setting) { - return i_efd_data->dram_dic(o_setting); - } -}; - -/// -/// @brief Traits for attr_engine -/// @class attrEngineTraits -/// @note attr_si_engine_fields, SI_VREF_DQ_TRAIN_RANGE specialization -/// -template<> -struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_RANGE> -{ - using attr_type = fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE_Type; - using attr_integral_type = std::remove_all_extents<attr_type>::type; - static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE_TargetType; - static constexpr generic_ffdc_codes FFDC_CODE = SET_SI_VREF_DQ_TRAIN_RANGE; - - /// - /// @brief attribute getter - /// @param[in] i_target the fapi2 target - /// @param[out] o_setting array to populate - /// @return FAPI2_RC_SUCCESS iff okay - /// - static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, - attr_type& o_setting) - { - return mss::attr::get_si_vref_dq_train_range(i_target, o_setting); - } - - /// - /// @brief attribute setter - /// @param[in] i_target the fapi2 target - /// @param[in] i_setting array to set - /// @return FAPI2_RC_SUCCESS iff okay - /// - static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - attr_type& i_setting) - { - return mss::attr::set_si_vref_dq_train_range(i_target, i_setting); - } - - /// - /// @brief Computes setting for attribute - /// @param[in] i_efd_data EFD data - /// @param[out] o_setting value we want to set attr with - /// @return FAPI2_RC_SUCCESS iff okay - /// - static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, - attr_integral_type& o_setting) - { - return i_efd_data->wr_vref_dq_range(o_setting); - } -}; + static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_DIC_MAP = + { + // {key byte, capacity in GBs} + {0, fapi2::ENUM_ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS_DISABLE}, + {1, fapi2::ENUM_ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS_OHM34}, + {2, fapi2::ENUM_ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS_OHM48}, + }; -/// -/// @brief Traits for attr_engine -/// @class attrEngineTraits -/// @note attr_si_engine_fields, SI_VREF_DQ_TRAIN_VALUE specialization -/// -template<> -struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_VALUE> -{ - using attr_type = fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE_Type; - using attr_integral_type = std::remove_all_extents<attr_type>::type; - static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE_TargetType; - static constexpr generic_ffdc_codes FFDC_CODE = SET_SI_VREF_DQ_TRAIN_VALUE; + const auto l_ocmb = i_efd_data->get_ocmb_target(); - /// - /// @brief attribute getter - /// @param[in] i_target the fapi2 target - /// @param[out] o_setting array to populate - /// @return FAPI2_RC_SUCCESS iff okay - /// - static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, - attr_type& o_setting) - { - return mss::attr::get_si_vref_dq_train_value(i_target, o_setting); - } + attr_integral_type l_dram_dic = 0; + FAPI_TRY(i_efd_data->dram_dic(l_dram_dic)) - /// - /// @brief attribute setter - /// @param[in] i_target the fapi2 target - /// @param[out] o_setting array to populate - /// @return FAPI2_RC_SUCCESS iff okay - /// - static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - attr_type& o_setting) - { - return mss::attr::set_si_vref_dq_train_value(i_target, o_setting); - } + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(l_ocmb, DRAM_DIC_MAP, SET_SI_DRAM_DRV_IMP_DQ_DQS, l_dram_dic, o_setting)); - /// - /// @brief Computes setting for attribute - /// @param[in] i_efd_data EFD data - /// @param[out] o_setting value we want to set attr with - /// @return FAPI2_RC_SUCCESS iff okay - /// - static inline fapi2::ReturnCode get_value_to_set(const std::shared_ptr<efd::base_decoder>& i_efd_data, - attr_integral_type& o_setting) - { - return i_efd_data->wr_vref_dq_value(o_setting); + fapi_try_exit: + return fapi2::current_err; } }; @@ -1627,6 +1676,78 @@ struct attrEngineTraits<attr_engine_derived_fields, MEM_DIMM_SIZE> } }; +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @note attr_engine_derived_fields, HEIGHT_3DS specialization +/// +template<> +struct attrEngineTraits<attr_engine_derived_fields, HEIGHT_3DS> +{ + using attr_type = fapi2::ATTR_MEM_3DS_HEIGHT_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_3DS_HEIGHT_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_3DS_HEIGHT; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_3ds_height(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_3ds_height(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + uint8_t l_master_ranks_per_dimm = 0; + uint8_t l_logical_ranks_per_dimm = 0; + + FAPI_TRY(mss::attr::get_num_master_ranks_per_dimm(i_target, l_master_ranks_per_dimm)); + FAPI_TRY(mss::attr::get_logical_ranks_per_dimm(i_target, l_logical_ranks_per_dimm)); + { + uint16_t l_result = l_logical_ranks_per_dimm / l_master_ranks_per_dimm; + + static const std::vector< std::pair<uint16_t, uint16_t> > HEIGHT_3DS_MAP = + { + // {key byte, device width (bits)} + {1, fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_PLANAR}, + {2, fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H2}, + {4, fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H4}, + {8, fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H8}, + // All others reserved + }; + + // Map SPD value to desired setting + FAPI_TRY(lookup_table_check(i_target, HEIGHT_3DS_MAP, mss::SET_3DS_HEIGHT, l_result, o_setting)); + } + fapi_try_exit: + return fapi2::current_err; + } +}; + }//mss #endif diff --git a/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H b/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H index 813abbe33..911821b5f 100644 --- a/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H +++ b/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H @@ -98,9 +98,11 @@ enum attr_eff_engine_fields DRAM_DENSITY = 3, PRIMARY_DIE_COUNT = 4, PRIM_STACK_TYPE = 5, + COLUMN_ADDR_BITS = 6, + ROW_ADDR_BITS = 7, // Dispatcher set to last enum value - ATTR_EFF_DISPATCHER = PRIM_STACK_TYPE, + ATTR_EFF_DISPATCHER = ROW_ADDR_BITS, }; /// @@ -127,11 +129,9 @@ enum attr_si_engine_fields SI_DRAM_PREAMBLE = 13, SI_MC_DRV_EQ_DQ_DQS = 14, SI_DRAM_DRV_IMP_DQ_DQS = 15, - SI_VREF_DQ_TRAIN_RANGE = 16, - SI_VREF_DQ_TRAIN_VALUE = 17, - SI_ODT_WR = 18, - SI_ODT_RD = 19, - SI_GEARDOWN_MODE = 20, + SI_ODT_WR = 16, + SI_ODT_RD = 17, + SI_GEARDOWN_MODE = 18, // Dispatcher set to last enum value ATTR_SI_DISPATCHER = SI_GEARDOWN_MODE, @@ -154,7 +154,8 @@ enum attr_engine_derived_fields // Attrs to set MEM_DIMM_SIZE = 1, - LOGICAL_RANKS = 2, + HEIGHT_3DS = 2, // HEIGHT_3DS must be calculated after LOGICAL_RANKS + LOGICAL_RANKS = 3, // Dispatcher set to last enum value ATTR_DERIVED_DISPATCHER = LOGICAL_RANKS, diff --git a/src/import/generic/memory/lib/mss_generic_attribute_getters.H b/src/import/generic/memory/lib/mss_generic_attribute_getters.H index fd953e84e..ecc9af5ff 100644 --- a/src/import/generic/memory/lib/mss_generic_attribute_getters.H +++ b/src/import/generic/memory/lib/mss_generic_attribute_getters.H @@ -2138,6 +2138,52 @@ fapi_try_exit: } /// +/// @brief ATTR_MEM_3DS_HEIGHT getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint16_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Setting for 3DS stack. Calculated from logical_ranks / master_ranks +/// +inline fapi2::ReturnCode get_3ds_height(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint16_t& o_value) +{ + uint16_t l_value[2] = {}; + const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_3DS_HEIGHT, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_3DS_HEIGHT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_3DS_HEIGHT getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint16_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Setting for 3DS stack. Calculated from logical_ranks / master_ranks +/// +inline fapi2::ReturnCode get_3ds_height(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint16_t (&o_array)[2]) +{ + uint16_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_3DS_HEIGHT, i_target, l_value) ); + memcpy(o_array, &l_value, 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_3DS_HEIGHT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// /// @brief ATTR_MEM_EFF_REGISTER_TYPE getter /// @param[in] const ref to the TARGET_TYPE_DIMM /// @param[out] uint8_t& reference to store the value @@ -3288,100 +3334,6 @@ fapi_try_exit: } /// -/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE getter -/// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t&[] array reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note ARRAY[DIMM][RANK] vrefdq_train value. This is for DDR4 MRS6. -/// -inline fapi2::ReturnCode get_si_vref_dq_train_value(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t (&o_array)[4]) -{ - uint8_t l_value[2][4] = {}; - const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE, l_port, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t&[] array reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note ARRAY[DIMM][RANK] vrefdq_train value. This is for DDR4 MRS6. -/// -inline fapi2::ReturnCode get_si_vref_dq_train_value(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[2][4]) -{ - uint8_t l_value[2][4] = {}; - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE, i_target, l_value) ); - memcpy(o_array, &l_value, 8); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE getter -/// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t&[] array reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note ARRAY[DIMM][RANK] vrefdq_train range. This is for DDR4 MRS6. -/// -inline fapi2::ReturnCode get_si_vref_dq_train_range(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - uint8_t (&o_array)[4]) -{ - uint8_t l_value[2][4] = {}; - const auto l_port = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>(); - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE, l_port, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t&[] array reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note ARRAY[DIMM][RANK] vrefdq_train range. This is for DDR4 MRS6. -/// -inline fapi2::ReturnCode get_si_vref_dq_train_range(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - uint8_t (&o_array)[2][4]) -{ - uint8_t l_value[2][4] = {}; - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE, i_target, l_value) ); - memcpy(o_array, &l_value, 8); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// /// @brief ATTR_MEM_SI_GEARDOWN_MODE getter /// @param[in] const ref to the TARGET_TYPE_DIMM /// @param[out] uint8_t&[] array reference to store the value diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H index cd904ef9b..213293fdd 100644 --- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H +++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_ddr4_custom_microchip_decoder.H @@ -489,26 +489,26 @@ class decoder<mss::spd::device_type::DDR4, DDR4_CUSTOM_MICROCHIP, R > : public b } /// - /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_RANGE + /// @brief Decodes Host RD VREF DQ -> INIT_PHY_VREF /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode wr_vref_dq_range(uint8_t& o_output) const override + virtual fapi2::ReturnCode init_phy_vref(uint8_t& o_output) const override { - FAPI_TRY(( reader<fields_t::WR_VREF_DQ_RANGE, R>(iv_target, iv_data, o_output)) ); + FAPI_TRY( (reader<fields_t::INIT_PHY_VREF, R>(iv_target, iv_data, o_output)) ); fapi_try_exit: return fapi2::current_err; } /// - /// @brief Decodes Host RD VREF DQ -> PHY_VREF_PERCENT + /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_RANGE /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode phy_vref_percent(uint8_t& o_output) const + virtual fapi2::ReturnCode wr_vref_dq_range(uint8_t& o_output) const override { - FAPI_TRY( (reader<fields_t::PHY_VREF_PERCENT, R>(iv_target, iv_data, o_output)) ); + FAPI_TRY(( reader<fields_t::WR_VREF_DQ_RANGE, R>(iv_target, iv_data, o_output)) ); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H index d59aac75f..9a1415a75 100644 --- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H +++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_fields_ddr4.H @@ -244,16 +244,16 @@ class fields<mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP> PHY_EQUALIZATION_LEN = 2, // Byte 44: Initial WR VREF DQ setting - WR_VREF_DQ_BYTE = 44, + INIT_VREF_DQ_BYTE = 44, WR_VREF_DQ_RANGE_START = 1, WR_VREF_DQ_RANGE_LEN = 1, WR_VREF_DQ_VALUE_START = 2, WR_VREF_DQ_VALUE_LEN = 6, // Byte 45: Host RD VREF DQ - RD_VREF_DQ_BYTE = 45, - PHY_VREF_PERCENT_START = 1, - PHY_VREF_PERCENT_LEN = 7, + INIT_PHY_VREF_BYTE = 45, + INIT_PHY_VREF_START = 1, + INIT_PHY_VREF_LEN = 7, // Byte 46: ODT WR Map CS Byte1 ODT_WR_MAP1_BYTE = 46, @@ -554,12 +554,12 @@ class fields<mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP> // Byte 43: PHY Equalization static constexpr field_t PHY_EQUALIZATION{PHY_EQUALIZATION_BYTE, PHY_EQUALIZATION_START, PHY_EQUALIZATION_LEN}; - // Byte 44: Initial WR VREF DQ setting - static constexpr field_t WR_VREF_DQ_RANGE{WR_VREF_DQ_BYTE, WR_VREF_DQ_RANGE_START, WR_VREF_DQ_RANGE_LEN}; - static constexpr field_t WR_VREF_DQ_VALUE{WR_VREF_DQ_BYTE, WR_VREF_DQ_VALUE_START, WR_VREF_DQ_VALUE_LEN}; + // Byte 44: Initial VREF DQ setting + static constexpr field_t WR_VREF_DQ_RANGE{INIT_VREF_DQ_BYTE, WR_VREF_DQ_RANGE_START, WR_VREF_DQ_RANGE_LEN}; + static constexpr field_t WR_VREF_DQ_VALUE{INIT_VREF_DQ_BYTE, WR_VREF_DQ_VALUE_START, WR_VREF_DQ_VALUE_LEN}; - // Byte 45: Host RD VREF DQ - static constexpr field_t PHY_VREF_PERCENT{RD_VREF_DQ_BYTE, PHY_VREF_PERCENT_START, PHY_VREF_PERCENT_LEN}; + // Byte 45: Initial PHY VREF setting + static constexpr field_t INIT_PHY_VREF{INIT_PHY_VREF_BYTE, INIT_PHY_VREF_START, INIT_PHY_VREF_LEN}; // Byte 46: ODT WR Map CS Byte1 static constexpr field_t ODT_WR_MAP_RANK3{ODT_WR_MAP1_BYTE, ODT_WR_MAP_RANK3_START, ODT_WR_MAP_RANK3_LEN}; diff --git a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H index 784dba0f6..1acdc554d 100644 --- a/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H +++ b/src/import/generic/memory/lib/spd/ddimm/ddr4/efd_traits_ddr4.H @@ -784,7 +784,7 @@ class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUS /// @note valid for all revs /// template< mss::spd::rev R > -class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::PHY_VREF_PERCENT, R > +class readerTraits < fields< mss::spd::device_type::DDR4, mss::efd::id::DDR4_CUSTOM_MICROCHIP>::INIT_PHY_VREF, R > { public: diff --git a/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H b/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H index 8427b5b88..df0dbed5e 100644 --- a/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H +++ b/src/import/generic/memory/lib/spd/ddimm/efd_decoder.H @@ -492,7 +492,7 @@ class base_decoder } /// - /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_RANGE + /// @brief Decodes Initial VREF DQ setting -> WR_VREF_DQ_RANGE /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// @@ -503,22 +503,22 @@ class base_decoder } /// - /// @brief Decodes Host RD VREF DQ -> PHY_VREF_PERCENT + /// @brief Decodes Initial VREF DQ setting -> WR_VREF_DQ_VALUE /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode phy_vref_percent(uint8_t& o_output) const + virtual fapi2::ReturnCode wr_vref_dq_value(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; } /// - /// @brief Decodes Initial WR VREF DQ setting -> WR_VREF_DQ_VALUE + /// @brief Decodes Initial PHY VREF -> INIT_PHY_VREF /// @param[out] o_output encoding from SPD /// @return FAPI2_RC_SUCCESS if okay /// - virtual fapi2::ReturnCode wr_vref_dq_value(uint8_t& o_output) const + virtual fapi2::ReturnCode init_phy_vref(uint8_t& o_output) const { o_output = 0; return fapi2::FAPI2_RC_SUCCESS; diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index b77cbcd47..dd56562a4 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -220,6 +220,9 @@ enum generic_ffdc_codes SET_CAC_DELAY_B = 0x1077, EFD_CA_LATENCY_MODE = 0x1080, EFD_CA_PL_MODE = 0x1081, + SET_COL_ADDR_BITS = 0x1082, + SET_ROW_ADDR_BITS = 0x1083, + SET_3DS_HEIGHT = 0x1084, // Power thermal functions diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml index 8e7b12bbf..3167e018a 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml @@ -187,6 +187,7 @@ </description> <initToZero></initToZero> <valueType>uint8</valueType> + <enum> NUM10 = 10</enum> <writeable/> <array>2</array> <mssAccessorName>dram_column_bits</mssAccessorName> @@ -588,6 +589,20 @@ <mssAccessorName>logical_ranks_per_dimm</mssAccessorName> </attribute> + <attribute> + <id>ATTR_MEM_3DS_HEIGHT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Setting for 3DS stack. Calculated from logical_ranks / master_ranks + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <enum>PLANAR = 0, H2 = 2, H4 = 4, H8 = 8</enum> + <array>2</array> + <writeable/> + <mssAccessorName>3ds_height</mssAccessorName> + </attribute> + <attribute> <id>ATTR_MEM_EFF_REGISTER_TYPE</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml index 1ec910f04..d8410a5a0 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml @@ -106,7 +106,7 @@ <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> - <enum>OHM34 = 34, OHM48 = 48</enum> + <enum>DISABLE = 0, OHM34 = 34, OHM48 = 48</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_dram_drv_imp_dq_dqs</mssAccessorName> <array>2 4</array> @@ -179,35 +179,6 @@ </attribute> <attribute> - <id>ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM][RANK] - vrefdq_train value. This is for DDR4 MRS6. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2 4</array> - <mssAccessorName>si_vref_dq_train_value</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM][RANK] - vrefdq_train range. This is for DDR4 MRS6. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>RANGE1 = 0, RANGE2 = 1</enum> - <writeable/> - <array>2 4</array> - <mssAccessorName>si_vref_dq_train_range</mssAccessorName> - </attribute> - - <attribute> <id>ATTR_MEM_SI_GEARDOWN_MODE</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> |
