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| author | Andre Marin <aamarin@us.ibm.com> | 2019-07-11 13:01:31 -0400 |
|---|---|---|
| committer | Daniel M Crowell <dcrowell@us.ibm.com> | 2019-08-09 07:56:28 -0500 |
| commit | 1061da0271bf85fe29fedff6f242181b3dc6d5ed (patch) | |
| tree | f586bdbba79f3ee934073e1bbd49981d0d29b0b0 /src/import/generic/memory/lib/spd/common | |
| parent | 9fb424b8af396bb626c28105b4383fc22aeccd94 (diff) | |
| download | talos-hostboot-1061da0271bf85fe29fedff6f242181b3dc6d5ed.tar.gz talos-hostboot-1061da0271bf85fe29fedff6f242181b3dc6d5ed.zip | |
Add missing attributes needed to be set for generic mss_kind
Setting DRAM_MFG_ID, RCD_MFG_ID, and MODULE_HEIGHT
to eff_config and editing SPD timing values to use common
API for calculations that come with values from
the EEPROM
Change-Id: If33f2f2a49a62f114575ef36d6325fc537d1dc27
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79921
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79936
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/generic/memory/lib/spd/common')
| -rw-r--r-- | src/import/generic/memory/lib/spd/common/dimm_module_decoder.H | 11 | ||||
| -rw-r--r-- | src/import/generic/memory/lib/spd/common/spd_decoder_base.H | 62 |
2 files changed, 72 insertions, 1 deletions
diff --git a/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H b/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H index 8ff2e30fa..c8ab503ec 100644 --- a/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H +++ b/src/import/generic/memory/lib/spd/common/dimm_module_decoder.H @@ -1490,6 +1490,17 @@ class dimm_module_decoder o_output = 0; return fapi2::FAPI2_RC_SUCCESS; } + + /// + /// @brief Decodes DRAM Manufacturer ID code + /// @param[out] o_value dram manufacturing id code + /// @return FAPI2_RC_SUCCESS iff okay + /// + virtual fapi2::ReturnCode dram_manufacturer_id_code( uint16_t& o_value ) const + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } }; }// spd diff --git a/src/import/generic/memory/lib/spd/common/spd_decoder_base.H b/src/import/generic/memory/lib/spd/common/spd_decoder_base.H index 878d2f27e..d69d216b5 100644 --- a/src/import/generic/memory/lib/spd/common/spd_decoder_base.H +++ b/src/import/generic/memory/lib/spd/common/spd_decoder_base.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -788,6 +788,66 @@ class base_cnfg_decoder } /// + /// @brief Decodes Fine Offset for tWTR_L + /// @param[out] o_value tWTR_L offset in FTB units + /// @return FAPI2_RC_SUCCESS iff okay + /// @warning not an actual SPD field, defaulted to zero to simplify calculations + /// + virtual fapi2::ReturnCode fine_offset_min_twtr_l( int64_t& o_value ) const + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for twtr_s + /// @param[out] o_value twtr_s offset in FTB units + /// @return FAPI2_RC_SUCCESS iff okay + /// @warning not an actual SPD field, defaulted to zero to simplify calculations + /// + virtual fapi2::ReturnCode fine_offset_min_twtr_s( int64_t& o_value ) const + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for tfaw + /// @param[out] o_value tfaw offset in FTB units + /// @return FAPI2_RC_SUCCESS iff okay + /// @warning not an actual SPD field, defaulted to zero to simplify calculations + /// + virtual fapi2::ReturnCode fine_offset_min_tfaw( int64_t& o_value ) const + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for tras + /// @param[out] o_value tras offset in FTB units + /// @return FAPI2_RC_SUCCESS iff okay + /// @warning not an actual SPD field, defaulted to zero to simplify calculations + /// + virtual fapi2::ReturnCode fine_offset_min_tras( int64_t& o_value ) const + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes Fine Offset for twr + /// @param[out] o_value twr offset in FTB units + /// @return FAPI2_RC_SUCCESS iff okay + /// @warning not an actual SPD field, defaulted to zero to simplify calculations + /// + virtual fapi2::ReturnCode fine_offset_min_twr( int64_t& o_value ) const + { + o_value = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// /// @brief Decodes Cyclical Redundancy Code (CRC) for Base Configuration Section /// @param[out] o_value crc value from SPD /// @return FAPI2_RC_SUCCESS iff okay |
