Ported ecc engine to generic

Change-Id: Icd8034fd8a0a58874bf79f72392cdc737c5af99e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71828
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76179
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

1 files changed, 107 insertions, 0 deletions

diff --git a/src/import/generic/memory/lib/ecc/mainline_ue_trap.H b/src/import/generic/memory/lib/ecc/mainline_ue_trap.H
index 10da89c18..ed5e46820 100644
--- a/src/import/generic/memory/lib/ecc/mainline_ue_trap.H
+++ b/src/import/generic/memory/lib/ecc/mainline_ue_trap.H
@@ -22,3 +22,110 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file mainline_ue_trap.H
+/// @brief Subroutines for the MC mainline ue address trap registers (MBUER*Q)
+///
+// *HWP HWP Owner: Matt Hickman <Matthew.Hickman@ibm.com>
+// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: FSP:HB
+
+#ifndef _MSS_MAINLINE_UE_TRAP_H_
+#define _MSS_MAINLINE_UE_TRAP_H_
+
+#include <fapi2.H>
+#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_address.H>
+#include <generic/memory/lib/utils/scom.H>
+#include <generic/memory/lib/utils/find.H>
+#include <generic/memory/lib/utils/shared/mss_generic_consts.H>
+#include <generic/memory/lib/ecc/ecc_traits.H>
+
+namespace mss
+{
+
+namespace ecc
+{
+
+namespace mainline_ue_trap
+{
+
+///
+/// @brief Read MBS Mainline UE Address Trap (MBUER*Q) register
+/// @tparam T fapi2 Target Type - derived from i_target's type
+/// @tparam TT traits type defaults to eccTraits<DEFAULT_MC_TYPE, T>
+/// @param[in] i_target the fapi2 target of the mc
+/// @param[out] o_data the value of the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = eccTraits<DEFAULT_MC_TYPE, T> >
+inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data )
+{
+    const auto& l_mcbist_target = mss::find_target<DEFAULT_MC_TARGET>(i_target);
+    const auto& l_port = mss::relative_pos<DEFAULT_MC_TARGET>(i_target);
+
+    FAPI_TRY( mss::getScom(l_mcbist_target, (TT::MAINLINE_UE_REGS[l_port]), o_data) );
+    FAPI_INF("read: 0x%016lx", o_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Write MBS Mainline UE Address Trap (MBUER*Q) register
+/// @tparam T fapi2 Target Type - derived from i_target's type
+/// @tparam TT traits type defaults to eccTraits<DEFAULT_MC_TYPE, T>
+/// @param[in] i_target the fapi2 target of the mc
+/// @param[in] i_data the value to write to the register
+/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok
+///
+template< fapi2::TargetType T, typename TT = eccTraits<DEFAULT_MC_TYPE, T> >
+inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data )
+{
+    const auto& l_mcbist_target = mss::find_target<DEFAULT_MC_TARGET>(i_target);
+    const auto& l_port = mss::relative_pos<DEFAULT_MC_TARGET>(i_target);
+
+    FAPI_TRY( mss::putScom(l_mcbist_target, (TT::MAINLINE_UE_REGS[l_port]), i_data) );
+    FAPI_INF("write: 0x%016lx", i_data);
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief set_address
+/// @tparam T fapi2 Target Type defaults to DEFAULT_MEM_PORT_TARGET
+/// @tparam TT traits type defaults to eccTraits<DEFAULT_MC_TYPE, T>
+/// @param[in, out] io_data the register value
+/// @param[in] i_address mcbist::address form of address field
+///
+template< fapi2::TargetType T = DEFAULT_MEM_PORT_TARGET, typename TT = eccTraits<DEFAULT_MC_TYPE, T> >
+inline void set_address( fapi2::buffer<uint64_t>& io_data, const mcbist::address& i_address)
+{
+    io_data.insertFromRight<TT::UE_ADDR_TRAP, TT::UE_ADDR_TRAP_LEN>(uint64_t(i_address));
+    FAPI_INF("set_address: 0x%016lx", uint64_t(i_address));
+}
+
+///
+/// @brief get_address
+/// @tparam T fapi2 Target Type defaults to DEFAULT_MEM_PORT_TARGET
+/// @tparam TT traits type defaults to eccTraits<DEFAULT_MC_TYPE, T>
+/// @param[in] i_data the register value
+/// @param[out] o_address mcbist::address form of address field
+///
+template< fapi2::TargetType T = DEFAULT_MEM_PORT_TARGET, typename TT = eccTraits<DEFAULT_MC_TYPE, T> >
+inline void get_address( const fapi2::buffer<uint64_t>& i_data, mcbist::address& o_address )
+{
+    uint64_t l_addr = 0;
+    i_data.extractToRight<TT::UE_ADDR_TRAP, TT::UE_ADDR_TRAP_LEN>(l_addr);
+    o_address = mcbist::address(l_addr);
+    FAPI_INF("get_address: 0x%016lx", uint64_t(l_addr));
+}
+
+} // close namespace mainline_ue_trap
+
+} // close namespace ecc
+
+} // close namespace mss
+
+#endif