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| author | Andre A. Marin <aamarin@us.ibm.com> | 2019-03-20 09:01:13 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-04-02 13:20:03 -0500 |
| commit | ee76c2ca5927122cc9bfc792de240f20b87abe82 (patch) | |
| tree | 5a2a256cc16f3b45ba1d3bf166b41b17692ab490 /src/import/generic/memory/lib/data_engine | |
| parent | 8daf280f7d24a3f5b2c553bb39ceda4d0fd32736 (diff) | |
| download | talos-hostboot-ee76c2ca5927122cc9bfc792de240f20b87abe82.tar.gz talos-hostboot-ee76c2ca5927122cc9bfc792de240f20b87abe82.zip | |
Fix c_str and pos DIMM specialization
Change-Id: Id234f7f14bc4dd90de1f8ea70a4617c513ca1ffa
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74846
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74877
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/generic/memory/lib/data_engine')
7 files changed, 509 insertions, 161 deletions
diff --git a/src/import/generic/memory/lib/data_engine/attr_engine_traits.H b/src/import/generic/memory/lib/data_engine/attr_engine_traits.H index 72e89b3f3..1d7388f65 100644 --- a/src/import/generic/memory/lib/data_engine/attr_engine_traits.H +++ b/src/import/generic/memory/lib/data_engine/attr_engine_traits.H @@ -70,7 +70,7 @@ struct attrEngineTraits<attr_eff_engine_fields, DRAM_WIDTH> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DRAM_WIDTH, i_target, o_setting); + return mss::attr::get_dram_width(i_target, o_setting); } /// @@ -82,7 +82,7 @@ struct attrEngineTraits<attr_eff_engine_fields, DRAM_WIDTH> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DRAM_WIDTH, i_target, i_setting); + return mss::attr::set_dram_width(i_target, i_setting); } /// @@ -158,7 +158,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_DQ_DQS> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS, i_target, o_setting); + return mss::attr::get_si_mc_rcv_imp_dq_dqs(i_target, o_setting); } /// @@ -170,7 +170,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_DQ_DQS> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS, i_target, i_setting); + return mss::attr::set_si_mc_rcv_imp_dq_dqs(i_target, i_setting); } /// @@ -208,7 +208,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_UP> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP, i_target, o_setting); + return mss::attr::get_si_mc_drv_imp_dq_dqs_pull_up(i_target, o_setting); } /// @@ -220,7 +220,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_UP> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP, i_target, i_setting); + return mss::attr::set_si_mc_drv_imp_dq_dqs_pull_up(i_target, i_setting); } /// @@ -258,7 +258,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN, i_target, o_setting); + return mss::attr::get_si_mc_drv_imp_dq_dqs_pull_down(i_target, o_setting); } /// @@ -270,7 +270,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN, i_target, i_setting); + return mss::attr::set_si_mc_drv_imp_dq_dqs_pull_down(i_target, i_setting); } /// @@ -309,7 +309,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_DQ_DQS> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS, i_target, o_setting); + return mss::attr::get_si_mc_drv_slew_rate_dq_dqs(i_target, o_setting); } /// @@ -321,7 +321,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_DQ_DQS> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS, i_target, i_setting); + return mss::attr::set_si_mc_drv_slew_rate_dq_dqs(i_target, i_setting); } /// @@ -359,7 +359,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CMD_ADDR> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR, i_target, o_setting); + return mss::attr::get_si_mc_drv_imp_cmd_addr(i_target, o_setting); } /// @@ -371,7 +371,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CMD_ADDR> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR, i_target, i_setting); + return mss::attr::set_si_mc_drv_imp_cmd_addr(i_target, i_setting); } /// @@ -409,7 +409,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CMD_ADDR> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR, i_target, o_setting); + return mss::attr::get_si_mc_drv_slew_rate_cmd_addr(i_target, o_setting); } /// @@ -421,7 +421,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CMD_ADDR> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR, i_target, i_setting); + return mss::attr::set_si_mc_drv_slew_rate_cmd_addr(i_target, i_setting); } /// @@ -459,7 +459,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CLK> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CLK, i_target, o_setting); + return mss::attr::get_si_mc_drv_imp_clk(i_target, o_setting); } /// @@ -471,7 +471,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CLK> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CLK, i_target, i_setting); + return mss::attr::set_si_mc_drv_imp_clk(i_target, i_setting); } /// @@ -509,7 +509,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CLK> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK, i_target, o_setting); + return mss::attr::get_si_mc_drv_slew_rate_clk(i_target, o_setting); } /// @@ -521,7 +521,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CLK> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK, i_target, i_setting); + return mss::attr::set_si_mc_drv_slew_rate_clk(i_target, i_setting); } /// @@ -559,7 +559,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_ALERT_N> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_ALERT_N, i_target, o_setting); + return mss::attr::get_si_mc_rcv_imp_alert_n(i_target, o_setting); } /// @@ -571,7 +571,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_ALERT_N> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_ALERT_N, i_target, i_setting); + return mss::attr::set_si_mc_rcv_imp_alert_n(i_target, i_setting); } /// @@ -609,7 +609,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_NOM> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_RTT_NOM, i_target, o_setting); + return mss::attr::get_si_dram_rtt_nom(i_target, o_setting); } /// @@ -621,7 +621,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_NOM> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_DRAM_RTT_NOM, i_target, i_setting); + return mss::attr::set_si_dram_rtt_nom(i_target, i_setting); } /// @@ -659,7 +659,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_WR> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_RTT_WR, i_target, o_setting); + return mss::attr::get_si_dram_rtt_wr(i_target, o_setting); } /// @@ -671,7 +671,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_WR> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_DRAM_RTT_WR, i_target, i_setting); + return mss::attr::set_si_dram_rtt_wr(i_target, i_setting); } /// @@ -709,7 +709,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_PARK> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_RTT_PARK, i_target, o_setting); + return mss::attr::get_si_dram_rtt_park(i_target, o_setting); } /// @@ -721,7 +721,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_PARK> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_DRAM_RTT_PARK, i_target, i_setting); + return mss::attr::set_si_dram_rtt_park(i_target, i_setting); } /// @@ -759,7 +759,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_PREAMBLE> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_PREAMBLE, i_target, o_setting); + return mss::attr::get_si_dram_preamble(i_target, o_setting); } /// @@ -771,7 +771,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_PREAMBLE> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_DRAM_PREAMBLE, i_target, i_setting); + return mss::attr::set_si_dram_preamble(i_target, i_setting); } /// @@ -810,7 +810,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_EQ_DQ_DQS> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS, i_target, o_setting); + return mss::attr::get_si_mc_drv_eq_dq_dqs(i_target, o_setting); } /// @@ -822,7 +822,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_EQ_DQ_DQS> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS, i_target, i_setting); + return mss::attr::set_si_mc_drv_eq_dq_dqs(i_target, i_setting); } /// @@ -860,7 +860,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_DRV_IMP_DQ_DQS> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS, i_target, o_setting); + return mss::attr::get_si_dram_drv_imp_dq_dqs(i_target, o_setting); } /// @@ -872,7 +872,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_DRV_IMP_DQ_DQS> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS, i_target, i_setting); + return mss::attr::set_si_dram_drv_imp_dq_dqs(i_target, i_setting); } /// @@ -910,7 +910,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_RANGE> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE, i_target, o_setting); + return mss::attr::get_si_vref_dq_train_range(i_target, o_setting); } /// @@ -922,7 +922,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_RANGE> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE, i_target, i_setting); + return mss::attr::set_si_vref_dq_train_range(i_target, i_setting); } /// @@ -960,7 +960,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_VALUE> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE, i_target, o_setting); + return mss::attr::get_si_vref_dq_train_value(i_target, o_setting); } /// @@ -972,7 +972,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_VALUE> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE, i_target, o_setting); + return mss::attr::set_si_vref_dq_train_value(i_target, o_setting); } /// @@ -1010,7 +1010,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_WR> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_ODT_WR, i_target, o_setting); + return mss::attr::get_si_odt_wr(i_target, o_setting); } /// @@ -1022,7 +1022,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_WR> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_ODT_WR, i_target, i_setting); + return mss::attr::set_si_odt_wr(i_target, i_setting); } /// @@ -1095,7 +1095,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_RD> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_ODT_RD, i_target, o_setting); + return mss::attr::get_si_odt_rd(i_target, o_setting); } /// @@ -1107,7 +1107,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_RD> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_ODT_RD, i_target, i_setting); + return mss::attr::set_si_odt_rd(i_target, i_setting); } /// @@ -1179,7 +1179,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_GEARDOWN_MODE> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_GEARDOWN_MODE, i_target, o_setting); + return mss::attr::get_si_geardown_mode(i_target, o_setting); } /// @@ -1191,7 +1191,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_GEARDOWN_MODE> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_GEARDOWN_MODE, i_target, i_setting); + return mss::attr::set_si_geardown_mode(i_target, i_setting); } /// diff --git a/src/import/generic/memory/lib/data_engine/data_engine.H b/src/import/generic/memory/lib/data_engine/data_engine.H index 6a7cbb437..aa0fb5f0a 100644 --- a/src/import/generic/memory/lib/data_engine/data_engine.H +++ b/src/import/generic/memory/lib/data_engine/data_engine.H @@ -236,6 +236,27 @@ struct attr_eff_engine } }; +/// +/// @brief Data structure to set effective config EFF data +/// @class attr_derived_engine +/// @tparam ET attr fields enum type +/// +template < typename ET, typename TT = attrEnumTraits<ET> > +struct attr_derived_engine +{ + using attr_eng_t = gen::attr_engine<ET, static_cast<ET>(TT::DISPATCHER)>; + + /// + /// @brief Sets attr fields denoted by an eum list + /// @param[in] i_target the DIMM target + /// @return FAPI2_RC_SUCCESS iff ok + /// + static fapi2::ReturnCode set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) + { + return attr_eng_t::set(i_target); + } +}; + }// mss #endif diff --git a/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H b/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H index 4a802bd46..57ae5355b 100644 --- a/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H +++ b/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H @@ -45,11 +45,29 @@ namespace mss /// /// @brief enum list of preliminary data fields /// +enum generic_metadata_fields +{ + // Template recursive base case + ATTR_METADATA_BASE_CASE = 0, + + // Attrs to set + DIMM_TYPE_METADATA = 1, + DRAM_GEN_METADATA = 2, + DIMM_POS_METADATA = 3, + + // Dispatcher set to last enum value + ATTR_METADATA_DISPATCHER = DIMM_POS_METADATA, +}; + +/// +/// @brief enum list of preliminary data fields +/// enum pre_data_init_fields { // Template recursive base case ATTR_PRE_DATA_ENGINE_CASE = 0, + // Attrs to set DIMM_TYPE = 1, DRAM_GEN = 2, HYBRID = 3, @@ -119,6 +137,13 @@ enum attr_si_engine_fields template< proc_type T, pre_data_init_fields TT > class preDataInitTraits; +/// +/// @brief Traits associated with DIMM positioning +/// @class dimmPosTraits +/// @tparam MC the MC type +/// +template< mss::mc_type MC > +class dimmPosTraits; /// /// @brief Forward declartion of traits for attrEngineTraits @@ -139,7 +164,7 @@ template < typename ET, ET T > struct setTimingTraits; /// -/// @brief Forward declartion of traits for attr_engine +/// @brief Forward declartion of traits for attrEnumTraits /// @class attrEnumTraits /// @tparam ET enum type /// diff --git a/src/import/generic/memory/lib/data_engine/data_engine_utils.H b/src/import/generic/memory/lib/data_engine/data_engine_utils.H index 5436fd5a3..aaf9a0485 100644 --- a/src/import/generic/memory/lib/data_engine/data_engine_utils.H +++ b/src/import/generic/memory/lib/data_engine/data_engine_utils.H @@ -39,6 +39,7 @@ #include <fapi2.H> #include <generic/memory/lib/utils/index.H> #include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/pos.H> #include <generic/memory/lib/spd/ddimm/efd_decoder.H> #include <generic/memory/lib/spd/spd_facade.H> @@ -61,8 +62,8 @@ struct DataSetterTraits2D; /// template < > struct DataSetterTraits2D < proc_type::NIMBUS, - procTraits<proc_type::NIMBUS>::PORTS_PER_MCS, - procTraits<proc_type::NIMBUS>::DIMMS_PER_PORT + mcTypeTraits<mc_type::NIMBUS>::PORTS_PER_MCS, + mcTypeTraits<mc_type::NIMBUS>::DIMMS_PER_PORT > { static constexpr fapi2::TargetType TARGET = fapi2::TARGET_TYPE_MCA; @@ -319,6 +320,31 @@ fapi_try_exit: /// /// @brief Helper function to update the structure that holds attr data +/// @tparam T the FAPI2 TargetType +/// @tparam IT Input data type +/// @tparam FFDC type +/// @tparam OT Output data type +/// @param[in] i_target the FAPI2 target +/// @param[in] i_setting array to set +/// @param[in] i_ffdc_code FFDC function code +/// @param[out] o_data output to set +/// @return FAPI2_RC_SUCCESS iff okay +/// +template < fapi2::TargetType T, + typename IT, + typename FFDC, + typename OT > +inline fapi2::ReturnCode update_data( const fapi2::Target<T>& i_target, + const IT i_setting, + const FFDC i_ffdc_code, + OT& o_data ) +{ + FAPI_DBG("Updating data with %d for %s", i_setting, spd::c_str(i_target)); + o_data = i_setting; + return fapi2::FAPI2_RC_SUCCESS; +} +/// +/// @brief Helper function to update the structure that holds attr data /// @tparam DT the data type /// @tparam IT Input data type /// @tparam FFDC type @@ -358,7 +384,7 @@ template< typename TT, inline fapi2::ReturnCode set_field(const fapi2::Target<T>& i_target, const IT i_setting) { - const auto l_attr_target = mss::find_target<TT::TARGET>(i_target); + const auto l_attr_target = mss::find_target<TT::TARGET_TYPE>(i_target); typename TT::attr_type l_attr_list = {}; FAPI_TRY( TT::get_attr(l_attr_target, l_attr_list) ); @@ -446,6 +472,24 @@ struct attr_engine { /// /// @brief Sets attributes fields F in ET + /// @tparam T the fapi2 target type + /// @param[in] i_target the fapi2 target + /// @return FAPI2_RC_SUCCESS iff oka + /// + template < fapi2::TargetType T > + static fapi2::ReturnCode single_set(const fapi2::Target<T>& i_target) + { + typename TT::attr_integral_type l_value = 0; + FAPI_TRY( TT::get_value_to_set(i_target, l_value) ); + + FAPI_TRY( set_field<TT>(i_target, l_value) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Sets attributes fields F in ET /// @tparam DT the data type /// @param[in] i_data the data (efd_decoder, spd_facade, etc.) /// @return FAPI2_RC_SUCCESS iff ok @@ -481,6 +525,26 @@ struct attr_engine fapi_try_exit: return fapi2::current_err; } + + /// + /// @brief Sets attributes fields F in ET + /// @tparam T the fapi2 target type + /// @param[in] i_target the fapi2 target + /// @return FAPI2_RC_SUCCESS iff ok + /// + template < fapi2::TargetType T > + static fapi2::ReturnCode set(const fapi2::Target<T>& i_target) + { + FAPI_TRY( (attr_engine<ET, F>::single_set(i_target)) ); + + // Compiler isn't smart enough to deduce F - 1u (decrementing the enum values by 1) + // Cast needed to help the compiler deduce this value is an ET type + // This does the recursive call to unroll a compile-time looping of a enum list of attrs to set + FAPI_TRY( (attr_engine < ET, static_cast<ET>(F - 1u) >::set(i_target)) ); + + fapi_try_exit: + return fapi2::current_err; + } }; /// @@ -498,6 +562,18 @@ struct attr_engine< ET, { /// /// @brief Sets attributes fields F in ET + /// @tparam T the fapi2 target type + /// @param[in] i_target the fapi2 target + /// @return FAPI2_RC_SUCCESS iff ok + /// + template < fapi2::TargetType T > + static fapi2::ReturnCode set(const fapi2::Target<T>& i_target) + { + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Sets attributes fields F in ET /// @tparam DT the data type /// @param[in] i_data the data (efd_decoder, spd_facade, etc.) /// @return FAPI2_RC_SUCCESS iff ok @@ -509,6 +585,30 @@ struct attr_engine< ET, } }; +/// +/// @brief Return a DIMM's position from a fapi2 target +/// @tparam TT Traits associated with DIMM position (e.g. dimmPosTraits) +/// @tparam OT the output type +/// @param[in] i_target a target representing the target in question +/// @param[out] o_value The position relative to the chip +/// +template< typename TT, typename OT> +fapi2::ReturnCode dimm_pos(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, OT& o_value) +{ + const auto l_proc_pos = mss::pos( TT::get_proc(i_target) ); + + typename TT::pos_type l_pos = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FAPI_POS, i_target, l_pos)); + + // To get the FAPI_POS to the equivilent of ATTR_POS, we need to normalize the fapi_pos value + // to the processor (stride across which ever processor we're on) and then add in the delta + // per processor as ATTR_POS isn't processor relative (delta is the total dimm on a processor) + o_value = ((l_pos - (l_proc_pos * TT::DIMM_STRIDE_PER_PROC)) % TT::TOTAL_DIMM) + (TT::TOTAL_DIMM * l_proc_pos); + +fapi_try_exit: + return fapi2::current_err; +} + }// gen }//mss diff --git a/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H b/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H index 69234151e..0fd4a0056 100644 --- a/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H +++ b/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H @@ -39,14 +39,76 @@ #include <generic/memory/lib/data_engine/data_engine_traits_def.H> #include <generic/memory/lib/data_engine/data_engine_utils.H> #include <generic/memory/lib/spd/spd_facade.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> +#include <generic/memory/lib/mss_generic_attribute_setters.H> namespace mss { /// +/// @brief Helper function to get dimm_type from SPD +/// @param[in] i_spd_data SPD data +/// @param[in] i_setting value we want to set attr with +/// @return FAPI2_RC_SUCCESS iff okay +/// +static fapi2::ReturnCode get_dimm_type(const spd::facade& i_spd_data, + uint8_t& o_setting) +{ + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 3 (0x003): Key Byte / Module Type + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > BASE_MODULE_TYPE_MAP = + { + //{key byte, dimm type} + {1, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM}, + {2, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM}, + {10, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM}, + // All others reserved or not supported + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + uint8_t l_base_module_type = 0; + FAPI_TRY(i_spd_data.base_module(l_base_module_type)); + FAPI_TRY(lookup_table_check(l_dimm, BASE_MODULE_TYPE_MAP, SET_ATTR_DIMM_TYPE, l_base_module_type, o_setting)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Helper function to get dram_gen from SPD +/// @param[in] i_spd_data SPD data +/// @param[in] i_setting value we want to set attr with +/// @return FAPI2_RC_SUCCESS iff okay +/// +static fapi2::ReturnCode get_dram_gen(const spd::facade& i_spd_data, + uint8_t& o_setting) +{ + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 2 (0x002): Key Byte / DRAM Device Type + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_GEN_MAP = + { + //{key value, dram gen} + {0x0C, fapi2::ENUM_ATTR_MEM_EFF_DRAM_GEN_DDR4} + // Other key bytes reserved or not supported + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + uint8_t l_device_type = 0; + FAPI_TRY(i_spd_data.device_type(l_device_type)); + FAPI_TRY(lookup_table_check(l_dimm, DRAM_GEN_MAP, SET_ATTR_DRAM_GEN, l_device_type, o_setting)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief Traits for pre_data_engine /// @class attrEngineTraits -/// @note AXONE, DIMM_TYPE specialization +/// @note pre_data_init_fields, DIMM_TYPE specialization /// template<> struct attrEngineTraits<pre_data_init_fields, DIMM_TYPE> @@ -58,26 +120,26 @@ struct attrEngineTraits<pre_data_init_fields, DIMM_TYPE> /// /// @brief attribute getter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[out] o_setting array to populate /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DIMM_TYPE, i_target, o_setting); + return mss::attr::get_dimm_type(i_target, o_setting); } /// /// @brief attribute setter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[in] i_setting array to set /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DIMM_TYPE, i_target, i_setting); + return mss::attr::set_dimm_type(i_target, i_setting); } /// @@ -89,33 +151,14 @@ struct attrEngineTraits<pre_data_init_fields, DIMM_TYPE> static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, attr_integral_type& o_setting) { - // ========================================================= - // DDR4 SPD Document Release 4 - // Byte 3 (0x003): Key Byte / Module Type - // ========================================================= - static const std::vector< std::pair<uint8_t, uint8_t> > BASE_MODULE_TYPE_MAP = - { - //{key byte, dimm type} - {1, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM}, - {2, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM}, - {10, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM}, - // All others reserved or not supported - }; - - uint8_t l_base_module_type = 0; - FAPI_TRY(i_spd_data.base_module(l_base_module_type)); - FAPI_TRY(lookup_table_check(i_spd_data.get_dimm_target(), BASE_MODULE_TYPE_MAP, SET_ATTR_DIMM_TYPE, l_base_module_type, - o_setting)); - - fapi_try_exit: - return fapi2::current_err; + return get_dimm_type(i_spd_data, o_setting); } }; /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits -/// @note AXONE, DRAM_GEN specialization +/// @note pre_data_init_fields, DRAM_GEN specialization /// template<> struct attrEngineTraits<pre_data_init_fields, DRAM_GEN> @@ -127,26 +170,26 @@ struct attrEngineTraits<pre_data_init_fields, DRAM_GEN> /// /// @brief attribute getter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[out] o_setting array to populate /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DRAM_GEN, i_target, o_setting); + return mss::attr::get_dram_gen(i_target, o_setting); } /// /// @brief attribute setter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[in] i_setting array to set /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DRAM_GEN, i_target, i_setting); + return mss::attr::set_dram_gen(i_target, i_setting); } /// @@ -158,30 +201,14 @@ struct attrEngineTraits<pre_data_init_fields, DRAM_GEN> static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, attr_integral_type& o_setting) { - // ========================================================= - // DDR4 SPD Document Release 4 - // Byte 2 (0x002): Key Byte / DRAM Device Type - // ========================================================= - static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_GEN_MAP = - { - //{key value, dram gen} - {0x0C, fapi2::ENUM_ATTR_MEM_EFF_DRAM_GEN_DDR4} - // Other key bytes reserved or not supported - }; - - uint8_t l_device_type = 0; - FAPI_TRY(i_spd_data.device_type(l_device_type)); - FAPI_TRY(lookup_table_check(i_spd_data.get_dimm_target(), DRAM_GEN_MAP, SET_ATTR_DRAM_GEN, l_device_type, o_setting)); - - fapi_try_exit: - return fapi2::current_err; + return get_dram_gen(i_spd_data, o_setting); } }; /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits -/// @note AXONE, HYBRID specialization +/// @note pre_data_init_fields, HYBRID specialization /// template<> struct attrEngineTraits<pre_data_init_fields, HYBRID> @@ -193,26 +220,26 @@ struct attrEngineTraits<pre_data_init_fields, HYBRID> /// /// @brief attribute getter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[out] o_setting array to populate /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_HYBRID, i_target, o_setting); + return mss::attr::get_hybrid(i_target, o_setting); } /// /// @brief attribute setter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[in] i_setting array to set /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_HYBRID, i_target, i_setting); + return mss::attr::set_hybrid(i_target, i_setting); } /// @@ -248,7 +275,7 @@ struct attrEngineTraits<pre_data_init_fields, HYBRID> /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits -/// @note AXONE, HYBRID_MEDIA specialization +/// @note pre_data_init_fields, HYBRID_MEDIA specialization /// template<> struct attrEngineTraits<pre_data_init_fields, HYBRID_MEDIA> @@ -260,26 +287,26 @@ struct attrEngineTraits<pre_data_init_fields, HYBRID_MEDIA> /// /// @brief attribute getter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[out] o_setting array to populate /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_HYBRID_MEMORY_TYPE, i_target, o_setting); + return mss::attr::get_hybrid_memory_type(i_target, o_setting); } /// /// @brief attribute setter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[in] i_setting array to set /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_HYBRID_MEMORY_TYPE, i_target, i_setting); + return mss::attr::set_hybrid_memory_type(i_target, i_setting); } /// @@ -350,7 +377,7 @@ fapi_try_exit: /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits -/// @note AXONE, MRANKS specialization +/// @note pre_data_init_fields, MRANKS specialization /// template<> struct attrEngineTraits<pre_data_init_fields, MRANKS> @@ -362,26 +389,26 @@ struct attrEngineTraits<pre_data_init_fields, MRANKS> /// /// @brief attribute getter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[out] o_setting array to populate /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, o_setting); + return mss::attr::get_num_master_ranks_per_dimm(i_target, o_setting); } /// /// @brief attribute setter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[in] i_setting array to set /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, i_setting); + return mss::attr::set_num_master_ranks_per_dimm(i_target, i_setting); } /// @@ -403,7 +430,7 @@ struct attrEngineTraits<pre_data_init_fields, MRANKS> /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits -/// @note AXONE, DIMM_RANKS_CNFG specialization +/// @note pre_data_init_fields, DIMM_RANKS_CNFG specialization /// template<> struct attrEngineTraits<pre_data_init_fields, DIMM_RANKS_CNFG> @@ -415,26 +442,26 @@ struct attrEngineTraits<pre_data_init_fields, DIMM_RANKS_CNFG> /// /// @brief attribute getter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[out] o_setting array to populate /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED, i_target, o_setting); + return mss::attr::get_dimm_ranks_configed(i_target, o_setting); } /// /// @brief attribute setter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[in] i_setting array to set /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED, i_target, i_setting); + return mss::attr::set_dimm_ranks_configed(i_target, i_setting); } /// diff --git a/src/import/generic/memory/lib/data_engine/p9n/p9n_data_init_traits.H b/src/import/generic/memory/lib/data_engine/p9n/p9n_data_init_traits.H index 02254790e..5f0207b14 100644 --- a/src/import/generic/memory/lib/data_engine/p9n/p9n_data_init_traits.H +++ b/src/import/generic/memory/lib/data_engine/p9n/p9n_data_init_traits.H @@ -38,6 +38,8 @@ #include <fapi2.H> #include <generic/memory/lib/data_engine/data_engine_traits_def.H> +#include <generic/memory/lib/data_engine/data_engine.H> +#include <lib/mss_attribute_accessors.H> namespace mss { @@ -77,14 +79,9 @@ class preDataInitTraits<mss::proc_type::NIMBUS, DIMM_TYPE> /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - const attr_type& i_setting) + attr_type& i_setting) { - attr_type l_data = {}; - memcpy(l_data, i_setting, sizeof(l_data)); - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_TYPE, i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; + return FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_TYPE, i_target, i_setting); } }; @@ -123,15 +120,9 @@ class preDataInitTraits<mss::proc_type::NIMBUS, DRAM_GEN> /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - const attr_type& i_setting) + attr_type& i_setting) { - attr_type l_data = {}; - memcpy(l_data, i_setting, sizeof(l_data)); - - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_GEN, i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; + return FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_GEN, i_target, i_setting); } }; @@ -170,15 +161,9 @@ class preDataInitTraits<mss::proc_type::NIMBUS, HYBRID> /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - const attr_type& i_setting) + attr_type& i_setting) { - attr_type l_data = {}; - memcpy(l_data, i_setting, sizeof(l_data)); - - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_HYBRID, i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; + return FAPI_ATTR_SET(fapi2::ATTR_EFF_HYBRID, i_target, i_setting); } }; @@ -217,15 +202,9 @@ class preDataInitTraits<mss::proc_type::NIMBUS, HYBRID_MEDIA> /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - const attr_type& i_setting) + attr_type& i_setting) { - attr_type l_data = {}; - memcpy(l_data, i_setting, sizeof(l_data)); - - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_HYBRID_MEMORY_TYPE, i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; + return FAPI_ATTR_SET(fapi2::ATTR_EFF_HYBRID_MEMORY_TYPE, i_target, i_setting); } }; @@ -264,15 +243,9 @@ class preDataInitTraits<mss::proc_type::NIMBUS, MRANKS> /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - const attr_type& i_setting) + attr_type& i_setting) { - attr_type l_data = {}; - memcpy(l_data, i_setting, sizeof(l_data)); - - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; + return FAPI_ATTR_SET(fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, i_setting); } }; @@ -311,18 +284,205 @@ class preDataInitTraits<mss::proc_type::NIMBUS, DIMM_RANKS_CNFG> /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - const attr_type& i_setting) + attr_type& i_setting) { - attr_type l_data = {}; - memcpy(l_data, i_setting, sizeof(l_data)); + return FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED, i_target, i_setting); + } +}; - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED, i_target, l_data) ); +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note AXONE, DIMM_TYPE_METADATA specialization +/// +template<> +struct attrEngineTraits<generic_metadata_fields, DIMM_TYPE_METADATA> +{ + using attr_type = fapi2::ATTR_MEM_DIMM_TYPE_METADATA_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_DIMM_TYPE_METADATA_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_TYPE_METADATA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_TYPE_METADATA, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_DIMM_TYPE_METADATA, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + return mss::eff_dimm_type(i_target, o_setting); + } +}; - fapi_try_exit: - return fapi2::current_err; +/// +/// @brief Traits associated with DIMM positioning +/// @class dimmPosTraits - NIMBUS specializattion +/// +template<> +class dimmPosTraits<mss::mc_type::NIMBUS> +{ + private: + using PT = posTraits<fapi2::TARGET_TYPE_DIMM>; + using MT = mss::mcTypeTraits<mc_type::NIMBUS>; + + public: + // Public interface syntatic sugar + using pos_type = PT::pos_type; + + // Proc 0 is DIMM 0-15, proc 2 is 64-79. 64 is the stride between processors + static constexpr auto DIMM_STRIDE_PER_PROC = 64; + static constexpr auto TOTAL_DIMM = MT::MC_PER_MODULE * MT::MCS_PER_MC * MT::PORTS_PER_MCS * MT::DIMMS_PER_PORT; + + /// + /// @brief Return the PROC_CHIP parent of a DIMM + /// @param[in] i_target the dimm target + /// @return the fapi2 proc target + /// + static fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> get_proc(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) + { + // Using fapi2 rather than mss::find as this is pretty low level stuff. + return i_target.getParent<fapi2::TARGET_TYPE_MCA>().getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); } }; +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note generic_metadata_fields, DRAM_GEN_METADATA specialization +/// +template<> +struct attrEngineTraits<generic_metadata_fields, DRAM_GEN_METADATA> +{ + using attr_type = fapi2::ATTR_MEM_DRAM_GEN_METADATA_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_DRAM_GEN_METADATA_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DRAM_GEN_METADATA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_DRAM_GEN_METADATA, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_DRAM_GEN_METADATA, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + return mss::eff_dram_gen(i_target, o_setting); + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note generic_metadata_fields, DIMM_POS_METADATA specialization +/// +template<> +struct attrEngineTraits<generic_metadata_fields, DIMM_POS_METADATA> +{ + using attr_type = fapi2::ATTR_MEM_DIMM_POS_METADATA_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_DIMM_POS_METADATA_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_POS_METADATA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_POS_METADATA, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_DIMM_POS_METADATA, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + using TT = mss::dimmPosTraits<mss::mc_type::NIMBUS>; + return gen::dimm_pos<TT>(i_target, o_setting); + } +}; + +/// +/// @brief Value traits for attr_eff_engine_fields +/// @class attrEngineTraits +/// @note attr_eff_engine_fields +/// +template < > +struct attrEnumTraits<generic_metadata_fields> +{ + static constexpr size_t DISPATCHER = ATTR_METADATA_DISPATCHER; +}; + }// mss #endif diff --git a/src/import/generic/memory/lib/data_engine/pre_data_init.H b/src/import/generic/memory/lib/data_engine/pre_data_init.H index b3e4de8ad..b8311f83e 100644 --- a/src/import/generic/memory/lib/data_engine/pre_data_init.H +++ b/src/import/generic/memory/lib/data_engine/pre_data_init.H @@ -250,10 +250,23 @@ class pre_data_engine /// @return FAPI2_RC_SUCCESS iff ok /// template <mss::proc_type P> -fapi2::ReturnCode set_pre_init_attrs( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const spd::facade& i_spd_decoder ) +inline fapi2::ReturnCode set_pre_init_attrs( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const spd::facade& i_spd_decoder ); + +/// +/// @brief Sets pre_eff_config attributes - NIMBUS specialization +/// @param[in] i_target the DIMM target +/// @param[in] i_spd_decoder SPD decoder +/// @return FAPI2_RC_SUCCESS iff ok +/// +template <> +inline fapi2::ReturnCode set_pre_init_attrs<mss::proc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& + i_target, + const spd::facade& i_spd_decoder ) { - mss::pre_data_engine<P> l_data_engine(i_target, i_spd_decoder); + // TK explicitly forcing this API to only run in Nimbus, need to move pre_data_engine to Nimbus chip path, + // using template recursive algorithm moving forward + mss::pre_data_engine<mss::proc_type::NIMBUS> l_data_engine(i_target, i_spd_decoder); // Set attributes needed before eff_config // DIMM type and DRAM gen are needed for c_str to aid debugging @@ -270,6 +283,8 @@ fapi2::ReturnCode set_pre_init_attrs( const fapi2::Target<fapi2::TARGET_TYPE_DIM FAPI_TRY(l_data_engine.set_dimm_ranks_configured(), "Failed to set DIMM ranks configured %s", mss::spd::c_str(i_target) ); + FAPI_TRY( mss::attr_derived_engine<mss::generic_metadata_fields>::set(i_target) ); + fapi_try_exit: return fapi2::current_err; } |

