diff options
| author | Andre A. Marin <aamarin@us.ibm.com> | 2019-03-20 09:01:13 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-04-02 13:20:03 -0500 |
| commit | ee76c2ca5927122cc9bfc792de240f20b87abe82 (patch) | |
| tree | 5a2a256cc16f3b45ba1d3bf166b41b17692ab490 /src | |
| parent | 8daf280f7d24a3f5b2c553bb39ceda4d0fd32736 (diff) | |
| download | talos-hostboot-ee76c2ca5927122cc9bfc792de240f20b87abe82.tar.gz talos-hostboot-ee76c2ca5927122cc9bfc792de240f20b87abe82.zip | |
Fix c_str and pos DIMM specialization
Change-Id: Id234f7f14bc4dd90de1f8ea70a4617c513ca1ffa
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74846
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74877
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src')
44 files changed, 2120 insertions, 1537 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/memory/lib/utils/mem_size.C b/src/import/chips/centaur/procedures/hwp/memory/lib/utils/mem_size.C index 0a804bdf0..465e31779 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/lib/utils/mem_size.C +++ b/src/import/chips/centaur/procedures/hwp/memory/lib/utils/mem_size.C @@ -26,11 +26,10 @@ #include <fapi2.H> #include <lib/shared/dimmConsts.H> +#include <p9c_mss_funcs.H> #include <generic/memory/lib/utils/memory_size.H> #include <generic/memory/lib/utils/find.H> - -namespace mss -{ +#include <generic/memory/lib/utils/c_str.H> /// /// @brief Check if a given DIMM is functional @@ -74,6 +73,8 @@ bool is_dimm_functional(const uint8_t i_valid_dimm_bitmap, return fapi2::buffer<uint8_t>(i_valid_dimm_bitmap).getBit(VALID_DIMM_POS[i_port][i_dimm]); } +namespace mss +{ /// /// @brief Return the total memory size behind an MBA diff --git a/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.C b/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.C index 38aed25e9..f8324bb84 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.C +++ b/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.C @@ -33,8 +33,7 @@ #include <mss_dynamic_vid_utils.H> #include <generic/memory/lib/utils/find.H> - - +#include <generic/memory/lib/utils/c_str.H> /// /// @brief Checks centaur configurations and outputs DRAM device type diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_funcs.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_funcs.H index d53e72730..3472a6547 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_funcs.H +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_funcs.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -447,5 +447,16 @@ fapi2::ReturnCode cs_decode(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_targe const uint8_t i_stack_type, fapi2::variable_buffer& o_csn_8); +/// +/// @brief Check if a given DIMM is functional +/// @param[in] i_valid_dimm_bitmap from ATTR_CEN_MSS_EFF_DIMM_FUNCTIONAL_VECTOR +/// @param[in] i_port port index [0:1] +/// @param[in] i_dimm dimm index [0:1] +/// @return true if dimm is functional, false otherwise +/// +bool is_dimm_functional(const uint8_t i_valid_dimm_bitmap, + const uint8_t i_port, + const uint8_t i_dimm); + #endif /* _MSS_FUNCS_H */ diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_rowRepairFuncs.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_rowRepairFuncs.C index 65b95f894..8362380a7 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_rowRepairFuncs.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_rowRepairFuncs.C @@ -24,6 +24,7 @@ /* IBM_PROLOG_END_TAG */ #include <p9c_mss_rowRepairFuncs.H> #include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/c_str.H> using namespace fapi2; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H index 686f7085c..61c941f53 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H @@ -39,6 +39,7 @@ #include <fapi2.H> #include <lib/shared/exp_consts.H> +#include <generic/memory/lib/data_engine/data_engine_traits_def.H> #include <generic/memory/lib/data_engine/data_engine.H> #include <generic/memory/lib/spd/spd_facade.H> #include <lib/mss_explorer_attribute_getters.H> @@ -610,6 +611,191 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_CL_SUPPORTED> }; /// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note AXONE, DIMM_TYPE_METADATA specialization +/// +template<> +struct attrEngineTraits<generic_metadata_fields, DIMM_TYPE_METADATA> +{ + using attr_type = fapi2::ATTR_MEM_DIMM_TYPE_METADATA_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_DIMM_TYPE_METADATA_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_TYPE_METADATA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_dimm_type_metadata(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_dimm_type_metadata(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + return mss::attr::get_dimm_type(i_target, o_setting); + } +}; + +/// +/// @brief Traits associated with DIMM positioning +/// @class dimmPosTraits - EXPLORER specializattion +/// +template<> +class dimmPosTraits<mss::mc_type::EXPLORER> +{ + private: + using PT = posTraits<fapi2::TARGET_TYPE_DIMM>; + using MT = mss::mcTypeTraits<mc_type::EXPLORER>; + + public: + // Public interface syntatic sugar + using pos_type = PT::pos_type; + + // Proc 0 would be DIMM0 - 31, proc 1 would be DIMM32 - 63, etc. 32 is the stride between processors + static constexpr auto DIMM_STRIDE_PER_PROC = 32; + static constexpr auto TOTAL_DIMM = MT::MC_PER_PROC * MT::MI_PER_MC * MT::MCC_PER_MI * + MT::OMI_PER_MCC * MT::OCMB_PER_OMI * MT::PORTS_PER_OCMB * MT::DIMMS_PER_PORT; + + /// + /// @brief Return the PROC_CHIP parent of a DIMM + /// @param[in] i_target the dimm target + /// @return the fapi2 proc target + /// + static fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> get_proc(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) + { + // Using fapi2 rather than mss::find as this is pretty low level stuff. + const auto l_ocmb = i_target.getParent<fapi2::TARGET_TYPE_MEM_PORT>().getParent<fapi2::TARGET_TYPE_OCMB_CHIP>(); + const auto l_mc = l_ocmb.getParent<fapi2::TARGET_TYPE_OMI>().getParent<fapi2::TARGET_TYPE_MC>(); + return l_mc.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note generic_metadata_fields, DRAM_GEN_METADATA specialization +/// +template<> +struct attrEngineTraits<generic_metadata_fields, DRAM_GEN_METADATA> +{ + using attr_type = fapi2::ATTR_MEM_DRAM_GEN_METADATA_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_DRAM_GEN_METADATA_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DRAM_GEN_METADATA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_dram_gen_metadata(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_dram_gen_metadata(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + return mss::attr::get_dram_gen(i_target, o_setting); + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note generic_metadata_fields, DIMM_POS_METADATA specialization +/// +template<> +struct attrEngineTraits<generic_metadata_fields, DIMM_POS_METADATA> +{ + using attr_type = fapi2::ATTR_MEM_DIMM_POS_METADATA_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_DIMM_POS_METADATA_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_POS_METADATA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_dimm_pos_metadata(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_dimm_pos_metadata(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + using TT = mss::dimmPosTraits<mss::mc_type::EXPLORER>; + return gen::dimm_pos<TT>(i_target, o_setting); + } +}; + +/// /// @brief Value traits for attr_eff_engine_fields /// @class attrEngineTraits /// @note attr_eff_engine_fields @@ -620,6 +806,17 @@ struct attrEnumTraits<exp::attr_eff_engine_fields> static constexpr size_t DISPATCHER = exp::ATTR_EFF_DISPATCHER; }; +/// +/// @brief Value traits for attr_eff_engine_fields +/// @class attrEngineTraits +/// @note attr_eff_engine_fields +/// +template < > +struct attrEnumTraits<generic_metadata_fields> +{ + static constexpr size_t DISPATCHER = ATTR_METADATA_DISPATCHER; +}; + }//mss #endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils/explorer_pos.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils/explorer_pos.C index 4b1072a61..4a3f7c703 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils/explorer_pos.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils/explorer_pos.C @@ -22,3 +22,62 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file explorer_pos.C +/// @brief Tools to return target's position from a fapi2 target +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#include <generic/memory/lib/utils/pos.H> + +namespace mss +{ + +/// +/// +/// @brief Return a DIMM's relative position from a port +/// @param[in] i_target a target representing the target in question +/// @return The position relative to chiplet R +/// +template<> +posTraits<fapi2::TARGET_TYPE_DIMM>::pos_type +relative_pos<fapi2::TARGET_TYPE_MEM_PORT>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) +{ + typedef mcTypeTraits<mc_type::EXPLORER> TT; + return pos(i_target) % TT::DIMMS_PER_PORT; +} + +/// +/// @brief Return a DIMM's relative position from an OCMB +/// @tparam MC the type of memory controller (defaults to DEFAULT_MC_TYPE) +/// @param[in] i_target a target representing the target in question +/// @return The position relative to chiplet R +/// +template<> +posTraits<fapi2::TARGET_TYPE_DIMM>::pos_type +relative_pos<fapi2::TARGET_TYPE_OCMB_CHIP>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) +{ + typedef mcTypeTraits<mc_type::EXPLORER> TT; + return pos(i_target) % (TT::DIMMS_PER_PORT * TT::PORTS_PER_OCMB); +} + +/// +/// @brief Return an MEM_PORT's relative position from an OCMB +/// @tparam MC the type of memory controller (defaults to DEFAULT_MC_TYPE) +/// @param[in] i_target a target representing the target in question +/// @return The position relative to chiplet R +/// +template<> +posTraits<fapi2::TARGET_TYPE_MEM_PORT>::pos_type +relative_pos<fapi2::TARGET_TYPE_OCMB_CHIP>(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target) +{ + typedef mcTypeTraits<mc_type::EXPLORER> TT; + return pos(i_target) % TT::PORTS_PER_OCMB; +} + +}// mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C index e564eafce..d2ddaf136 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C @@ -49,7 +49,7 @@ #include <lib/mcbist/mcbist.H> #include <lib/mcbist/settings.H> #include <lib/utils/mss_nimbus_conversions.H> - +#include <generic/memory/lib/utils/pos.H> #include <lib/mc/port.H> #include <lib/phy/dp16.H> #include <lib/dimm/mrs_load.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H index bfded0433..038ed1e6e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,6 +41,7 @@ #include <generic/memory/lib/utils/scom.H> #include <generic/memory/lib/utils/find.H> #include <lib/ecc/ecc_traits.H> +#include <generic/memory/lib/utils/pos.H> namespace mss { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C index 68a5c02a2..e0c36092f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C @@ -38,7 +38,7 @@ #include <p9_mc_scom_addresses_fld.H> #include <p9_perv_scom_addresses.H> #include <p9_perv_scom_addresses_fld.H> - +#include <generic/memory/lib/utils/find_magic.H> #include <generic/memory/lib/utils/scom.H> #include <lib/fir/fir.H> #include <lib/fir/check.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C index 0e2cb2c93..999e4c812 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,7 +36,7 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> - +#include <generic/memory/lib/utils/find_magic.H> #include <generic/memory/lib/utils/scom.H> #include <lib/fir/fir.H> #include <lib/fir/unmask.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C index ef9933edb..62d36ae0b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,6 +44,7 @@ #include <generic/memory/lib/utils/scom.H> #include <lib/dimm/kind.H> #include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/pos.H> using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_MCS; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C index 87dd3db08..31ac6eade 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,7 +39,7 @@ #include <p9_mc_scom_addresses_fld.H> #include <lib/mss_attribute_accessors.H> - +#include <generic/memory/lib/utils/pos.H> #include <lib/mc/mc.H> #include <lib/mc/xlate.H> #include <generic/memory/lib/utils/scom.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C index 44ae66b87..64ac23bcc 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,6 +37,7 @@ #include <lib/mcbist/mcbist.H> #include <lib/utils/dump_regs.H> #include <lib/workarounds/mcbist_workarounds.H> +#include <generic/memory/lib/utils/pos.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C index bdd64a0d1..e7176b855 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,7 +37,7 @@ #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> - +#include <generic/memory/lib/utils/find_magic.H> #include <lib/mcbist/memdiags.H> #include <lib/mcbist/mcbist.H> #include <lib/mcbist/address.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C index 01940ac3c..20a8b10a3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,6 +41,7 @@ #include <lib/mcbist/patterns.H> #include <lib/mcbist/sim.H> #include <generic/memory/lib/utils/count_dimm.H> +#include <generic/memory/lib/utils/pos.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C index eaf787bbc..6ddc3b109 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,6 +38,7 @@ #include <generic/memory/lib/utils/scom.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/index.H> +#include <generic/memory/lib/utils/pos.H> namespace mss { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index c8f59400e..b9f8cc351 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -55,7 +55,7 @@ #include <lib/workarounds/dll_workarounds.H> #include <lib/workarounds/dqs_align_workarounds.H> #include <lib/phy/mss_training.H> - +#include <generic/memory/lib/utils/find_magic.H> #include <generic/memory/lib/utils/bit_count.H> #include <generic/memory/lib/utils/find.H> #include <lib/utils/dump_regs.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index d98f7a56f..89c00b0b8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -50,7 +50,7 @@ #include <generic/memory/lib/utils/scom.H> #include <generic/memory/lib/utils/pos.H> #include <generic/memory/lib/utils/c_str.H> - +#include <generic/memory/lib/utils/find_magic.H> #include <lib/workarounds/dp16_workarounds.H> #include <lib/fir/check.H> #include <generic/memory/lib/utils/mss_math.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C index d6137f0a4..0bee4a41f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C @@ -49,6 +49,7 @@ #include <lib/rosetta_map/rosetta_map.H> #include <lib/dimm/ddr4/pba.H> #include <lib/eff_config/timing.H> +#include <generic/memory/lib/utils/pos.H> #ifdef LRDIMM_CAPABLE #include <lib/phy/mss_lrdimm_training_helper.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C index a0622f929..82a5e2c6e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,6 +39,7 @@ // mss lib #include <lib/power_thermal/throttle.H> #include <generic/memory/lib/utils/count_dimm.H> +#include <generic/memory/lib/utils/pos.H> using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_MCS; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H index f02ff4310..9e8cd18a0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/rosetta_map/rosetta_map.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,7 +39,7 @@ #include <vector> #include <algorithm> #include <fapi2.H> - +#include <generic/memory/lib/utils/pos.H> #include <lib/mss_attribute_accessors.H> #include <lib/shared/mss_const.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/nimbus_pos.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/nimbus_pos.C index 658ef9bc9..8ace1cac4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/nimbus_pos.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/nimbus_pos.C @@ -22,3 +22,100 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file nimbus_pos.C +/// @brief Tools to return target's position from a fapi2 target +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/utils/pos.H> + +namespace mss +{ + +/// +/// @brief Return a MCA's relative position from an MCBIST +/// @param[in] i_target a target representing the target in question +/// @return The position relative to chiplet R +/// +template<> +posTraits<fapi2::TARGET_TYPE_MCA>::pos_type +relative_pos<fapi2::TARGET_TYPE_MCBIST>(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) +{ + + typedef mcTypeTraits<mc_type::NIMBUS> TT; + return pos(i_target) % TT::PORTS_PER_MCBIST; +} + +/// +/// @brief Return a DIMM's relative position from an MCS +/// @param[in] i_target a target representing the target in question +/// @return The position relative to chiplet R +/// +template<> +posTraits<fapi2::TARGET_TYPE_DIMM>::pos_type +relative_pos<fapi2::TARGET_TYPE_MCS>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) +{ + typedef mcTypeTraits<mc_type::NIMBUS> TT; + return pos(i_target) % TT::DIMMS_PER_MCS; +} + +/// +/// @brief Return a DIMM's relative position from an MCA +/// @param[in] i_target a target representing the target in question +/// @return The position relative to chiplet R +/// +template<> +posTraits<fapi2::TARGET_TYPE_DIMM>::pos_type +relative_pos<fapi2::TARGET_TYPE_MCA>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) +{ + typedef mcTypeTraits<mc_type::NIMBUS> TT; + return pos(i_target) % TT::DIMMS_PER_PORT; +} + +/// +/// @brief Return a DIMM's relative position from an MCBIST +/// @param[in] i_target a target representing the target in question +/// @return The position relative to chiplet R +/// +template<> +posTraits<fapi2::TARGET_TYPE_DIMM>::pos_type +relative_pos<fapi2::TARGET_TYPE_MCBIST>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) +{ + typedef mcTypeTraits<mc_type::NIMBUS> TT; + return pos(i_target) % TT::DIMMS_PER_MCBIST; +} + +/// +/// @brief Return an MCS's relative position from a processor +/// @param[in] i_target a target representing the target in question +/// @return The position relative to chiplet R +/// +template<> +posTraits<fapi2::TARGET_TYPE_MCS>::pos_type +relative_pos<fapi2::TARGET_TYPE_PROC_CHIP>(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target) +{ + typedef mcTypeTraits<mc_type::NIMBUS> TT; + return pos(i_target) % TT::MCS_PER_PROC; +} + +/// +/// @brief Return an MCA's relative position from an MCS +/// @param[in] i_target a target representing the target in question +/// @return The position relative to chiplet R +/// +template<> +posTraits<fapi2::TARGET_TYPE_MCA>::pos_type +relative_pos<fapi2::TARGET_TYPE_MCS>(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) +{ + typedef mcTypeTraits<mc_type::NIMBUS> TT; + return pos(i_target) % TT::PORTS_PER_MCS; +} + +}// mss diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C index e8acb8237..cb03ee369 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -43,6 +43,7 @@ #include <lib/phy/ddr_phy.H> #include <lib/mc/mc.H> #include <lib/fir/unmask.H> +#include <generic/memory/lib/utils/find_magic.H> using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_MCBIST; diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.C index 8a1e0a877..4fc51a28e 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.C +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.C @@ -67,6 +67,8 @@ fapi2::ReturnCode p9a_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MEM uint64_t l_freq = 0; FAPI_TRY( mss::attr::get_freq(mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(dimm), l_freq) ); + FAPI_TRY( mss::attr_derived_engine<mss::generic_metadata_fields>::set(dimm) ); + // Quick hack to get the index until DIMM level attrs work FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_REL_POS, dimm, l_dimm_index) ); diff --git a/src/import/generic/memory/lib/data_engine/attr_engine_traits.H b/src/import/generic/memory/lib/data_engine/attr_engine_traits.H index 72e89b3f3..1d7388f65 100644 --- a/src/import/generic/memory/lib/data_engine/attr_engine_traits.H +++ b/src/import/generic/memory/lib/data_engine/attr_engine_traits.H @@ -70,7 +70,7 @@ struct attrEngineTraits<attr_eff_engine_fields, DRAM_WIDTH> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DRAM_WIDTH, i_target, o_setting); + return mss::attr::get_dram_width(i_target, o_setting); } /// @@ -82,7 +82,7 @@ struct attrEngineTraits<attr_eff_engine_fields, DRAM_WIDTH> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DRAM_WIDTH, i_target, i_setting); + return mss::attr::set_dram_width(i_target, i_setting); } /// @@ -158,7 +158,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_DQ_DQS> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS, i_target, o_setting); + return mss::attr::get_si_mc_rcv_imp_dq_dqs(i_target, o_setting); } /// @@ -170,7 +170,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_DQ_DQS> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS, i_target, i_setting); + return mss::attr::set_si_mc_rcv_imp_dq_dqs(i_target, i_setting); } /// @@ -208,7 +208,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_UP> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP, i_target, o_setting); + return mss::attr::get_si_mc_drv_imp_dq_dqs_pull_up(i_target, o_setting); } /// @@ -220,7 +220,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_UP> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP, i_target, i_setting); + return mss::attr::set_si_mc_drv_imp_dq_dqs_pull_up(i_target, i_setting); } /// @@ -258,7 +258,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN, i_target, o_setting); + return mss::attr::get_si_mc_drv_imp_dq_dqs_pull_down(i_target, o_setting); } /// @@ -270,7 +270,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN, i_target, i_setting); + return mss::attr::set_si_mc_drv_imp_dq_dqs_pull_down(i_target, i_setting); } /// @@ -309,7 +309,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_DQ_DQS> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS, i_target, o_setting); + return mss::attr::get_si_mc_drv_slew_rate_dq_dqs(i_target, o_setting); } /// @@ -321,7 +321,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_DQ_DQS> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS, i_target, i_setting); + return mss::attr::set_si_mc_drv_slew_rate_dq_dqs(i_target, i_setting); } /// @@ -359,7 +359,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CMD_ADDR> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR, i_target, o_setting); + return mss::attr::get_si_mc_drv_imp_cmd_addr(i_target, o_setting); } /// @@ -371,7 +371,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CMD_ADDR> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR, i_target, i_setting); + return mss::attr::set_si_mc_drv_imp_cmd_addr(i_target, i_setting); } /// @@ -409,7 +409,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CMD_ADDR> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR, i_target, o_setting); + return mss::attr::get_si_mc_drv_slew_rate_cmd_addr(i_target, o_setting); } /// @@ -421,7 +421,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CMD_ADDR> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR, i_target, i_setting); + return mss::attr::set_si_mc_drv_slew_rate_cmd_addr(i_target, i_setting); } /// @@ -459,7 +459,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CLK> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CLK, i_target, o_setting); + return mss::attr::get_si_mc_drv_imp_clk(i_target, o_setting); } /// @@ -471,7 +471,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_IMP_CLK> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CLK, i_target, i_setting); + return mss::attr::set_si_mc_drv_imp_clk(i_target, i_setting); } /// @@ -509,7 +509,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CLK> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK, i_target, o_setting); + return mss::attr::get_si_mc_drv_slew_rate_clk(i_target, o_setting); } /// @@ -521,7 +521,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_SLEW_RATE_CLK> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK, i_target, i_setting); + return mss::attr::set_si_mc_drv_slew_rate_clk(i_target, i_setting); } /// @@ -559,7 +559,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_ALERT_N> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_ALERT_N, i_target, o_setting); + return mss::attr::get_si_mc_rcv_imp_alert_n(i_target, o_setting); } /// @@ -571,7 +571,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_RCV_IMP_ALERT_N> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_ALERT_N, i_target, i_setting); + return mss::attr::set_si_mc_rcv_imp_alert_n(i_target, i_setting); } /// @@ -609,7 +609,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_NOM> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_RTT_NOM, i_target, o_setting); + return mss::attr::get_si_dram_rtt_nom(i_target, o_setting); } /// @@ -621,7 +621,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_NOM> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_DRAM_RTT_NOM, i_target, i_setting); + return mss::attr::set_si_dram_rtt_nom(i_target, i_setting); } /// @@ -659,7 +659,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_WR> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_RTT_WR, i_target, o_setting); + return mss::attr::get_si_dram_rtt_wr(i_target, o_setting); } /// @@ -671,7 +671,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_WR> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_DRAM_RTT_WR, i_target, i_setting); + return mss::attr::set_si_dram_rtt_wr(i_target, i_setting); } /// @@ -709,7 +709,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_PARK> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_RTT_PARK, i_target, o_setting); + return mss::attr::get_si_dram_rtt_park(i_target, o_setting); } /// @@ -721,7 +721,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_RTT_PARK> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_DRAM_RTT_PARK, i_target, i_setting); + return mss::attr::set_si_dram_rtt_park(i_target, i_setting); } /// @@ -759,7 +759,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_PREAMBLE> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_PREAMBLE, i_target, o_setting); + return mss::attr::get_si_dram_preamble(i_target, o_setting); } /// @@ -771,7 +771,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_PREAMBLE> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_DRAM_PREAMBLE, i_target, i_setting); + return mss::attr::set_si_dram_preamble(i_target, i_setting); } /// @@ -810,7 +810,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_EQ_DQ_DQS> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS, i_target, o_setting); + return mss::attr::get_si_mc_drv_eq_dq_dqs(i_target, o_setting); } /// @@ -822,7 +822,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_MC_DRV_EQ_DQ_DQS> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS, i_target, i_setting); + return mss::attr::set_si_mc_drv_eq_dq_dqs(i_target, i_setting); } /// @@ -860,7 +860,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_DRV_IMP_DQ_DQS> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS, i_target, o_setting); + return mss::attr::get_si_dram_drv_imp_dq_dqs(i_target, o_setting); } /// @@ -872,7 +872,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_DRAM_DRV_IMP_DQ_DQS> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS, i_target, i_setting); + return mss::attr::set_si_dram_drv_imp_dq_dqs(i_target, i_setting); } /// @@ -910,7 +910,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_RANGE> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE, i_target, o_setting); + return mss::attr::get_si_vref_dq_train_range(i_target, o_setting); } /// @@ -922,7 +922,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_RANGE> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE, i_target, i_setting); + return mss::attr::set_si_vref_dq_train_range(i_target, i_setting); } /// @@ -960,7 +960,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_VALUE> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE, i_target, o_setting); + return mss::attr::get_si_vref_dq_train_value(i_target, o_setting); } /// @@ -972,7 +972,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_VREF_DQ_TRAIN_VALUE> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE, i_target, o_setting); + return mss::attr::set_si_vref_dq_train_value(i_target, o_setting); } /// @@ -1010,7 +1010,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_WR> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_ODT_WR, i_target, o_setting); + return mss::attr::get_si_odt_wr(i_target, o_setting); } /// @@ -1022,7 +1022,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_WR> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_ODT_WR, i_target, i_setting); + return mss::attr::set_si_odt_wr(i_target, i_setting); } /// @@ -1095,7 +1095,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_RD> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_ODT_RD, i_target, o_setting); + return mss::attr::get_si_odt_rd(i_target, o_setting); } /// @@ -1107,7 +1107,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_ODT_RD> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_ODT_RD, i_target, i_setting); + return mss::attr::set_si_odt_rd(i_target, i_setting); } /// @@ -1179,7 +1179,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_GEARDOWN_MODE> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_GEARDOWN_MODE, i_target, o_setting); + return mss::attr::get_si_geardown_mode(i_target, o_setting); } /// @@ -1191,7 +1191,7 @@ struct attrEngineTraits<attr_si_engine_fields, SI_GEARDOWN_MODE> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_SI_GEARDOWN_MODE, i_target, i_setting); + return mss::attr::set_si_geardown_mode(i_target, i_setting); } /// diff --git a/src/import/generic/memory/lib/data_engine/data_engine.H b/src/import/generic/memory/lib/data_engine/data_engine.H index 6a7cbb437..aa0fb5f0a 100644 --- a/src/import/generic/memory/lib/data_engine/data_engine.H +++ b/src/import/generic/memory/lib/data_engine/data_engine.H @@ -236,6 +236,27 @@ struct attr_eff_engine } }; +/// +/// @brief Data structure to set effective config EFF data +/// @class attr_derived_engine +/// @tparam ET attr fields enum type +/// +template < typename ET, typename TT = attrEnumTraits<ET> > +struct attr_derived_engine +{ + using attr_eng_t = gen::attr_engine<ET, static_cast<ET>(TT::DISPATCHER)>; + + /// + /// @brief Sets attr fields denoted by an eum list + /// @param[in] i_target the DIMM target + /// @return FAPI2_RC_SUCCESS iff ok + /// + static fapi2::ReturnCode set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) + { + return attr_eng_t::set(i_target); + } +}; + }// mss #endif diff --git a/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H b/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H index 4a802bd46..57ae5355b 100644 --- a/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H +++ b/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H @@ -45,11 +45,29 @@ namespace mss /// /// @brief enum list of preliminary data fields /// +enum generic_metadata_fields +{ + // Template recursive base case + ATTR_METADATA_BASE_CASE = 0, + + // Attrs to set + DIMM_TYPE_METADATA = 1, + DRAM_GEN_METADATA = 2, + DIMM_POS_METADATA = 3, + + // Dispatcher set to last enum value + ATTR_METADATA_DISPATCHER = DIMM_POS_METADATA, +}; + +/// +/// @brief enum list of preliminary data fields +/// enum pre_data_init_fields { // Template recursive base case ATTR_PRE_DATA_ENGINE_CASE = 0, + // Attrs to set DIMM_TYPE = 1, DRAM_GEN = 2, HYBRID = 3, @@ -119,6 +137,13 @@ enum attr_si_engine_fields template< proc_type T, pre_data_init_fields TT > class preDataInitTraits; +/// +/// @brief Traits associated with DIMM positioning +/// @class dimmPosTraits +/// @tparam MC the MC type +/// +template< mss::mc_type MC > +class dimmPosTraits; /// /// @brief Forward declartion of traits for attrEngineTraits @@ -139,7 +164,7 @@ template < typename ET, ET T > struct setTimingTraits; /// -/// @brief Forward declartion of traits for attr_engine +/// @brief Forward declartion of traits for attrEnumTraits /// @class attrEnumTraits /// @tparam ET enum type /// diff --git a/src/import/generic/memory/lib/data_engine/data_engine_utils.H b/src/import/generic/memory/lib/data_engine/data_engine_utils.H index 5436fd5a3..aaf9a0485 100644 --- a/src/import/generic/memory/lib/data_engine/data_engine_utils.H +++ b/src/import/generic/memory/lib/data_engine/data_engine_utils.H @@ -39,6 +39,7 @@ #include <fapi2.H> #include <generic/memory/lib/utils/index.H> #include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/pos.H> #include <generic/memory/lib/spd/ddimm/efd_decoder.H> #include <generic/memory/lib/spd/spd_facade.H> @@ -61,8 +62,8 @@ struct DataSetterTraits2D; /// template < > struct DataSetterTraits2D < proc_type::NIMBUS, - procTraits<proc_type::NIMBUS>::PORTS_PER_MCS, - procTraits<proc_type::NIMBUS>::DIMMS_PER_PORT + mcTypeTraits<mc_type::NIMBUS>::PORTS_PER_MCS, + mcTypeTraits<mc_type::NIMBUS>::DIMMS_PER_PORT > { static constexpr fapi2::TargetType TARGET = fapi2::TARGET_TYPE_MCA; @@ -319,6 +320,31 @@ fapi_try_exit: /// /// @brief Helper function to update the structure that holds attr data +/// @tparam T the FAPI2 TargetType +/// @tparam IT Input data type +/// @tparam FFDC type +/// @tparam OT Output data type +/// @param[in] i_target the FAPI2 target +/// @param[in] i_setting array to set +/// @param[in] i_ffdc_code FFDC function code +/// @param[out] o_data output to set +/// @return FAPI2_RC_SUCCESS iff okay +/// +template < fapi2::TargetType T, + typename IT, + typename FFDC, + typename OT > +inline fapi2::ReturnCode update_data( const fapi2::Target<T>& i_target, + const IT i_setting, + const FFDC i_ffdc_code, + OT& o_data ) +{ + FAPI_DBG("Updating data with %d for %s", i_setting, spd::c_str(i_target)); + o_data = i_setting; + return fapi2::FAPI2_RC_SUCCESS; +} +/// +/// @brief Helper function to update the structure that holds attr data /// @tparam DT the data type /// @tparam IT Input data type /// @tparam FFDC type @@ -358,7 +384,7 @@ template< typename TT, inline fapi2::ReturnCode set_field(const fapi2::Target<T>& i_target, const IT i_setting) { - const auto l_attr_target = mss::find_target<TT::TARGET>(i_target); + const auto l_attr_target = mss::find_target<TT::TARGET_TYPE>(i_target); typename TT::attr_type l_attr_list = {}; FAPI_TRY( TT::get_attr(l_attr_target, l_attr_list) ); @@ -446,6 +472,24 @@ struct attr_engine { /// /// @brief Sets attributes fields F in ET + /// @tparam T the fapi2 target type + /// @param[in] i_target the fapi2 target + /// @return FAPI2_RC_SUCCESS iff oka + /// + template < fapi2::TargetType T > + static fapi2::ReturnCode single_set(const fapi2::Target<T>& i_target) + { + typename TT::attr_integral_type l_value = 0; + FAPI_TRY( TT::get_value_to_set(i_target, l_value) ); + + FAPI_TRY( set_field<TT>(i_target, l_value) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Sets attributes fields F in ET /// @tparam DT the data type /// @param[in] i_data the data (efd_decoder, spd_facade, etc.) /// @return FAPI2_RC_SUCCESS iff ok @@ -481,6 +525,26 @@ struct attr_engine fapi_try_exit: return fapi2::current_err; } + + /// + /// @brief Sets attributes fields F in ET + /// @tparam T the fapi2 target type + /// @param[in] i_target the fapi2 target + /// @return FAPI2_RC_SUCCESS iff ok + /// + template < fapi2::TargetType T > + static fapi2::ReturnCode set(const fapi2::Target<T>& i_target) + { + FAPI_TRY( (attr_engine<ET, F>::single_set(i_target)) ); + + // Compiler isn't smart enough to deduce F - 1u (decrementing the enum values by 1) + // Cast needed to help the compiler deduce this value is an ET type + // This does the recursive call to unroll a compile-time looping of a enum list of attrs to set + FAPI_TRY( (attr_engine < ET, static_cast<ET>(F - 1u) >::set(i_target)) ); + + fapi_try_exit: + return fapi2::current_err; + } }; /// @@ -498,6 +562,18 @@ struct attr_engine< ET, { /// /// @brief Sets attributes fields F in ET + /// @tparam T the fapi2 target type + /// @param[in] i_target the fapi2 target + /// @return FAPI2_RC_SUCCESS iff ok + /// + template < fapi2::TargetType T > + static fapi2::ReturnCode set(const fapi2::Target<T>& i_target) + { + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Sets attributes fields F in ET /// @tparam DT the data type /// @param[in] i_data the data (efd_decoder, spd_facade, etc.) /// @return FAPI2_RC_SUCCESS iff ok @@ -509,6 +585,30 @@ struct attr_engine< ET, } }; +/// +/// @brief Return a DIMM's position from a fapi2 target +/// @tparam TT Traits associated with DIMM position (e.g. dimmPosTraits) +/// @tparam OT the output type +/// @param[in] i_target a target representing the target in question +/// @param[out] o_value The position relative to the chip +/// +template< typename TT, typename OT> +fapi2::ReturnCode dimm_pos(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, OT& o_value) +{ + const auto l_proc_pos = mss::pos( TT::get_proc(i_target) ); + + typename TT::pos_type l_pos = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FAPI_POS, i_target, l_pos)); + + // To get the FAPI_POS to the equivilent of ATTR_POS, we need to normalize the fapi_pos value + // to the processor (stride across which ever processor we're on) and then add in the delta + // per processor as ATTR_POS isn't processor relative (delta is the total dimm on a processor) + o_value = ((l_pos - (l_proc_pos * TT::DIMM_STRIDE_PER_PROC)) % TT::TOTAL_DIMM) + (TT::TOTAL_DIMM * l_proc_pos); + +fapi_try_exit: + return fapi2::current_err; +} + }// gen }//mss diff --git a/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H b/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H index 69234151e..0fd4a0056 100644 --- a/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H +++ b/src/import/generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H @@ -39,14 +39,76 @@ #include <generic/memory/lib/data_engine/data_engine_traits_def.H> #include <generic/memory/lib/data_engine/data_engine_utils.H> #include <generic/memory/lib/spd/spd_facade.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> +#include <generic/memory/lib/mss_generic_attribute_setters.H> namespace mss { /// +/// @brief Helper function to get dimm_type from SPD +/// @param[in] i_spd_data SPD data +/// @param[in] i_setting value we want to set attr with +/// @return FAPI2_RC_SUCCESS iff okay +/// +static fapi2::ReturnCode get_dimm_type(const spd::facade& i_spd_data, + uint8_t& o_setting) +{ + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 3 (0x003): Key Byte / Module Type + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > BASE_MODULE_TYPE_MAP = + { + //{key byte, dimm type} + {1, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM}, + {2, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM}, + {10, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM}, + // All others reserved or not supported + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + uint8_t l_base_module_type = 0; + FAPI_TRY(i_spd_data.base_module(l_base_module_type)); + FAPI_TRY(lookup_table_check(l_dimm, BASE_MODULE_TYPE_MAP, SET_ATTR_DIMM_TYPE, l_base_module_type, o_setting)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Helper function to get dram_gen from SPD +/// @param[in] i_spd_data SPD data +/// @param[in] i_setting value we want to set attr with +/// @return FAPI2_RC_SUCCESS iff okay +/// +static fapi2::ReturnCode get_dram_gen(const spd::facade& i_spd_data, + uint8_t& o_setting) +{ + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 2 (0x002): Key Byte / DRAM Device Type + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_GEN_MAP = + { + //{key value, dram gen} + {0x0C, fapi2::ENUM_ATTR_MEM_EFF_DRAM_GEN_DDR4} + // Other key bytes reserved or not supported + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + uint8_t l_device_type = 0; + FAPI_TRY(i_spd_data.device_type(l_device_type)); + FAPI_TRY(lookup_table_check(l_dimm, DRAM_GEN_MAP, SET_ATTR_DRAM_GEN, l_device_type, o_setting)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief Traits for pre_data_engine /// @class attrEngineTraits -/// @note AXONE, DIMM_TYPE specialization +/// @note pre_data_init_fields, DIMM_TYPE specialization /// template<> struct attrEngineTraits<pre_data_init_fields, DIMM_TYPE> @@ -58,26 +120,26 @@ struct attrEngineTraits<pre_data_init_fields, DIMM_TYPE> /// /// @brief attribute getter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[out] o_setting array to populate /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DIMM_TYPE, i_target, o_setting); + return mss::attr::get_dimm_type(i_target, o_setting); } /// /// @brief attribute setter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[in] i_setting array to set /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DIMM_TYPE, i_target, i_setting); + return mss::attr::set_dimm_type(i_target, i_setting); } /// @@ -89,33 +151,14 @@ struct attrEngineTraits<pre_data_init_fields, DIMM_TYPE> static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, attr_integral_type& o_setting) { - // ========================================================= - // DDR4 SPD Document Release 4 - // Byte 3 (0x003): Key Byte / Module Type - // ========================================================= - static const std::vector< std::pair<uint8_t, uint8_t> > BASE_MODULE_TYPE_MAP = - { - //{key byte, dimm type} - {1, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM}, - {2, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM}, - {10, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM}, - // All others reserved or not supported - }; - - uint8_t l_base_module_type = 0; - FAPI_TRY(i_spd_data.base_module(l_base_module_type)); - FAPI_TRY(lookup_table_check(i_spd_data.get_dimm_target(), BASE_MODULE_TYPE_MAP, SET_ATTR_DIMM_TYPE, l_base_module_type, - o_setting)); - - fapi_try_exit: - return fapi2::current_err; + return get_dimm_type(i_spd_data, o_setting); } }; /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits -/// @note AXONE, DRAM_GEN specialization +/// @note pre_data_init_fields, DRAM_GEN specialization /// template<> struct attrEngineTraits<pre_data_init_fields, DRAM_GEN> @@ -127,26 +170,26 @@ struct attrEngineTraits<pre_data_init_fields, DRAM_GEN> /// /// @brief attribute getter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[out] o_setting array to populate /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DRAM_GEN, i_target, o_setting); + return mss::attr::get_dram_gen(i_target, o_setting); } /// /// @brief attribute setter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[in] i_setting array to set /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DRAM_GEN, i_target, i_setting); + return mss::attr::set_dram_gen(i_target, i_setting); } /// @@ -158,30 +201,14 @@ struct attrEngineTraits<pre_data_init_fields, DRAM_GEN> static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, attr_integral_type& o_setting) { - // ========================================================= - // DDR4 SPD Document Release 4 - // Byte 2 (0x002): Key Byte / DRAM Device Type - // ========================================================= - static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_GEN_MAP = - { - //{key value, dram gen} - {0x0C, fapi2::ENUM_ATTR_MEM_EFF_DRAM_GEN_DDR4} - // Other key bytes reserved or not supported - }; - - uint8_t l_device_type = 0; - FAPI_TRY(i_spd_data.device_type(l_device_type)); - FAPI_TRY(lookup_table_check(i_spd_data.get_dimm_target(), DRAM_GEN_MAP, SET_ATTR_DRAM_GEN, l_device_type, o_setting)); - - fapi_try_exit: - return fapi2::current_err; + return get_dram_gen(i_spd_data, o_setting); } }; /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits -/// @note AXONE, HYBRID specialization +/// @note pre_data_init_fields, HYBRID specialization /// template<> struct attrEngineTraits<pre_data_init_fields, HYBRID> @@ -193,26 +220,26 @@ struct attrEngineTraits<pre_data_init_fields, HYBRID> /// /// @brief attribute getter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[out] o_setting array to populate /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_HYBRID, i_target, o_setting); + return mss::attr::get_hybrid(i_target, o_setting); } /// /// @brief attribute setter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[in] i_setting array to set /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_HYBRID, i_target, i_setting); + return mss::attr::set_hybrid(i_target, i_setting); } /// @@ -248,7 +275,7 @@ struct attrEngineTraits<pre_data_init_fields, HYBRID> /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits -/// @note AXONE, HYBRID_MEDIA specialization +/// @note pre_data_init_fields, HYBRID_MEDIA specialization /// template<> struct attrEngineTraits<pre_data_init_fields, HYBRID_MEDIA> @@ -260,26 +287,26 @@ struct attrEngineTraits<pre_data_init_fields, HYBRID_MEDIA> /// /// @brief attribute getter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[out] o_setting array to populate /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_HYBRID_MEMORY_TYPE, i_target, o_setting); + return mss::attr::get_hybrid_memory_type(i_target, o_setting); } /// /// @brief attribute setter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[in] i_setting array to set /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_HYBRID_MEMORY_TYPE, i_target, i_setting); + return mss::attr::set_hybrid_memory_type(i_target, i_setting); } /// @@ -350,7 +377,7 @@ fapi_try_exit: /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits -/// @note AXONE, MRANKS specialization +/// @note pre_data_init_fields, MRANKS specialization /// template<> struct attrEngineTraits<pre_data_init_fields, MRANKS> @@ -362,26 +389,26 @@ struct attrEngineTraits<pre_data_init_fields, MRANKS> /// /// @brief attribute getter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[out] o_setting array to populate /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, o_setting); + return mss::attr::get_num_master_ranks_per_dimm(i_target, o_setting); } /// /// @brief attribute setter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[in] i_setting array to set /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, i_setting); + return mss::attr::set_num_master_ranks_per_dimm(i_target, i_setting); } /// @@ -403,7 +430,7 @@ struct attrEngineTraits<pre_data_init_fields, MRANKS> /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits -/// @note AXONE, DIMM_RANKS_CNFG specialization +/// @note pre_data_init_fields, DIMM_RANKS_CNFG specialization /// template<> struct attrEngineTraits<pre_data_init_fields, DIMM_RANKS_CNFG> @@ -415,26 +442,26 @@ struct attrEngineTraits<pre_data_init_fields, DIMM_RANKS_CNFG> /// /// @brief attribute getter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[out] o_setting array to populate /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED, i_target, o_setting); + return mss::attr::get_dimm_ranks_configed(i_target, o_setting); } /// /// @brief attribute setter - /// @param[in] i_target the MCS target + /// @param[in] i_target the attr target /// @param[in] i_setting array to set /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return FAPI_ATTR_SET(fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED, i_target, i_setting); + return mss::attr::set_dimm_ranks_configed(i_target, i_setting); } /// diff --git a/src/import/generic/memory/lib/data_engine/p9n/p9n_data_init_traits.H b/src/import/generic/memory/lib/data_engine/p9n/p9n_data_init_traits.H index 02254790e..5f0207b14 100644 --- a/src/import/generic/memory/lib/data_engine/p9n/p9n_data_init_traits.H +++ b/src/import/generic/memory/lib/data_engine/p9n/p9n_data_init_traits.H @@ -38,6 +38,8 @@ #include <fapi2.H> #include <generic/memory/lib/data_engine/data_engine_traits_def.H> +#include <generic/memory/lib/data_engine/data_engine.H> +#include <lib/mss_attribute_accessors.H> namespace mss { @@ -77,14 +79,9 @@ class preDataInitTraits<mss::proc_type::NIMBUS, DIMM_TYPE> /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - const attr_type& i_setting) + attr_type& i_setting) { - attr_type l_data = {}; - memcpy(l_data, i_setting, sizeof(l_data)); - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_TYPE, i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; + return FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_TYPE, i_target, i_setting); } }; @@ -123,15 +120,9 @@ class preDataInitTraits<mss::proc_type::NIMBUS, DRAM_GEN> /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - const attr_type& i_setting) + attr_type& i_setting) { - attr_type l_data = {}; - memcpy(l_data, i_setting, sizeof(l_data)); - - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_GEN, i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; + return FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_GEN, i_target, i_setting); } }; @@ -170,15 +161,9 @@ class preDataInitTraits<mss::proc_type::NIMBUS, HYBRID> /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - const attr_type& i_setting) + attr_type& i_setting) { - attr_type l_data = {}; - memcpy(l_data, i_setting, sizeof(l_data)); - - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_HYBRID, i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; + return FAPI_ATTR_SET(fapi2::ATTR_EFF_HYBRID, i_target, i_setting); } }; @@ -217,15 +202,9 @@ class preDataInitTraits<mss::proc_type::NIMBUS, HYBRID_MEDIA> /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - const attr_type& i_setting) + attr_type& i_setting) { - attr_type l_data = {}; - memcpy(l_data, i_setting, sizeof(l_data)); - - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_HYBRID_MEMORY_TYPE, i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; + return FAPI_ATTR_SET(fapi2::ATTR_EFF_HYBRID_MEMORY_TYPE, i_target, i_setting); } }; @@ -264,15 +243,9 @@ class preDataInitTraits<mss::proc_type::NIMBUS, MRANKS> /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - const attr_type& i_setting) + attr_type& i_setting) { - attr_type l_data = {}; - memcpy(l_data, i_setting, sizeof(l_data)); - - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; + return FAPI_ATTR_SET(fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, i_setting); } }; @@ -311,18 +284,205 @@ class preDataInitTraits<mss::proc_type::NIMBUS, DIMM_RANKS_CNFG> /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - const attr_type& i_setting) + attr_type& i_setting) { - attr_type l_data = {}; - memcpy(l_data, i_setting, sizeof(l_data)); + return FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED, i_target, i_setting); + } +}; - FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED, i_target, l_data) ); +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note AXONE, DIMM_TYPE_METADATA specialization +/// +template<> +struct attrEngineTraits<generic_metadata_fields, DIMM_TYPE_METADATA> +{ + using attr_type = fapi2::ATTR_MEM_DIMM_TYPE_METADATA_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_DIMM_TYPE_METADATA_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_TYPE_METADATA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_TYPE_METADATA, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_DIMM_TYPE_METADATA, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + return mss::eff_dimm_type(i_target, o_setting); + } +}; - fapi_try_exit: - return fapi2::current_err; +/// +/// @brief Traits associated with DIMM positioning +/// @class dimmPosTraits - NIMBUS specializattion +/// +template<> +class dimmPosTraits<mss::mc_type::NIMBUS> +{ + private: + using PT = posTraits<fapi2::TARGET_TYPE_DIMM>; + using MT = mss::mcTypeTraits<mc_type::NIMBUS>; + + public: + // Public interface syntatic sugar + using pos_type = PT::pos_type; + + // Proc 0 is DIMM 0-15, proc 2 is 64-79. 64 is the stride between processors + static constexpr auto DIMM_STRIDE_PER_PROC = 64; + static constexpr auto TOTAL_DIMM = MT::MC_PER_MODULE * MT::MCS_PER_MC * MT::PORTS_PER_MCS * MT::DIMMS_PER_PORT; + + /// + /// @brief Return the PROC_CHIP parent of a DIMM + /// @param[in] i_target the dimm target + /// @return the fapi2 proc target + /// + static fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> get_proc(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) + { + // Using fapi2 rather than mss::find as this is pretty low level stuff. + return i_target.getParent<fapi2::TARGET_TYPE_MCA>().getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); } }; +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note generic_metadata_fields, DRAM_GEN_METADATA specialization +/// +template<> +struct attrEngineTraits<generic_metadata_fields, DRAM_GEN_METADATA> +{ + using attr_type = fapi2::ATTR_MEM_DRAM_GEN_METADATA_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_DRAM_GEN_METADATA_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DRAM_GEN_METADATA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_DRAM_GEN_METADATA, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_DRAM_GEN_METADATA, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + return mss::eff_dram_gen(i_target, o_setting); + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note generic_metadata_fields, DIMM_POS_METADATA specialization +/// +template<> +struct attrEngineTraits<generic_metadata_fields, DIMM_POS_METADATA> +{ + using attr_type = fapi2::ATTR_MEM_DIMM_POS_METADATA_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_DIMM_POS_METADATA_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_POS_METADATA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_POS_METADATA, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_DIMM_POS_METADATA, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + using TT = mss::dimmPosTraits<mss::mc_type::NIMBUS>; + return gen::dimm_pos<TT>(i_target, o_setting); + } +}; + +/// +/// @brief Value traits for attr_eff_engine_fields +/// @class attrEngineTraits +/// @note attr_eff_engine_fields +/// +template < > +struct attrEnumTraits<generic_metadata_fields> +{ + static constexpr size_t DISPATCHER = ATTR_METADATA_DISPATCHER; +}; + }// mss #endif diff --git a/src/import/generic/memory/lib/data_engine/pre_data_init.H b/src/import/generic/memory/lib/data_engine/pre_data_init.H index b3e4de8ad..b8311f83e 100644 --- a/src/import/generic/memory/lib/data_engine/pre_data_init.H +++ b/src/import/generic/memory/lib/data_engine/pre_data_init.H @@ -250,10 +250,23 @@ class pre_data_engine /// @return FAPI2_RC_SUCCESS iff ok /// template <mss::proc_type P> -fapi2::ReturnCode set_pre_init_attrs( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const spd::facade& i_spd_decoder ) +inline fapi2::ReturnCode set_pre_init_attrs( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const spd::facade& i_spd_decoder ); + +/// +/// @brief Sets pre_eff_config attributes - NIMBUS specialization +/// @param[in] i_target the DIMM target +/// @param[in] i_spd_decoder SPD decoder +/// @return FAPI2_RC_SUCCESS iff ok +/// +template <> +inline fapi2::ReturnCode set_pre_init_attrs<mss::proc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& + i_target, + const spd::facade& i_spd_decoder ) { - mss::pre_data_engine<P> l_data_engine(i_target, i_spd_decoder); + // TK explicitly forcing this API to only run in Nimbus, need to move pre_data_engine to Nimbus chip path, + // using template recursive algorithm moving forward + mss::pre_data_engine<mss::proc_type::NIMBUS> l_data_engine(i_target, i_spd_decoder); // Set attributes needed before eff_config // DIMM type and DRAM gen are needed for c_str to aid debugging @@ -270,6 +283,8 @@ fapi2::ReturnCode set_pre_init_attrs( const fapi2::Target<fapi2::TARGET_TYPE_DIM FAPI_TRY(l_data_engine.set_dimm_ranks_configured(), "Failed to set DIMM ranks configured %s", mss::spd::c_str(i_target) ); + FAPI_TRY( mss::attr_derived_engine<mss::generic_metadata_fields>::set(i_target) ); + fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/generic/memory/lib/mss_generic_attribute_getters.H b/src/import/generic/memory/lib/mss_generic_attribute_getters.H index 3b01d0c4a..613ddad0a 100644 --- a/src/import/generic/memory/lib/mss_generic_attribute_getters.H +++ b/src/import/generic/memory/lib/mss_generic_attribute_getters.H @@ -37,6 +37,77 @@ namespace mss namespace attr { /// +/// @brief ATTR_MEM_DIMM_POS_METADATA getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint32_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_other_attr_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note To get the FAPI_POS to the equivilent of ATTR_POS, we need to normalize the fapi_pos +/// value to the processor (stride across which ever processor we're on) and then add +/// in the delta per processor as ATTR_POS isn't processor relative (delta is the total +/// dimm on a processor) +/// +inline fapi2::ReturnCode get_dimm_pos_metadata(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint32_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_POS_METADATA, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_POS_METADATA: 0x%lx", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DRAM_GEN_METADATA getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_other_attr_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note DRAM Device Type. Decodes SPD byte 2. Created for use by attributes that need this +/// data earlier than eff_config, such as c_str and the hypervisor. Not meant for direct +/// HWP use. This is just an abstraction of any chip specific EFF_DRAM_GEN attribute. +/// +inline fapi2::ReturnCode get_dram_gen_metadata(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DRAM_GEN_METADATA, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DRAM_GEN_METADATA: 0x%lx", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_DIMM_TYPE_METADATA getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_other_attr_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Base Module Type. Decodes SPD Byte 3 (bits 3~0). Created for use by attributes that +/// need this data earlier than eff_config, such as c_str and the hypervisor. Not meant +/// for direct HWP use. This is just an abstraction of any chip specific EFF_DIMM_TYPE +/// attribute. +/// +inline fapi2::ReturnCode get_dimm_type_metadata(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_TYPE_METADATA, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_DIMM_TYPE_METADATA: 0x%lx", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + + +/// /// @brief ATTR_MEM_DRAM_CWL getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT /// @param[out] uint8_t& reference to store the value diff --git a/src/import/generic/memory/lib/utils/c_str.C b/src/import/generic/memory/lib/utils/c_str.C index 9b0333e48..bea66ea2e 100644 --- a/src/import/generic/memory/lib/utils/c_str.C +++ b/src/import/generic/memory/lib/utils/c_str.C @@ -28,7 +28,7 @@ /// @brief Storage for the C-string name of a thing /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: HB:FSP diff --git a/src/import/generic/memory/lib/utils/c_str.H b/src/import/generic/memory/lib/utils/c_str.H index ee1c044c2..d0e5eb6ae 100644 --- a/src/import/generic/memory/lib/utils/c_str.H +++ b/src/import/generic/memory/lib/utils/c_str.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,7 +28,7 @@ /// @brief Function to return the C-string name of a thing /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: HB:FSP @@ -37,7 +37,6 @@ #define _MSS_C_STR_H_ #include <fapi2.H> -#include <generic/memory/lib/utils/index.H> namespace mss { @@ -72,36 +71,28 @@ inline const char* c_str( const fapi2::template Target<T>& i_target ) return c_str_storage; } +/// +/// @brief fapi2::Target c_str general declaration +/// @param[in] i_target - target you want the name for +/// @return const char * +/// @note DIMM specialization +/// template<> inline const char* c_str( const fapi2::template Target<fapi2::TARGET_TYPE_DIMM>& i_target ) { - const auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>(); - const auto l_mcs = l_mca.getParent<fapi2::TARGET_TYPE_MCS>(); + static constexpr auto l_max_gen = 3; + static constexpr auto l_max_type = 5; - constexpr auto l_max_gen = 3; - constexpr auto l_max_type = 4; - const char* const l_map_gen_to_string[l_max_gen] = {"empty", "DDR3", "DDR4"}; - const char* const l_map_type_to_string[l_max_type] = {"empty", "RDIMM", "UDIMM", "LRDIMM"}; - - uint8_t l_type = 0; uint8_t l_gen = 0; - char l_buffer[fapi2::MAX_ECMD_STRING_LEN] = {}; - - fapi2::toString( i_target, c_str_storage, fapi2::MAX_ECMD_STRING_LEN ); + uint8_t l_type = 0; // Had to unroll FAPI_TRY so that fapi2::current_err doesn't get overwritten, causes errors // when calling c_str inside of a function that returns fapi2::ReturnCode - constexpr size_t PORTS_PER_MCS = 2; - constexpr size_t MAX_DIMM_PER_PORT = 2; - uint8_t l_value[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; - - if (FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_TYPE, l_mcs, l_value) != fapi2::FAPI2_RC_SUCCESS) + if (FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_TYPE_METADATA, i_target, l_type) != fapi2::FAPI2_RC_SUCCESS) { goto fapi_try_exit; } - l_type = l_value[mss::index(l_mca)][mss::index(i_target)]; - if (l_type >= l_max_type) { goto fapi_try_exit; @@ -109,20 +100,26 @@ inline const char* c_str( const fapi2::template Target<fapi2::TARGET_TYPE_DIMM>& // Had to unroll FAPI_TRY so that fapi2::current_err doesn't get overwritten, causes errors // when calling c_str inside of a function that returns fapi2::ReturnCode - if (FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_GEN, l_mcs, l_value) != fapi2::FAPI2_RC_SUCCESS) + if (FAPI_ATTR_GET(fapi2::ATTR_MEM_DRAM_GEN_METADATA, i_target, l_gen) != fapi2::FAPI2_RC_SUCCESS) { goto fapi_try_exit; } - l_gen = l_value[mss::index(l_mca)][mss::index(i_target)]; - if (l_gen >= l_max_gen) { goto fapi_try_exit; } - snprintf(l_buffer, fapi2::MAX_ECMD_STRING_LEN, " %s (%s)", l_map_type_to_string[l_type], l_map_gen_to_string[l_gen]); - return strncat( c_str_storage, l_buffer, fapi2::MAX_ECMD_STRING_LEN - strlen(c_str_storage) ); + { + const char* const l_map_gen_to_string[l_max_gen] = {"empty", "DDR3", "DDR4"}; + const char* const l_map_type_to_string[l_max_type] = {"empty", "RDIMM", "UDIMM", "LRDIMM", "DDIMM"}; + + char l_buffer[fapi2::MAX_ECMD_STRING_LEN] = {}; + fapi2::toString( i_target, c_str_storage, fapi2::MAX_ECMD_STRING_LEN ); + + snprintf(l_buffer, fapi2::MAX_ECMD_STRING_LEN, " %s (%s)", l_map_type_to_string[l_type], l_map_gen_to_string[l_gen]); + return strncat( c_str_storage, l_buffer, fapi2::MAX_ECMD_STRING_LEN - strlen(c_str_storage) ); + } fapi_try_exit: // Probably the best we're going to do ... diff --git a/src/import/generic/memory/lib/utils/find.H b/src/import/generic/memory/lib/utils/find.H index df7d55d41..c22199b6d 100644 --- a/src/import/generic/memory/lib/utils/find.H +++ b/src/import/generic/memory/lib/utils/find.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,120 +38,110 @@ #include <fapi2.H> #include <vector> -#include <generic/memory/lib/utils/pos.H> -#include <generic/memory/lib/utils/c_str.H> namespace mss { /// -/// @brief find a set of elements based on a fapi2 target +/// @brief Helper to find a set of elements based on a fapi2 target /// @tparam M the target type to be returned /// @tparam T the fapi2 target type of the argument /// @param[in] i_target the fapi2 target T +/// @param[in] std::false_type tag dispatch if T != M /// @param[in] i_state [optional] fapi2 target state (defaults to TARGET_STATE_FUNCTIONAL) /// @return a vector of M targets. -/// @note Only works for valid parent-child relationships -/// So calling find_targets<TARGET_TYPE_DIMM>(l_mca) will work here -/// but calling find_targets<TARGET_TYPE_DIMM>(l_mcs) will not work -/// Compiler will freak out and we'll never get a bad relationship/ error at runtime -/// If we do, it's on fapi2 /// template< fapi2::TargetType M, fapi2::TargetType T > -inline std::vector< fapi2::Target<M> > find_targets( const fapi2::Target<T>& i_target, - fapi2::TargetState i_state = fapi2::TARGET_STATE_FUNCTIONAL ) +static inline std::vector< fapi2::Target<M> > find_targets_impl( const fapi2::Target<T>& i_target, + std::false_type, + fapi2::TargetState i_state ) { return i_target.template getChildren<M>(i_state); } /// -/// @brief find an element based on a fapi2 target +/// @brief Helper to find a set of elements based on a fapi2 target /// @tparam M the target type to be returned /// @tparam T the fapi2 target type of the argument /// @param[in] i_target the fapi2 target T -/// @return an M target. -/// @note Only works for valid parent-child relationships -/// Will work for MCA and DIMM -/// Will not work for MCS and DIMM -/// The compiler will let you know if it doesn't work +/// @param[in] std::true_type tag dispatch if T == M +/// @param[in] i_state [optional] fapi2 target state (defaults to TARGET_STATE_FUNCTIONAL) +/// @return a vector of M targets. /// template< fapi2::TargetType M, fapi2::TargetType T > -inline fapi2::Target<M> find_target( const fapi2::Target<T>& i_target ) +static inline std::vector< fapi2::Target<M> > find_targets_impl( const fapi2::Target<T>& i_target, + std::true_type, + fapi2::TargetState i_state ) { - return i_target.template getParent<M>(); + return std::vector< fapi2::Target<M> > {i_target}; } /// -/// @brief find the union of functionl targets and any magic targets -/// @note The PHY has a logic block which is only contained in the 0th PHY in the controller. -/// This makes the 0th PHY 'magic' in that it needs to always be present if not functional. -/// This function returns all functional targets and includes the magic target whether or not -/// it is truly functional. +/// @brief find a set of elements based on a fapi2 target /// @tparam M the target type to be returned /// @tparam T the fapi2 target type of the argument /// @param[in] i_target the fapi2 target T +/// @param[in] std::true_type tag dispatch if T == M +/// @param[in] i_state [optional] fapi2 target state (defaults to TARGET_STATE_FUNCTIONAL) /// @return a vector of M targets. +/// @note Only works for valid parent-child relationships +/// So calling find_targets<TARGET_TYPE_DIMM>(l_mca) will work here +/// but calling find_targets<TARGET_TYPE_DIMM>(l_mcs) will not work +/// Compiler will freak out and we'll never get a bad relationship/ error at runtime +/// If we do, it's on fapi2 /// template< fapi2::TargetType M, fapi2::TargetType T > -inline std::vector< fapi2::Target<M> > find_targets_with_magic( const fapi2::Target<T>& i_target); +inline std::vector< fapi2::Target<M> > find_targets( const fapi2::Target<T>& i_target, + fapi2::TargetState i_state = fapi2::TARGET_STATE_FUNCTIONAL ) +{ + return find_targets_impl<M>(i_target, std::integral_constant<bool, M == T> {}, i_state); +} /// -/// @brief find a set of magic elements based on a fapi2 target -/// @note The PHY has a logic block which is only contained in the 0th PHY in the controller. -/// This makes the 0th PHY 'magic' in that it needs to always be present if not functional. -/// This function returns all magic targets whether or not it is truly functional. -/// It does not include other functional or present targets. +/// @brief Helper to find an element based on a fapi2 target /// @tparam M the target type to be returned /// @tparam T the fapi2 target type of the argument /// @param[in] i_target the fapi2 target T -/// @return a vector of M targets. +/// @param[in] std::false_type tag dispatch if T != M +/// @return an M target. +/// @note Only works for valid parent-child relationships /// template< fapi2::TargetType M, fapi2::TargetType T > -inline std::vector< fapi2::Target<M> > find_magic_targets( const fapi2::Target<T>& i_target); - -/// -/// @brief find the McBIST given a McBIST -/// @param[in] i_self the fapi2 target mcBIST -/// @return a McBIST target. -/// -template<> -inline fapi2::Target<fapi2::TARGET_TYPE_MCBIST> find_target( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_self) -{ - return i_self; -} - -/// -/// @brief find the MCS given an MCS -/// @param[in] i_self the fapi2 target MCS -/// @return a MCS target. -/// -template<> -inline fapi2::Target<fapi2::TARGET_TYPE_MCS> find_target( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_self) +static inline fapi2::Target<M> find_target_impl( const fapi2::Target<T>& i_target, + std::false_type ) { - return i_self; + return i_target.template getParent<M>(); } /// -/// @brief find the MEM_PORT given a MEM_PORT -/// @param[in] i_self the fapi2 target MEM_PORT -/// @return a MEM_PORT target. +/// @brief Helper to find an element based on a fapi2 target +/// @tparam M the target type to be returned +/// @tparam T the fapi2 target type of the argument +/// @param[in] i_target the fapi2 target T +/// @return an M target. +/// @note Only works for valid parent-child relationships /// -template<> -inline fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> find_target( const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& - i_self) +template< fapi2::TargetType M, fapi2::TargetType T > +static inline fapi2::Target<M> find_target_impl( const fapi2::Target<T>& i_target, + std::true_type ) { - return i_self; + return i_target; } /// -/// @brief find the OCMB_CHIP given a OCMB_CHIP -/// @param[in] i_self the fapi2 target OCMB_CHIP -/// @return a OCMB_CHIP target. +/// @brief find an element based on a fapi2 target +/// @tparam M the target type to be returned +/// @tparam T the fapi2 target type of the argument +/// @param[in] i_target the fapi2 target T +/// @return an M target. +/// @note Only works for valid parent-child relationships +/// Will work for MCA and DIMM +/// Will not work for MCS and DIMM +/// The compiler will let you know if it doesn't work /// -template<> -inline fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> find_target( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& - i_self) +template< fapi2::TargetType M, fapi2::TargetType T > +inline fapi2::Target<M> find_target( const fapi2::Target<T>& i_target) { - return i_self; + return find_target_impl<M>(i_target, std::integral_constant<bool, M == T> {}); } /// @@ -160,7 +150,7 @@ inline fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> find_target( const fapi2::Tar /// @return a McBIST target. /// template<> -inline fapi2::Target<fapi2::TARGET_TYPE_MCBIST> find_target( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) +inline fapi2::Target<fapi2::TARGET_TYPE_MCBIST> find_target(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) { return i_target.getParent<fapi2::TARGET_TYPE_MCA>().getParent<fapi2::TARGET_TYPE_MCBIST>(); } @@ -171,7 +161,7 @@ inline fapi2::Target<fapi2::TARGET_TYPE_MCBIST> find_target( const fapi2::Target /// @return a DMI target. /// template<> -inline fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> find_target( const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target) +inline fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> find_target(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target) { return i_target.getParent<fapi2::TARGET_TYPE_MEMBUF_CHIP>() .getParent<fapi2::TARGET_TYPE_DMI>() @@ -184,7 +174,7 @@ inline fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> find_target( const fapi2::Tar /// @return a PROC_CHIP target. /// template<> -inline fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> find_target( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& +inline fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> find_target(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) { return i_target.getParent<fapi2::TARGET_TYPE_OMI>() @@ -198,48 +188,24 @@ inline fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> find_target( const fapi2::Tar /// @return a DMI target. /// template<> -inline fapi2::Target<fapi2::TARGET_TYPE_DMI> find_target( const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target) +inline fapi2::Target<fapi2::TARGET_TYPE_DMI> find_target(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target) { return i_target.getParent<fapi2::TARGET_TYPE_MEMBUF_CHIP>().getParent<fapi2::TARGET_TYPE_DMI>(); } /// -/// @brief find the DMI given a MEMBUF -/// @param[in] i_target the fapi2 target MEMBUF -/// @return a DMI target. -/// -template<> -inline fapi2::Target<fapi2::TARGET_TYPE_DMI> find_target( const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& i_target) -{ - return i_target.getParent<fapi2::TARGET_TYPE_DMI>(); -} - -/// /// @brief find the PROC given a MEMBUF /// @param[in] i_target the fapi2 target MEMBUF /// @return a PROC target. /// template<> -inline fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> find_target( const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& +inline fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> find_target(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& i_target) { return i_target.getParent<fapi2::TARGET_TYPE_DMI>().getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); } /// -/// @brief find all the DMIs connected to an PROC_CHIP -/// @param[in] i_target a fapi2::Target DMI -/// @return a vector of fapi2::TARGET_TYPE_MBA -/// -template<> -inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_DMI> > -find_targets( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, - fapi2::TargetState i_state ) -{ - return i_target.getChildren<fapi2::TARGET_TYPE_DMI>(i_state); -} - -/// /// @brief find all the OCMB_CHIPs connected to a PROC_CHIP /// @param[in] i_target a fapi2::Target PROC_CHIP /// @return a vector of fapi2::TARGET_TYPE_OCMB_CHIP @@ -264,32 +230,6 @@ find_targets( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, } /// -/// @brief find all the MEMBUFs connected to an DMI -/// @param[in] i_target a fapi2::Target DMI -/// @return a vector of fapi2::TARGET_TYPE_MEMBUF_CHIP -/// -template<> -inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> > -find_targets( const fapi2::Target<fapi2::TARGET_TYPE_DMI>& i_target, - fapi2::TargetState i_state ) -{ - return i_target.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>(i_state); -} - -/// -/// @brief find all the MBAs connected to an MEMBUF -/// @param[in] i_target a fapi2::Target MEMBUF_CHIP -/// @return a vector of fapi2::TARGET_TYPE_MBA -/// -template<> -inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MBA> > -find_targets( const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& i_target, - fapi2::TargetState i_state ) -{ - return i_target.getChildren<fapi2::TARGET_TYPE_MBA>(i_state); -} - -/// /// @brief find all the MBA connected to an DMI /// @param[in] i_target a fapi2::Target DMI /// @return a vector of fapi2::TARGET_TYPE_MBA @@ -343,7 +283,6 @@ find_targets( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, { std::vector< fapi2::Target<fapi2::TARGET_TYPE_DIMM> > l_dimms; - // At this time, fapi2 (cronus?) doesn't seem to recognize a DIMM is the child of an MCS. for (const auto& p : i_target.getChildren<fapi2::TARGET_TYPE_MCA>(i_state)) { auto l_these_dimms( p.getChildren<fapi2::TARGET_TYPE_DIMM>(i_state) ); @@ -375,176 +314,6 @@ find_targets( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, } /// -/// @brief find all the MCS connected to a PROC_CHIP -/// @param[in] i_target a fapi2::Target PROC_CHIP -/// @return a vector of fapi2::TARGET_TYPE_MCS -/// -template<> -inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCS> > find_targets -( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, - fapi2::TargetState i_state ) -{ - return i_target.getChildren<fapi2::TARGET_TYPE_MCS>(i_state); -} - -/// -/// @brief find all the MCS connected to an MCBIST -/// @param[in] i_target a fapi2::Target MCBIST -/// @return a vector of fapi2::TARGET_TYPE_MCS -/// @note Cronus should support MCS children of an MCBIST - so this might be temporary -/// -template<> -inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCS> > find_targets -( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - fapi2::TargetState i_state ) -{ - std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCS> > l_mcses; - - // At this time, fapi2 (cronus?) doesn't seem to recognize a MCS is the child of an MCBIST - for (const auto& p : i_target.getChildren<fapi2::TARGET_TYPE_MCA>(i_state)) - { - fapi2::Target<fapi2::TARGET_TYPE_MCS> l_mcs = p.getParent<fapi2::TARGET_TYPE_MCS>(); - - if ( l_mcses.end() == std::find_if( l_mcses.begin(), l_mcses.end(), - [l_mcs](const fapi2::Target<fapi2::TARGET_TYPE_MCS>& c) - { - return l_mcs == c; - }) ) - { - l_mcses.push_back(l_mcs); - } - } - - return l_mcses; -} - -/// -/// @brief find all the MCA connected to an MCBIST -/// @param[in] i_target a fapi2::Target MCBIST -/// @return a vector of fapi2::TARGET_TYPE_MCA -/// -template<> -inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> > find_targets -( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - fapi2::TargetState i_state ) -{ - return i_target.getChildren<fapi2::TARGET_TYPE_MCA>(i_state); -} - -/// -/// @brief find all the MCA connected to an MCA -/// @param[in] i_target a fapi2::Target MCA -/// @return a vector of fapi2::TARGET_TYPE_MCA -/// -template<> -inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> > find_targets -( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - fapi2::TargetState i_state ) -{ - // TODO - RTC:174905. Find out if we really need a find API that returns a vector of MCA from an MCA - std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> > l_temp = {i_target}; - return l_temp; -} - -/// -/// @brief find the magic MCA connected to an MCBIST -/// @param[in] i_target the fapi2::Target MCBIST -/// @return a vector of fapi2::TARGET_TYPE_MCA -/// -template<> -inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> > find_magic_targets -( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target) -{ - // The magic port is in position 0, relative to the MCBIST - constexpr uint64_t RELATIVE_MAGIC_POS = 0; - - // This is only one magic MCA on every MCBIST, so we only return a vector of one - std::vector<fapi2::Target<fapi2::TARGET_TYPE_MCA>> l_magic_ports; - - // Get all the present MCA children and find the target with the relative position of 0 - for (const auto& p : i_target.getChildren<fapi2::TARGET_TYPE_MCA>(fapi2::TARGET_STATE_PRESENT)) - { - if (mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(p) == RELATIVE_MAGIC_POS) - { - l_magic_ports.push_back(p); - } - } - - // We don't care if the vector is empty. We don't know what the caller will do with this - // and they might not care if there is no magic port either ... - return l_magic_ports; -} - -/// -/// @brief find the union of functionl targets and any magic targets -/// @param[in] i_target the fapi2::Target MCBIST -/// @return a vector of i2::Target<fapi2::TARGET_TYPE_MCA> -/// -template<> -inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> > find_targets_with_magic -( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target) -{ - // We need the union of the functional target list and the magic target list. We can - // get a little tricky with the MCA's - we know there's only one magic port. - // So if the one magic port isn't in the list of functional ports, add it - auto l_magic_ports = find_magic_targets<fapi2::TARGET_TYPE_MCA>(i_target); - - if (l_magic_ports.size() != 1) - { - FAPI_ERR("Found wrong number of magic ports on %s (%d)", mss::c_str(i_target), l_magic_ports.size()); - fapi2::Assert(false); - } - - auto l_ports = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); - const auto l_magic_pos = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(l_magic_ports[0]); - const auto l_magic_port = std::find_if(l_ports.begin(), l_ports.end(), - [&l_magic_pos](const fapi2::Target<fapi2::TARGET_TYPE_MCA>& t) - { - // Check ports by relative position. - const auto l_pos = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(t); - FAPI_DBG("checking for magic port at %d candidate is %d", l_magic_pos, l_pos); - return l_magic_pos == l_pos; - }); - - if (l_magic_port == l_ports.end()) - { - // Add the magic port to the front of the port vector. - FAPI_DBG("inserting magic port %d", l_magic_pos); - l_ports.insert(l_ports.begin(), l_magic_ports[0]); - } - - // In either case, l_ports is the proper thing to return. Either the magic port was in - // l_ports or it is now because we inserted it. - return l_ports; -} - -/// -/// @brief find all the MCA connected to an MCS -/// @param[in] i_target a fapi2::Target MCS -/// @return a vector of fapi2::TARGET_TYPE_MCA -/// -template<> -inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> > find_targets -( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, - fapi2::TargetState i_state ) -{ - return i_target.getChildren<fapi2::TARGET_TYPE_MCA>(i_state); -} - -/// -/// @brief find all the DIMM connected to an MCA -/// @param[in] i_target a fapi2::Target MCA -/// @return a vector of fapi2::TARGET_TYPE_DIMM -/// -template<> -inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_DIMM> > find_targets -( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - fapi2::TargetState i_state ) -{ - return i_target.getChildren<fapi2::TARGET_TYPE_DIMM>(i_state); -} - -/// /// @brief find the MCS given a DIMM /// @param[in] i_target the fapi2 target DIMM /// @return a MCS target. @@ -556,19 +325,6 @@ inline fapi2::Target<fapi2::TARGET_TYPE_MCS> find_target( const fapi2::Target<fa } /// -/// @brief find all the MCBISTs connected to a PROC_CHIP -/// @param[in] i_target a fapi2::Target PROC_CHIP -/// @return a vector of fapi2::TARGET_TYPE_MCBIST -/// -template<> -inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCBIST> > find_targets( - const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, - fapi2::TargetState i_state ) -{ - return i_target.getChildren<fapi2::TARGET_TYPE_MCBIST>(i_state); -} - -/// /// @brief find a key value from a vector of STL pairs /// @tparam T input type /// @tparam OT the output type to be returned @@ -676,30 +432,6 @@ bool find_value_from_key( const std::pair<T, OT> (&i_array)[N], return false; } -/// -/// @brief Determine if a thing is functional -/// @tparam P, the type of the parent which holds the things of interest -/// @tparam I, the type of the item we want to check for -/// @param[in] i_target the parent containing the thing we're looking for -/// @param[in] i_rel_pos the relative position of the item of interest. -/// @return bool true iff the thing at i_rel_pos is noted as functional -/// -template< fapi2::TargetType I, fapi2::TargetType P > -bool is_functional( const fapi2::Target<P>& i_target, const uint64_t i_rel_pos ) -{ - // Not sure of a good way to do this ... we get all the functional - // children of the parent and look for our relative position ... - for (const auto& i : i_target.template getChildren<I>(fapi2::TARGET_STATE_FUNCTIONAL)) - { - if (mss::template relative_pos<P>(i) == i_rel_pos) - { - return true; - } - } - - return false; -} - }// mss #endif diff --git a/src/import/generic/memory/lib/utils/find_magic.H b/src/import/generic/memory/lib/utils/find_magic.H index 0e8a3f1ef..a67d4f2e8 100644 --- a/src/import/generic/memory/lib/utils/find_magic.H +++ b/src/import/generic/memory/lib/utils/find_magic.H @@ -22,3 +22,143 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +#ifndef _MSS_FIND_WITH_MAGIC_H +#define _MSS_FIND_WITH_MAGIC_H + +#include <fapi2.H> +#include <vector> +#include <generic/memory/lib/utils/pos.H> +#include <generic/memory/lib/utils/c_str.H> +#include <generic/memory/lib/utils/find.H> + +namespace mss +{ + +/// +/// @brief find the union of functionl targets and any magic targets +/// @note The PHY has a logic block which is only contained in the 0th PHY in the controller. +/// This makes the 0th PHY 'magic' in that it needs to always be present if not functional. +/// This function returns all functional targets and includes the magic target whether or not +/// it is truly functional. +/// @tparam M the target type to be returned +/// @tparam T the fapi2 target type of the argument +/// @param[in] i_target the fapi2 target T +/// @return a vector of M targets. +/// +template< fapi2::TargetType M, fapi2::TargetType T > +inline std::vector< fapi2::Target<M> > find_targets_with_magic( const fapi2::Target<T>& i_target); + +/// +/// @brief find a set of magic elements based on a fapi2 target +/// @note The PHY has a logic block which is only contained in the 0th PHY in the controller. +/// This makes the 0th PHY 'magic' in that it needs to always be present if not functional. +/// This function returns all magic targets whether or not it is truly functional. +/// It does not include other functional or present targets. +/// @tparam M the target type to be returned +/// @tparam T the fapi2 target type of the argument +/// @param[in] i_target the fapi2 target T +/// @return a vector of M targets. +/// +template< fapi2::TargetType M, fapi2::TargetType T > +inline std::vector< fapi2::Target<M> > find_magic_targets( const fapi2::Target<T>& i_target); + +/// +/// @brief find the magic MCA connected to an MCBIST +/// @param[in] i_target the fapi2::Target MCBIST +/// @return a vector of fapi2::TARGET_TYPE_MCA +/// +template<> +inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> > +find_magic_targets(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target) +{ + // The magic port is in position 0, relative to the MCBIST + constexpr uint64_t RELATIVE_MAGIC_POS = 0; + + // This is only one magic MCA on every MCBIST, so we only return a vector of one + std::vector<fapi2::Target<fapi2::TARGET_TYPE_MCA>> l_magic_ports; + + // Get all the present MCA children and find the target with the relative position of 0 + for (const auto& p : i_target.getChildren<fapi2::TARGET_TYPE_MCA>(fapi2::TARGET_STATE_PRESENT)) + { + if (mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(p) == RELATIVE_MAGIC_POS) + { + l_magic_ports.push_back(p); + } + } + + // We don't care if the vector is empty. We don't know what the caller will do with this + // and they might not care if there is no magic port either ... + return l_magic_ports; +} + +/// +/// @brief find the union of functionl targets and any magic targets +/// @param[in] i_target the fapi2::Target MCBIST +/// @return a vector of i2::Target<fapi2::TARGET_TYPE_MCA> +/// +template<> +inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> > +find_targets_with_magic( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target) +{ + // We need the union of the functional target list and the magic target list. We can + // get a little tricky with the MCA's - we know there's only one magic port. + // So if the one magic port isn't in the list of functional ports, add it + auto l_magic_ports = find_magic_targets<fapi2::TARGET_TYPE_MCA>(i_target); + + if (l_magic_ports.size() != 1) + { + FAPI_ERR("Found wrong number of magic ports on %s (%d)", mss::c_str(i_target), l_magic_ports.size()); + fapi2::Assert(false); + } + + auto l_ports = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); + const auto l_magic_pos = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(l_magic_ports[0]); + const auto l_magic_port = std::find_if(l_ports.begin(), l_ports.end(), + [&l_magic_pos](const fapi2::Target<fapi2::TARGET_TYPE_MCA>& t) + { + // Check ports by relative position. + const auto l_pos = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(t); + FAPI_DBG("checking for magic port at %d candidate is %d", l_magic_pos, l_pos); + return l_magic_pos == l_pos; + }); + + if (l_magic_port == l_ports.end()) + { + // Add the magic port to the front of the port vector. + FAPI_DBG("inserting magic port %d", l_magic_pos); + l_ports.insert(l_ports.begin(), l_magic_ports[0]); + } + + // In either case, l_ports is the proper thing to return. Either the magic port was in + // l_ports or it is now because we inserted it. + return l_ports; +} + +/// +/// @brief Determine if a thing is functional +/// @tparam I, the type of the item we want to check for +/// @tparam P, the type of the parent which holds the things of interest +/// @param[in] i_target the parent containing the thing we're looking for +/// @param[in] i_rel_pos the relative position of the item of interest. +/// @return bool true iff the thing at i_rel_pos is noted as functional +/// +template< fapi2::TargetType I, fapi2::TargetType P > +bool is_functional( const fapi2::Target<P>& i_target, const uint64_t i_rel_pos ) +{ + // Not sure of a good way to do this ... we get all the functional + // children of the parent and look for our relative position ... + for (const auto& i : i_target.template getChildren<I>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + if (mss::template relative_pos<P>(i) == i_rel_pos) + { + return true; + } + } + + return false; +} + +}// mss + +#endif diff --git a/src/import/generic/memory/lib/utils/freq/mss_freq_scoreboard.H b/src/import/generic/memory/lib/utils/freq/mss_freq_scoreboard.H index 7b9adacdc..1cd31adc5 100644 --- a/src/import/generic/memory/lib/utils/freq/mss_freq_scoreboard.H +++ b/src/import/generic/memory/lib/utils/freq/mss_freq_scoreboard.H @@ -41,6 +41,7 @@ #include <generic/memory/lib/utils/freq/gen_mss_freq_traits.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/pos.H> namespace mss { diff --git a/src/import/generic/memory/lib/utils/index.H b/src/import/generic/memory/lib/utils/index.H index dc60b8c19..fde43f711 100644 --- a/src/import/generic/memory/lib/utils/index.H +++ b/src/import/generic/memory/lib/utils/index.H @@ -38,13 +38,10 @@ #include <fapi2.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> -#include <generic/memory/lib/utils/pos.H> namespace mss { -// TODO Add mc_type template on mss::index API" - /// /// @brief Return an attribute array index from a fapi2 target /// @tparam T the fapi2::TargetType - derived @@ -52,55 +49,28 @@ namespace mss /// @return size_t the attribute array index. /// template< fapi2::TargetType T > -inline size_t index(const fapi2::Target<T>& i_target); - -/// -/// @brief Return an attribute array index from a DIMM target -/// @param[in] i_target a DIMM target representing the DIMM in question -/// @return size_t the attribute array index. -/// -template<> -inline size_t index(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) +inline size_t index(const fapi2::Target<T>& i_target) { - typedef procTraits<proc_type::NIMBUS> TT; - return mss::pos(i_target) % TT::DIMMS_PER_PORT; -} + // Unrolled c_str to avoid a circular include + char l_c_str_storage[fapi2::MAX_ECMD_STRING_LEN] = {}; + fapi2::toString( i_target, l_c_str_storage, fapi2::MAX_ECMD_STRING_LEN ); -/// -///@brief Return an attribute array index from a MCA target -/// @param[in] i_target a MCA target representing the MCA in question -/// @return size_t the attribute array index. -/// -template<> -inline size_t index(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) -{ - typedef procTraits<proc_type::NIMBUS> TT; - return mss::pos(i_target) % TT::PORTS_PER_MCS; -} + uint8_t l_pos = 0; -/// -/// @brief Return an attribute array index from a MCS target -/// @param[in] i_target a MCS target representing the MCS in question -/// @return size_t the attribute array index. -/// -template<> -inline size_t index(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target) -{ - typedef procTraits<proc_type::NIMBUS> TT; - return mss::pos(i_target) % TT::MCS_PER_MC; -} + // Don't use FAPI_TRY as you'll mess up fapi2::current_err which + // lmits where this can be used. + if (FAPI_ATTR_GET(fapi2::ATTR_REL_POS, i_target, l_pos) != fapi2::FAPI2_RC_SUCCESS) + { + goto fapi_try_exit; + } -/// -/// @brief Return an attribute array index from a OCMB target -/// @param[in] i_target a MEM_PORT target representing the OCMB in question -/// @return size_t the attribute array index. -/// -template<> -inline size_t index(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target) -{ - typedef procTraits<proc_type::AXONE> TT; - // We may need to revisit this later if we get an OCMB that has more than one port. - return mss::pos(i_target) % TT::EXP_PORTS_PER_OCMB; + return l_pos; + +fapi_try_exit: + // If we can't get our relative position, we're in other trouble + FAPI_ERR("can't get ATTR_REL_POS for %s", l_c_str_storage); + fapi2::Assert(false); + return 0; } /// diff --git a/src/import/generic/memory/lib/utils/memory_size.H b/src/import/generic/memory/lib/utils/memory_size.H index dc2e73cc7..bf57c3d43 100644 --- a/src/import/generic/memory/lib/utils/memory_size.H +++ b/src/import/generic/memory/lib/utils/memory_size.H @@ -37,20 +37,11 @@ #define _MSS_EFF_MEMORY_SIZE_H_ #include <fapi2.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> #include <generic/memory/lib/utils/find.H> namespace mss { -/// -/// @brief Check if a given DIMM is functional -/// @param[in] i_valid_dimm_bitmap from ATTR_CEN_MSS_EFF_DIMM_FUNCTIONAL_VECTOR -/// @param[in] i_port port index [0:1] -/// @param[in] i_dimm dimm index [0:1] -/// @return true if dimm is functional, false otherwise -/// -bool is_dimm_functional(const uint8_t i_valid_dimm_bitmap, - const uint8_t i_port, - const uint8_t i_dimm); /// /// @brief Return the total memory size behind the target diff --git a/src/import/generic/memory/lib/utils/pos.H b/src/import/generic/memory/lib/utils/pos.H index be82d5385..b04e965f2 100644 --- a/src/import/generic/memory/lib/utils/pos.H +++ b/src/import/generic/memory/lib/utils/pos.H @@ -28,7 +28,7 @@ /// @brief Tools to return target's position from a fapi2 target /// // *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Jacob Harvey <jlharvey@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: HB:FSP @@ -39,8 +39,6 @@ #include <fapi2.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> -// TODO Add mc_type template on mss::pos API" - /// /// @brief Trait classes for the mss::pos functions /// @@ -89,7 +87,7 @@ inline typename TT::pos_type pos(const fapi2::Target<T>& i_target) typename TT::pos_type l_pos = 0; // Don't use FAPI_TRY as you'll mess up fapi2::current_err which - // lmits where this can be used. + // limits where this can be used. if (FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target, l_pos) != fapi2::FAPI2_RC_SUCCESS) { goto fapi_try_exit; @@ -134,130 +132,32 @@ fapi_try_exit: /// @brief Return a DIMM's position from a fapi2 target /// @param[in] i_target a target representing the target in question /// @return The position relative to the chip -/// @warning Nimbus implementation only +/// @warning assumes this attr is already set after pre_eff_config /// -template<> inline posTraits<fapi2::TARGET_TYPE_DIMM>::pos_type pos(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) { - typedef posTraits<fapi2::TARGET_TYPE_DIMM> TT; - typedef procTraits<proc_type::NIMBUS> T; - - // Proc 0 is DIMM 0-15, proc 2 is 64-79 - 64 is the stride between processors - constexpr uint64_t DIMM_STRIDE_PER_PROC = 64; - constexpr uint64_t TOTAL_DIMM = T::MC_PER_MODULE * T::MCS_PER_MC * T::PORTS_PER_MCS * T::DIMMS_PER_PORT; - - TT::pos_type l_pos = 0; - - // Using fapi2 rather than mss::find as this is pretty low level stuff. - const auto l_proc_pos = - mss::template pos(i_target.getParent<fapi2::TARGET_TYPE_MCA>().getParent<fapi2::TARGET_TYPE_PROC_CHIP>()); + posTraits<fapi2::TARGET_TYPE_DIMM>::pos_type l_pos = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_POS_METADATA, i_target, l_pos)); - if (FAPI_ATTR_GET(fapi2::ATTR_FAPI_POS, i_target, l_pos) != fapi2::FAPI2_RC_SUCCESS) - { - goto fapi_try_exit; - } - - // To get the FAPI_POS to the equivilent of ATTR_POS, we need to normalize the fapi_pos value - // to the processor (stride across which ever processor we're on) and then add in the delta - // per processor as ATTR_POS isn't processor relative (delta is the total dimm on a processor) - return ((l_pos - (l_proc_pos * DIMM_STRIDE_PER_PROC)) % TOTAL_DIMM) + (TOTAL_DIMM * l_proc_pos); + return l_pos; fapi_try_exit: // If we can't get our position, we're in other trouble - FAPI_ERR("can't get our fapi position"); + FAPI_ERR("can't get our dimm position"); fapi2::Assert(false); return 0; } /// /// @brief Return a target's relative position from a fapi2 target -/// @tparam T the fapi2::TargetType /// @tparam R the fapi2::TargetType we want the position relative to +/// @tparam T the fapi2::TargetType /// @param[in] i_target a target representing the target in question /// @return The position relative to chiplet R /// template< fapi2::TargetType R, fapi2::TargetType T, typename TT = posTraits<T> > -inline typename TT::pos_type relative_pos(const fapi2::Target<T>& i_target); - -/// -/// @brief Return a MCA's relative position from an MCBIST -/// @param[in] i_target a target representing the target in question -/// @return The position relative to chiplet R -/// -template<> -inline posTraits<fapi2::TARGET_TYPE_MCA>::pos_type -relative_pos<fapi2::TARGET_TYPE_MCBIST>(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) -{ - - typedef procTraits<proc_type::NIMBUS> TT; - return pos(i_target) % TT::PORTS_PER_MCBIST; -} - -/// -/// @brief Return a DIMM's relative position from an MCS -/// @param[in] i_target a target representing the target in question -/// @return The position relative to chiplet R -/// -template<> -inline posTraits<fapi2::TARGET_TYPE_DIMM>::pos_type -relative_pos<fapi2::TARGET_TYPE_MCS>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) -{ - typedef procTraits<proc_type::NIMBUS> TT; - return pos(i_target) % TT::DIMMS_PER_MCS; -} - -/// -/// @brief Return a DIMM's relative position from an MCA -/// @param[in] i_target a target representing the target in question -/// @return The position relative to chiplet R -/// -template<> -inline posTraits<fapi2::TARGET_TYPE_DIMM>::pos_type -relative_pos<fapi2::TARGET_TYPE_MCA>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) -{ - typedef procTraits<proc_type::NIMBUS> TT; - return pos(i_target) % TT::DIMMS_PER_PORT; -} - -/// -/// @brief Return a DIMM's relative position from an MCBIST -/// @param[in] i_target a target representing the target in question -/// @return The position relative to chiplet R -/// -template<> -inline posTraits<fapi2::TARGET_TYPE_DIMM>::pos_type -relative_pos<fapi2::TARGET_TYPE_MCBIST>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) -{ - typedef procTraits<proc_type::NIMBUS> TT; - return pos(i_target) % TT::DIMMS_PER_MCBIST; -} - -/// -/// @brief Return an MCS's relative position from a processor -/// @param[in] i_target a target representing the target in question -/// @return The position relative to chiplet R -/// -template<> -inline posTraits<fapi2::TARGET_TYPE_MCS>::pos_type -relative_pos<fapi2::TARGET_TYPE_PROC_CHIP>(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target) -{ - typedef procTraits<proc_type::NIMBUS> TT; - return pos(i_target) % TT::MCS_PER_PROC; -} - -/// -/// @brief Return an MCA's relative position from an MCS -/// @param[in] i_target a target representing the target in question -/// @return The position relative to chiplet R -/// -template<> -inline posTraits<fapi2::TARGET_TYPE_MCA>::pos_type -relative_pos<fapi2::TARGET_TYPE_MCS>(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) -{ - typedef procTraits<proc_type::NIMBUS> TT; - return pos(i_target) % TT::PORTS_PER_MCS; -} +typename TT::pos_type relative_pos(const fapi2::Target<T>& i_target); /// /// @brief Return a target's fapi position from a fapi2 target @@ -271,7 +171,7 @@ inline uint32_t fapi_pos(const fapi2::Target<T>& i_target) uint32_t l_pos = 0; // Don't use FAPI_TRY as you'll mess up fapi2::current_err which - // lmits where this can be used. + // limits where this can be used. if (FAPI_ATTR_GET(fapi2::ATTR_FAPI_POS, i_target, l_pos) != fapi2::FAPI2_RC_SUCCESS) { goto fapi_try_exit; @@ -286,6 +186,5 @@ fapi_try_exit: return 0; } - } #endif diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index 17fe87ac4..f7f2338fb 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -164,7 +164,10 @@ enum generic_ffdc_codes SET_SI_ODT_WR = 0x1059, SET_SI_ODT_RD = 0x1060, SET_SI_GEARDOWN_MODE = 0x1061, - PRE_DATA_ENGINE_CTOR = 0x1062 + PRE_DATA_ENGINE_CTOR = 0x1062, + SET_DRAM_GEN_METADATA = 0x1063, + SET_DIMM_TYPE_METADATA = 0x1064, + SET_DIMM_POS_METADATA = 0x1065, }; /// @@ -343,16 +346,17 @@ enum class throttle_type }; /// -/// @brief Trait classes for proc_type +/// @brief Trait classes for mc_type +/// @tparam MC the mc_type /// -template< proc_type P > -class procTraits; +template< mc_type MC > +class mcTypeTraits; /// -/// @brief Trait classes for proc_type - NIMBUS specialization +/// @brief Trait classes for mc_type - NIMBUS specialization /// template< > -struct procTraits<proc_type::NIMBUS> +struct mcTypeTraits<mc_type::NIMBUS> { enum { @@ -368,15 +372,19 @@ struct procTraits<proc_type::NIMBUS> }; /// -/// @brief Trait classes for proc_type - AXONE specialization +/// @brief Trait classes for mc_type - EXPLORER specialization /// -/// TODO: Need to add mc_type template< > -struct procTraits<proc_type::AXONE> +struct mcTypeTraits<mc_type::EXPLORER> { enum { - EXP_PORTS_PER_OCMB = 1, + MC_PER_PROC = 2, + MI_PER_MC = 2, + MCC_PER_MI = 2, + OMI_PER_MCC = 2, + OCMB_PER_OMI = 1, + PORTS_PER_OCMB = 1, DIMMS_PER_PORT = 2, }; }; diff --git a/src/import/generic/memory/lib/utils/voltage/gen_mss_volt.H b/src/import/generic/memory/lib/utils/voltage/gen_mss_volt.H index 284995546..1b74f0028 100644 --- a/src/import/generic/memory/lib/utils/voltage/gen_mss_volt.H +++ b/src/import/generic/memory/lib/utils/voltage/gen_mss_volt.H @@ -37,8 +37,9 @@ #define _GEN_MSS_VOLT_H_ #include <fapi2.H> -#include <generic/memory/lib/utils/find.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/voltage/gen_mss_voltage_traits.H> namespace mss diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml index 348764642..48c351b5f 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml @@ -24,59 +24,59 @@ <!-- IBM_PROLOG_END_TAG --> <attributes> - <attribute> - <id>ATTR_MEM_DRAM_CWL</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - CAS Write Latency. - </description> - <mssUnits> nck </mssUnits> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssAccessorName>dram_cwl</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DRAM_CWL</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + CAS Write Latency. + </description> + <mssUnits> nck </mssUnits> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssAccessorName>dram_cwl</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_RDIMM_BUFFER_DELAY</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Delay due to the presence of a buffer, in number of clocks - </description> - <mssUnits> nck </mssUnits> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssAccessorName>dimm_buffer_delay</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_RDIMM_BUFFER_DELAY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Delay due to the presence of a buffer, in number of clocks + </description> + <mssUnits> nck </mssUnits> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssAccessorName>dimm_buffer_delay</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_REORDER_QUEUE_SETTING</id> - <targetType>TARGET_TYPE_OCMB_CHIP</targetType> - <description> - Contains the settings for write/read reorder queue - </description> - <enum>REORDER = 0, FIFO = 1</enum> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssAccessorName>reorder_queue_setting</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_REORDER_QUEUE_SETTING</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + Contains the settings for write/read reorder queue + </description> + <enum>REORDER = 0, FIFO = 1</enum> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssAccessorName>reorder_queue_setting</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_2N_MODE</id> - <targetType>TARGET_TYPE_OCMB_CHIP</targetType> - <description> - Default value for 2N Mode from Signal Integrity. - 0x0 = Invalid Mode, 0x01 = 1N Mode , 0x02 = 2N Mode - If value is set to 0x0 this indicate value was never - initialized correctly. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssAccessorName>mem_2n_mode</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_2N_MODE</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + Default value for 2N Mode from Signal Integrity. + 0x0 = Invalid Mode, 0x01 = 1N Mode , 0x02 = 2N Mode + If value is set to 0x0 this indicate value was never + initialized correctly. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssAccessorName>mem_2n_mode</mssAccessorName> + </attribute> <attribute> <id>ATTR_MEM_VPD_DQ_MAP</id> @@ -338,4 +338,54 @@ <mssAccessorName>dimm_ddr4_f1rc05</mssAccessorName> </attribute> + <attribute> + <id>ATTR_MEM_DIMM_POS_METADATA</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + To get the FAPI_POS to the equivilent of ATTR_POS, we need to normalize the fapi_pos value + to the processor (stride across which ever processor we're on) and then add in the delta + per processor as ATTR_POS isn't processor relative (delta is the total dimm on a processor) + </description> + <initToZero></initToZero> + <valueType>uint32</valueType> + <writeable/> + <mssAccessorName>dimm_pos_metadata</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DRAM_GEN_METADATA</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + DRAM Device Type. + Decodes SPD byte 2. + Created for use by attributes that need this data + earlier than eff_config, such as c_str and the hypervisor. + Not meant for direct HWP use. This is just an abstraction + of any chip specific EFF_DRAM_GEN attribute. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>EMPTY = 0, DDR3 = 1, DDR4 = 2</enum> + <writeable/> + <mssAccessorName>dram_gen_metadata</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_DIMM_TYPE_METADATA</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + Base Module Type. + Decodes SPD Byte 3 (bits 3~0). + Created for use by attributes that need this data + earlier than eff_config, such as c_str and the hypervisor. + Not meant for direct HWP use. This is just an abstraction + of any chip specific EFF_DIMM_TYPE attribute. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum> EMPTY = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3, DDIMM = 4</enum> + <writeable/> + <mssAccessorName>dimm_type_metadata</mssAccessorName> + </attribute> + </attributes> diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml index ae04f2e57..864d871f4 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml @@ -36,769 +36,769 @@ <attributes> - <attribute> - <id>ATTR_MEM_EFF_DRAM_GEN</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - DRAM Device Type. - Decodes SPD byte 2. - Generation of memory: DDR3, DDR4. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>EMPTY = 0, DDR3 = 1, DDR4 = 2</enum> - <writeable/> - <array>2</array> - <mssAccessorName>dram_gen</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DIMM_TYPE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Base Module Type. - Decodes SPD Byte 3 (bits 3~0). - Type of DIMM: RDIMM, UDIMM, LRDIMM as specified by the JEDEC standard. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum> EMPTY = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3, DDIMM = 4</enum> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_type</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_HYBRID_MEMORY_TYPE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Hybrid Media. - Decodes SPD Byte 3 (bits 6~4) - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum> NONE = 0, NVDIMM = 1</enum> - <writeable/> - <array>2</array> - <mssAccessorName>hybrid_memory_type</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_HYBRID</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Hybrid. - Decodes SPD Byte 3 (bit 7) - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum> NOT_HYBRID = 0, IS_HYBRID= 1</enum> - <writeable/> - <array>2</array> - <mssAccessorName>hybrid</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_DENSITY</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - DRAM Density. - Decodes SPD Byte 4 (bits 3~0). - Total SDRAM capacity per die. - For multi-die stacks (DDP, QDP, or 3DS), this represents - the capacity of each DRAM die in the stack. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum> 4G = 4, 8G = 8, 16G = 16 </enum> - <writeable/> - <array>2</array> - <mssUnit>Gb</mssUnit> - <mssAccessorName>dram_density</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_BANK_BITS</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Number of DRAM bank address bits. - Actual number of banks is 2^N, where - N is the number of bank address bits. - Decodes SPD Byte 4 (bits 5~4). - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dram_bank_bits</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_BANK_GROUP_BITS</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Bank Groups Bits. - Decoded SPD Byte 4 (bits 7~6). - Actual number of bank groups is 2^N, - where N is the number of bank address bits. - This value represents the number of bank groups - into which the memory array is divided. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dram_bank_group_bits</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_COLUMN_BITS</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Column Address Bits. - Decoded SPD Byte 5 (bits 2~0). - Actual number of DRAM columns is 2^N, - where N is the number of column address bits - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dram_column_bits</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_ROW_BITS</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Row Address Bits. - Decodes Byte 5 (bits 5~3). - Number of DRAM column address bits. - Actual number of DRAM rows is 2^N, - where N is the number of row address bits - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum> NUM14 = 14, NUM15 = 15, NUM16 = 16, NUM17 = 17, NUM18 = 18</enum> - <writeable/> - <array>2</array> - <mssAccessorName>dram_row_bits</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_PRIM_STACK_TYPE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Primary SDRAM Package Type. - Decodes Byte 6. - This byte defines the primary set of SDRAMs. - Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = 3DS - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum> SDP = 0, DDP_QDP = 1, 3DS = 2</enum> - <writeable/> - <array>2</array> - <mssAccessorName>prim_stack_type</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_PPR</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Post Package Repair. Used in various locations and is evaluated in mss_eff_cnfg. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>NOT_SUPPORTED = 0, SUPPORTED = 1</enum> - <writeable/> - <array>2</array> - <mssAccessorName>dram_ppr</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_SOFT_PPR</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Soft Post Package Repair. Used in various locations and is evaluated in mss_eff_cnfg. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>NOT_SUPPORTED = 0, SUPPORTED = 1</enum> - <writeable/> - <array>2</array> - <mssAccessorName>dram_soft_ppr</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TRCD</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Minimum RAS to CAS Delay Time - in nck (number of clock cyles). - Decodes SPD byte 25 (7~0) and byte 112 (7~0). - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_trcd</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TRP</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - SDRAM Row Precharge Delay Time - in nck (number of clock cycles). - Decodes SPD byte 26 (bits 7~0) and byte 121 (bits 7~0). - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_trp</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TRAS</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Minimum Active to Precharge Delay Time - in nck (number of clock cycles). - Decodes SPD byte 27 (bits 3~0) and byte 28 (7~0). - Each memory channel will have a value. - creator: mss_eff_cnfg_timing - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_tras</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TRC</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Minimum Active to Active/Refresh Delay - in nck (number of clock cyles). - Decodes SPD byte 27 (bits 7~4), byte 29 (bits 7~0), and byte 120. - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_trc</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TRFC</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - DDR4 Spec defined as Refresh Cycle Time (tRFC). - SPD Spec refers it to the Minimum Refresh Recovery Delay Time. - In nck (number of clock cyles). - Decodes SPD byte 31 (bits 15~8) and byte 30 (bits 7~0) for tRFC1. - Decodes SPD byte 33 (bits 15~8) and byte 32 (bits 7~0) for tRFC2. - Decodes SPD byte 35 (bits 15~8) and byte 34 (bits 7~0) for tRFC4. - Selected tRFC value depends on MRW attribute that selects refresh mode. - For 3DS, The tRFC time to the same logical rank is defined as tRFC_slr and is - specificed as the value as for a monolithic DDR4 SDRAM of equivalent density. - </description> - <initToZero></initToZero> - <valueType>uint16</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_trfc</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TFAW</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Minimum Four Activate Window Delay Time - in nck (number of clock cycles). - Decodes SPD byte 36 (bits 3~0) and byte 37 (bits 7~0). - For 3DS, tFAW time to the same logical rank is defined as - tFAW_slr_x4 or tFAW_slr_x8 (for x4 and x8 devices only) and - specificed as the value as for a monolithic DDR4 SDRAM - equivalent density. - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_tfaw</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TRRD_S</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Minimum Activate to Activate Delay Time, different bank group - in nck (number of clock cycles). - Decodes SPD byte 38 (bits 7~0). - For 3DS, The tRRD_S time to a different bank group in the - same logical rank is defined as tRRD_slr and is - specificed as the value as for a monolithic - DDR4 SDRAM of equivalent density. - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_trrd_s</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TRRD_L</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Minimum Activate to Activate Delay Time, same bank group - in nck (number of clock cycles). - Decodes SPD byte 39 (bits 7~0). - For 3DS, The tRRD_L time to the same bank group in the - same logical rank is defined as tRRD_L_slr and is - specificed as the value as for a monolithic - DDR4 SDRAM of equivalent density. - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_trrd_l</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TRRD_DLR</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Minimum Activate to Activate Delay Time (different logical ranks) - in nck (number of clock cycles). - For 3DS, The tRRD_S time to a different logical rank is defined as tRRD_dlr. - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_trrd_dlr</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TCCD_L</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Minimum CAS to CAS Delay Time, same bank group - in nck (number of clock cycles). - Decodes SPD byte 40 (bits 7~0) and byte 117 (bits 7~0). - This is for DDR4 MRS6. - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>4NCK = 4, 5NCK = 5, 6NCK = 6, 7NCK = 7, 8NCK = 8</enum> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_tccd_l</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TWR</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Minimum Write Recovery Time. - Decodes SPD byte 41 (bits 3~0) and byte 42 (bits 7~0). - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_twr</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TWTR_S</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Minimum Write to Read Time, different bank group - in nck (number of clock cycles). - Decodes SPD byte 43 (3~0) and byte 44 (bits 7~0). - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_twtr_s</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TWTR_L</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Minimum Write to Read Time, same bank group - in nck (number of clock cycles). - Decodes byte 43 (7~4) and byte 45 (bits 7~0). - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_twtr_l</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TMAW</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Maximum Activate Window - in nck (number of clock cycles). - Decodes SPD byte 7 (bits 5~4). - Depends on tREFI multiplier. - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint16</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_tmaw</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_WIDTH</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - SDRAM Device Width - Decodes SPD Byte 12 (bits 2~0). - Options: X4 (4 bits), X8 (8 bits), X16 (16 bits), X32 (32 bits). - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>X4 = 4, X8 = 8, X16 = 16, X32 = 32</enum> - <mssUnit>bits</mssUnit> - <writeable/> - <array>2</array> - <mssAccessorName>dram_width</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_NUM_RANKS_PER_DIMM</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Total number of ranks in each DIMM. - For monolithic and multi-load stack modules (SDP/DDP) this is the same as - the number of package ranks per DIMM (SPD Byte 12 bits 5~3). - - For single load stack (3DS) modules this value represents the number - of logical ranks per DIMM. - Logical rank refers the individually addressable die in a 3DS stack - and has no meaning for monolithic or multi-load stacked SDRAMs. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum> - 1R = 1, 2R = 2, 4R = 4, 8R = 8, 16R = 16 - </enum> - <writeable/> - <array>2</array> - <mssAccessorName>num_ranks_per_dimm</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_REGISTER_TYPE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Register Type - Decodes SPD Byte 131 - </description> - <enum>RCD01 = 0x0, RCD02 = 0x1</enum> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>register_type</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_MFG_ID</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - DRAM Manufacturer ID Code - Decodes SPD Byte 350 and 351 - </description> - <enum>MICRON = 0x802C, SAMSUNG = 0x80CE, HYNIX = 0x80AD </enum> - <initToZero></initToZero> - <valueType>uint16</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dram_mfg_id</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_RCD_MFG_ID</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Register Manufacturer ID Code - Decodes SPD Byte 133 and 134 - </description> - <enum>INPHI = 0xB304, MONTAGE = 0x3286, IDT = 0xB380 </enum> - <initToZero></initToZero> - <valueType>uint16</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>rcd_mfg_id</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_REGISTER_REV</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Register Revision Number - Decodes SPD Byte 135 - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>register_rev</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_PACKAGE_RANK_MAP</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM][DQ_NIBBLES] - Package Rank Map - Decodes SPD Byte 60 - 77 (Bits 7~6) - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2 20</array> - <mssAccessorName>package_rank_map</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_NIBBLE_MAP</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM][DQ_NIBBLES] - Nibble Map - Decodes SPD Byte 60 - 77 (Bits 5~0) for DDR4 - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2 20</array> - <mssAccessorName>nibble_map</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DIMM_SIZE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - DIMM Size, in GB Used in various locations - </description> - <initToZero></initToZero> - <valueType>uint32</valueType> - <enum> - 4GB = 4, - 8GB = 8, - 16GB = 16, - 32GB = 32, - 64GB = 64, - 128GB = 128, - 256GB = 256, - 512GB = 512 - </enum> - <writeable/> - <array>2</array> - <mssUnits>GB</mssUnits> - <mssAccessorName>dimm_size</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DIMM_SPARE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. - Array indexes are [DIMM][RANK] - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum> - <writeable/> - <array> 2 4</array> - <mssAccessorName>dimm_spare</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_CL</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - CAS Latency. - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits>nck</mssUnits> - <mssAccessorName>dram_cl</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Specifies the number of master ranks per DIMM. - Represents the number of physical ranks on a DIMM. - From SPD spec JEDEC Standard No. 21-C: Page 4.1.2.L-4. - Byte 12 (Bits 5~3) Number of package ranks per DIMM. - Package ranks per DIMM refers to the collections of devices - on the module sharing common chip select signals. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum> - 1R = 1, 2R = 2, 4R = 4, 8R = 8 - </enum> - <writeable/> - <array>2</array> - <mssAccessorName>num_master_ranks_per_dimm</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DIMM_RANKS_CONFIGED</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Bit wise representation of master ranks in each DIMM that are used for reads and writes. - Used by PRD. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array> 2 </array> - <mssAccessorName>dimm_ranks_configed</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TREFI</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Average Refresh Interval (tREFI) - in nck (number of clock cycles). - This depends on MRW attribute that selects fine refresh mode (x1, x2, x4). - From DDR4 spec (79-4A). - - For 3DS, the tREFI time to the same logical rank is defined as - tRFC_slr1, tRFC_slr2, or tRFC_slr4. - </description> - <initToZero></initToZero> - <valueType>uint16</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_trefi</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TRTP</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Internal Read to Precharge Delay. - From the DDR4 spec (79-4A). - Each memory channel will have a value. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits>nck</mssUnits> - <mssAccessorName>dram_trtp</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_DRAM_TRFC_DLR</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Minimum Refresh Recovery Delay Time (different logical ranks) - in nck (number of clock cyles). - Selected tRFC value (tRFC_dlr1, tRFC_dlr2, or tRFC_dlr4) - depends on MRW attribute that selects fine refresh mode (x1, x2, x4). - For 3DS, The tRFC time to different logical ranks are defined as tRFC_dlr - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits> nck </mssUnits> - <mssAccessorName>dram_trfc_dlr</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_FREQ</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Frequency of this memory channel in MT/s (Mega Transfers per second) - </description> - <initToZero></initToZero> - <valueType>uint64</valueType> - <writeable/> - <mssUnits> MT/s </mssUnits> - <mssAccessorName>freq</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_VOLT_VDDR</id> - <targetType>TARGET_TYPE_OCMB_CHIP</targetType> - <description> - DRAM Voltage, each voltage rail would need to have a value. - </description> - <initToZero></initToZero> - <valueType>uint32</valueType> - <writeable/> - <mssUnits> mV </mssUnits> - <mssAccessorName>volt_vddr</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_VOLT_VPP</id> - <targetType>TARGET_TYPE_OCMB_CHIP</targetType> - <description> - DRAM VPP Voltage, each voltage rail would need to have a value. - </description> - <initToZero></initToZero> - <valueType>uint32</valueType> - <writeable/> - <mssUnits> mV </mssUnits> - <mssAccessorName>volt_vpp</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_EFF_DRAM_GEN</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + DRAM Device Type. + Decodes SPD byte 2. + Generation of memory: DDR3, DDR4. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>EMPTY = 0, DDR3 = 1, DDR4 = 2</enum> + <writeable/> + <array>2</array> + <mssAccessorName>dram_gen</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DIMM_TYPE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Base Module Type. + Decodes SPD Byte 3 (bits 3~0). + Type of DIMM: RDIMM, UDIMM, LRDIMM as specified by the JEDEC standard. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum> EMPTY = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3, DDIMM = 4</enum> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_type</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_HYBRID_MEMORY_TYPE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Hybrid Media. + Decodes SPD Byte 3 (bits 6~4) + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum> NONE = 0, NVDIMM = 1</enum> + <writeable/> + <array>2</array> + <mssAccessorName>hybrid_memory_type</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_HYBRID</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Hybrid. + Decodes SPD Byte 3 (bit 7) + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum> NOT_HYBRID = 0, IS_HYBRID= 1</enum> + <writeable/> + <array>2</array> + <mssAccessorName>hybrid</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_DENSITY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + DRAM Density. + Decodes SPD Byte 4 (bits 3~0). + Total SDRAM capacity per die. + For multi-die stacks (DDP, QDP, or 3DS), this represents + the capacity of each DRAM die in the stack. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum> 4G = 4, 8G = 8, 16G = 16 </enum> + <writeable/> + <array>2</array> + <mssUnit>Gb</mssUnit> + <mssAccessorName>dram_density</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_BANK_BITS</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Number of DRAM bank address bits. + Actual number of banks is 2^N, where + N is the number of bank address bits. + Decodes SPD Byte 4 (bits 5~4). + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dram_bank_bits</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_BANK_GROUP_BITS</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Bank Groups Bits. + Decoded SPD Byte 4 (bits 7~6). + Actual number of bank groups is 2^N, + where N is the number of bank address bits. + This value represents the number of bank groups + into which the memory array is divided. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dram_bank_group_bits</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_COLUMN_BITS</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Column Address Bits. + Decoded SPD Byte 5 (bits 2~0). + Actual number of DRAM columns is 2^N, + where N is the number of column address bits + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dram_column_bits</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_ROW_BITS</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Row Address Bits. + Decodes Byte 5 (bits 5~3). + Number of DRAM column address bits. + Actual number of DRAM rows is 2^N, + where N is the number of row address bits + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum> NUM14 = 14, NUM15 = 15, NUM16 = 16, NUM17 = 17, NUM18 = 18</enum> + <writeable/> + <array>2</array> + <mssAccessorName>dram_row_bits</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PRIM_STACK_TYPE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Primary SDRAM Package Type. + Decodes Byte 6. + This byte defines the primary set of SDRAMs. + Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = 3DS + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum> SDP = 0, DDP_QDP = 1, 3DS = 2</enum> + <writeable/> + <array>2</array> + <mssAccessorName>prim_stack_type</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_PPR</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Post Package Repair. Used in various locations and is evaluated in mss_eff_cnfg. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>NOT_SUPPORTED = 0, SUPPORTED = 1</enum> + <writeable/> + <array>2</array> + <mssAccessorName>dram_ppr</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_SOFT_PPR</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Soft Post Package Repair. Used in various locations and is evaluated in mss_eff_cnfg. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>NOT_SUPPORTED = 0, SUPPORTED = 1</enum> + <writeable/> + <array>2</array> + <mssAccessorName>dram_soft_ppr</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TRCD</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Minimum RAS to CAS Delay Time + in nck (number of clock cyles). + Decodes SPD byte 25 (7~0) and byte 112 (7~0). + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_trcd</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TRP</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + SDRAM Row Precharge Delay Time + in nck (number of clock cycles). + Decodes SPD byte 26 (bits 7~0) and byte 121 (bits 7~0). + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_trp</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TRAS</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Minimum Active to Precharge Delay Time + in nck (number of clock cycles). + Decodes SPD byte 27 (bits 3~0) and byte 28 (7~0). + Each memory channel will have a value. + creator: mss_eff_cnfg_timing + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_tras</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TRC</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Minimum Active to Active/Refresh Delay + in nck (number of clock cyles). + Decodes SPD byte 27 (bits 7~4), byte 29 (bits 7~0), and byte 120. + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_trc</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TRFC</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + DDR4 Spec defined as Refresh Cycle Time (tRFC). + SPD Spec refers it to the Minimum Refresh Recovery Delay Time. + In nck (number of clock cyles). + Decodes SPD byte 31 (bits 15~8) and byte 30 (bits 7~0) for tRFC1. + Decodes SPD byte 33 (bits 15~8) and byte 32 (bits 7~0) for tRFC2. + Decodes SPD byte 35 (bits 15~8) and byte 34 (bits 7~0) for tRFC4. + Selected tRFC value depends on MRW attribute that selects refresh mode. + For 3DS, The tRFC time to the same logical rank is defined as tRFC_slr and is + specificed as the value as for a monolithic DDR4 SDRAM of equivalent density. + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_trfc</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TFAW</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Minimum Four Activate Window Delay Time + in nck (number of clock cycles). + Decodes SPD byte 36 (bits 3~0) and byte 37 (bits 7~0). + For 3DS, tFAW time to the same logical rank is defined as + tFAW_slr_x4 or tFAW_slr_x8 (for x4 and x8 devices only) and + specificed as the value as for a monolithic DDR4 SDRAM + equivalent density. + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_tfaw</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TRRD_S</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Minimum Activate to Activate Delay Time, different bank group + in nck (number of clock cycles). + Decodes SPD byte 38 (bits 7~0). + For 3DS, The tRRD_S time to a different bank group in the + same logical rank is defined as tRRD_slr and is + specificed as the value as for a monolithic + DDR4 SDRAM of equivalent density. + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_trrd_s</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TRRD_L</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Minimum Activate to Activate Delay Time, same bank group + in nck (number of clock cycles). + Decodes SPD byte 39 (bits 7~0). + For 3DS, The tRRD_L time to the same bank group in the + same logical rank is defined as tRRD_L_slr and is + specificed as the value as for a monolithic + DDR4 SDRAM of equivalent density. + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_trrd_l</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TRRD_DLR</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Minimum Activate to Activate Delay Time (different logical ranks) + in nck (number of clock cycles). + For 3DS, The tRRD_S time to a different logical rank is defined as tRRD_dlr. + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_trrd_dlr</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TCCD_L</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Minimum CAS to CAS Delay Time, same bank group + in nck (number of clock cycles). + Decodes SPD byte 40 (bits 7~0) and byte 117 (bits 7~0). + This is for DDR4 MRS6. + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>4NCK = 4, 5NCK = 5, 6NCK = 6, 7NCK = 7, 8NCK = 8</enum> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_tccd_l</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TWR</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Minimum Write Recovery Time. + Decodes SPD byte 41 (bits 3~0) and byte 42 (bits 7~0). + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_twr</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TWTR_S</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Minimum Write to Read Time, different bank group + in nck (number of clock cycles). + Decodes SPD byte 43 (3~0) and byte 44 (bits 7~0). + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_twtr_s</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TWTR_L</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Minimum Write to Read Time, same bank group + in nck (number of clock cycles). + Decodes byte 43 (7~4) and byte 45 (bits 7~0). + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_twtr_l</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TMAW</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Maximum Activate Window + in nck (number of clock cycles). + Decodes SPD byte 7 (bits 5~4). + Depends on tREFI multiplier. + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_tmaw</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_WIDTH</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + SDRAM Device Width + Decodes SPD Byte 12 (bits 2~0). + Options: X4 (4 bits), X8 (8 bits), X16 (16 bits), X32 (32 bits). + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>X4 = 4, X8 = 8, X16 = 16, X32 = 32</enum> + <mssUnit>bits</mssUnit> + <writeable/> + <array>2</array> + <mssAccessorName>dram_width</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_NUM_RANKS_PER_DIMM</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Total number of ranks in each DIMM. + For monolithic and multi-load stack modules (SDP/DDP) this is the same as + the number of package ranks per DIMM (SPD Byte 12 bits 5~3). + + For single load stack (3DS) modules this value represents the number + of logical ranks per DIMM. + Logical rank refers the individually addressable die in a 3DS stack + and has no meaning for monolithic or multi-load stacked SDRAMs. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum> + 1R = 1, 2R = 2, 4R = 4, 8R = 8, 16R = 16 + </enum> + <writeable/> + <array>2</array> + <mssAccessorName>num_ranks_per_dimm</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_REGISTER_TYPE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Register Type + Decodes SPD Byte 131 + </description> + <enum>RCD01 = 0x0, RCD02 = 0x1</enum> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>register_type</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_MFG_ID</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + DRAM Manufacturer ID Code + Decodes SPD Byte 350 and 351 + </description> + <enum>MICRON = 0x802C, SAMSUNG = 0x80CE, HYNIX = 0x80AD </enum> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dram_mfg_id</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_RCD_MFG_ID</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Register Manufacturer ID Code + Decodes SPD Byte 133 and 134 + </description> + <enum>INPHI = 0xB304, MONTAGE = 0x3286, IDT = 0xB380 </enum> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>rcd_mfg_id</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_REGISTER_REV</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Register Revision Number + Decodes SPD Byte 135 + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>register_rev</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PACKAGE_RANK_MAP</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM][DQ_NIBBLES] + Package Rank Map + Decodes SPD Byte 60 - 77 (Bits 7~6) + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2 20</array> + <mssAccessorName>package_rank_map</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_NIBBLE_MAP</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM][DQ_NIBBLES] + Nibble Map + Decodes SPD Byte 60 - 77 (Bits 5~0) for DDR4 + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2 20</array> + <mssAccessorName>nibble_map</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DIMM_SIZE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + DIMM Size, in GB Used in various locations + </description> + <initToZero></initToZero> + <valueType>uint32</valueType> + <enum> + 4GB = 4, + 8GB = 8, + 16GB = 16, + 32GB = 32, + 64GB = 64, + 128GB = 128, + 256GB = 256, + 512GB = 512 + </enum> + <writeable/> + <array>2</array> + <mssUnits>GB</mssUnits> + <mssAccessorName>dimm_size</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DIMM_SPARE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. + Array indexes are [DIMM][RANK] + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3</enum> + <writeable/> + <array> 2 4</array> + <mssAccessorName>dimm_spare</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_CL</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + CAS Latency. + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits>nck</mssUnits> + <mssAccessorName>dram_cl</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Specifies the number of master ranks per DIMM. + Represents the number of physical ranks on a DIMM. + From SPD spec JEDEC Standard No. 21-C: Page 4.1.2.L-4. + Byte 12 (Bits 5~3) Number of package ranks per DIMM. + Package ranks per DIMM refers to the collections of devices + on the module sharing common chip select signals. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum> + 1R = 1, 2R = 2, 4R = 4, 8R = 8 + </enum> + <writeable/> + <array>2</array> + <mssAccessorName>num_master_ranks_per_dimm</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DIMM_RANKS_CONFIGED</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Bit wise representation of master ranks in each DIMM that are used for reads and writes. + Used by PRD. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array> 2 </array> + <mssAccessorName>dimm_ranks_configed</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TREFI</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Average Refresh Interval (tREFI) + in nck (number of clock cycles). + This depends on MRW attribute that selects fine refresh mode (x1, x2, x4). + From DDR4 spec (79-4A). + + For 3DS, the tREFI time to the same logical rank is defined as + tRFC_slr1, tRFC_slr2, or tRFC_slr4. + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_trefi</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TRTP</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Internal Read to Precharge Delay. + From the DDR4 spec (79-4A). + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits>nck</mssUnits> + <mssAccessorName>dram_trtp</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DRAM_TRFC_DLR</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Minimum Refresh Recovery Delay Time (different logical ranks) + in nck (number of clock cyles). + Selected tRFC value (tRFC_dlr1, tRFC_dlr2, or tRFC_dlr4) + depends on MRW attribute that selects fine refresh mode (x1, x2, x4). + For 3DS, The tRFC time to different logical ranks are defined as tRFC_dlr + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits> nck </mssUnits> + <mssAccessorName>dram_trfc_dlr</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_FREQ</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Frequency of this memory channel in MT/s (Mega Transfers per second) + </description> + <initToZero></initToZero> + <valueType>uint64</valueType> + <writeable/> + <mssUnits> MT/s </mssUnits> + <mssAccessorName>freq</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_VOLT_VDDR</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + DRAM Voltage, each voltage rail would need to have a value. + </description> + <initToZero></initToZero> + <valueType>uint32</valueType> + <writeable/> + <mssUnits> mV </mssUnits> + <mssAccessorName>volt_vddr</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_VOLT_VPP</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + DRAM VPP Voltage, each voltage rail would need to have a value. + </description> + <initToZero></initToZero> + <valueType>uint32</valueType> + <writeable/> + <mssUnits> mV </mssUnits> + <mssAccessorName>volt_vpp</mssAccessorName> + </attribute> </attributes> |
