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author | Andre A. Marin <aamarin@us.ibm.com> | 2019-03-05 22:53:02 -0600 |
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committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-03-16 14:51:17 -0500 |
commit | b5e9f70eb916d2dcda27751588ce24199338950f (patch) | |
tree | 9364aee37ca9cc7e337395f46b803532384aa19b /src/import/chips | |
parent | bcecb8a2a15af6d4147a740d3fc4d4224b38fd93 (diff) | |
download | talos-hostboot-b5e9f70eb916d2dcda27751588ce24199338950f.tar.gz talos-hostboot-b5e9f70eb916d2dcda27751588ce24199338950f.zip |
Update phy_pharams structure, tests, and exp attrs
Change-Id: I6999ba3e4b013dd10867a9b006e8cf7e5c1c5bbf
Original-Change-Id: Ie84463e9497bf53d8cd13b14526be93d9de95506
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72070
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/73470
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips')
-rw-r--r-- | src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml | 105 | ||||
-rw-r--r-- | src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_eff_attributes.xml | 144 |
2 files changed, 192 insertions, 57 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml index 927bdcf83..8ff5a9df3 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml @@ -120,42 +120,17 @@ <mssAccessorName>mvpd_fwms</mssAccessorName> </attribute> + <!-- user_input_msdg attribute overrides start --> <attribute> - <id>ATTR_MEM_EXP_FIRMWARE_EMULATION_MODE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Enable Special mode for Emulation Support - </description> - <valueType>uint8</valueType> - <initToZero></initToZero> - <enum>NORMAL = 0, EMULATION = 1</enum> - <writeable/> - <mssAccessorName>exp_firmware_emulation_mode</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EXP_CHIP_SELECT</id> + <id>ATTR_MEM_EXP_CS_PRESENT</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> Indicate presence of DRAM at each Chip Select for PHY </description> - <valueType>uint8</valueType> <initToZero></initToZero> + <valueType>uint16</valueType> <writeable/> - <mssAccessorName>exp_chip_select</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EXP_PHY_EQUALIZATION</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Phy Equalization mode enable - </description> - <valueType>uint8</valueType> - <initToZero></initToZero> - <enum>DISABLE = 0, ENABLE = 1</enum> - <writeable/> - <mssAccessorName>exp_phy_equalization</mssAccessorName> + <mssAccessorName>exp_cs_present</mssAccessorName> </attribute> <attribute> @@ -183,70 +158,71 @@ </attribute> <attribute> - <id>ATTR_MEM_EXP_ODT_MAP_CS_WR</id> + <id>ATTR_MEM_EXP_RCD_DIC</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Desired ODT Value to write to the ranks + CA and CS signal Driver Characteristics from F0RC03, F0RC04, F0RC05 </description> - <valueType>uint8</valueType> + <valueType>uint16</valueType> <initToZero></initToZero> <writeable/> - <mssAccessorName>exp_odt_map_cs_wr</mssAccessorName> + <mssAccessorName>exp_rcd_dic</mssAccessorName> </attribute> <attribute> - <id>ATTR_MEM_EXP_ODT_MAP_CS_RD</id> + <id>ATTR_MEM_EXP_RCD_VOLTAGE_CTRL</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Desired ODT Value when reading from the ranks + RCD operating voltage VDD and VrefCA control from F0RC0B and F0RC1x </description> - <valueType>uint8</valueType> + <valueType>uint16</valueType> <initToZero></initToZero> <writeable/> - <mssAccessorName>exp_odt_map_cs_rd</mssAccessorName> + <mssAccessorName>exp_rcd_voltage_ctrl</mssAccessorName> </attribute> <attribute> - <id>ATTR_MEM_EXP_RCD_DIC</id> + <id>ATTR_MEM_EXP_DRAM_ADDRESS_MIRRORING</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - CA and CS signal Driver Characteristics from F0RC03, F0RC04, F0RC05 + Ranks that have address mirroring. + This data is derived from SPD or VPD. + Note: This is a bit-wise map and muliple ranks can be mirrored. </description> - <valueType>uint8</valueType> <initToZero></initToZero> + <valueType>uint8</valueType> + <array>2</array> <writeable/> - <mssAccessorName>exp_rcd_dic</mssAccessorName> + <mssAccessorName>exp_dram_address_mirroring</mssAccessorName> </attribute> <attribute> - <id>ATTR_MEM_EXP_RCD_VOLTAGE_CTRL</id> + <id>ATTR_MEM_EXP_RCD_SLEW_RATE</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - RCD operating voltage VDD and VrefCA control from F0RC0B and F0RC1x + RCD slew rate control from F1RC02,F1RC03,F1RC04,F1RC05 </description> - <valueType>uint8</valueType> <initToZero></initToZero> + <valueType>uint16</valueType> <writeable/> - <mssAccessorName>exp_rcd_voltage_ctrl</mssAccessorName> + <mssAccessorName>exp_rcd_slew_rate</mssAccessorName> </attribute> <attribute> - <id>ATTR_MEM_EXP_DRAM_ADDRESS_MIRRORING</id> + <id>ATTR_MEM_EXP_3DS_HEIGHT</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Ranks that have address mirroring. - This data is derived from SPD or VPD. - Note: This is a bit-wise map and muliple ranks can be mirrored. + Explorer setting for 3DS stack </description> <initToZero></initToZero> - <valueType>uint8</valueType> - <array>2</array> + <valueType>uint16</valueType> + <enum>PLANAR = 0, H2 = 2, H4 = 4, H8 = 8</enum> <writeable/> - <mssAccessorName>exp_dram_address_mirroring</mssAccessorName> + <mssAccessorName>exp_3ds_height</mssAccessorName> </attribute> <attribute> - <id>ATTR_MEM_EXP_SPD_CL</id> + <id>ATTR_MEM_EXP_SPD_CL_SUPPORTED</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> Cas Latency Supported by DRAM @@ -254,19 +230,34 @@ <initToZero></initToZero> <valueType>uint32</valueType> <writeable/> - <mssAccessorName>exp_spd_cl</mssAccessorName> + <mssAccessorName>exp_spd_cl_supported</mssAccessorName> </attribute> <attribute> - <id>ATTR_MEM_EXP_RCD_SLEW_RATE</id> + <id>ATTR_MEM_EXP_SPD_TAA_MIN</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - RCD slew rate control from F1RC02,F1RC03,F1RC04,F1RC05 + Minimum Cas Latency Time (tAAmin) in Picosecond (Byte 24) </description> <initToZero></initToZero> <valueType>uint16</valueType> <writeable/> - <mssAccessorName>exp_rcd_slew_rate</mssAccessorName> + <mssUnits>ps</mssUnits> + <mssAccessorName>exp_spd_taa_min</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_FIRMWARE_EMULATION_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Enable Special mode for Emulation Support + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <mssUnits>bool</mssUnits> + <enum>NORMAL = 0, EMULATION = 1</enum> + <writeable/> + <mssAccessorName>exp_firmware_emulation_mode</mssAccessorName> </attribute> </attributes> diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_eff_attributes.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_eff_attributes.xml new file mode 100644 index 000000000..76b295dd9 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_eff_attributes.xml @@ -0,0 +1,144 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_eff_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2019 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<attributes> + <attribute> + <id>ATTR_MEM_EFF_PSTATES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + This byte defines the allowed number of + P-States for the DDR4 Differential Memory Buffer. + P-States can be thought of as an available performance profile. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <array>2</array> + <writeable/> + <mssAccessorName>pstates</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_BYTE_ENABLES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + These bits are used to activate or deactivate bytes in the + DDR interface of the differential memory + buffer chip. + Right aligned data. + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <array>2</array> + <writeable/> + <mssAccessorName>byte_enables</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_NIBBLE_ENABLES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + These bits are used to select the active nibbles or DQS on the DDR interface. + Right aligned data. + </description> + <initToZero></initToZero> + <valueType>uint32</valueType> + <array>2</array> + <writeable/> + <mssAccessorName>nibble_enables</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_FOUR_RANK_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + A-Side CA bus drives rank 0/1 + and B-Side CA bus drives rank 2/3, DQ/DQS are + shared across the ranks + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <array>2</array> + <mssUnits>bool</mssUnits> + <mssAccessorName>four_rank_mode</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_MRAM_SUPPORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + MRAM Support + Support timing parameters of Everspin DDR4 MRAM + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <array>2</array> + <mssUnits>bool</mssUnits> + <mssAccessorName>mram_support</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DDP_COMPATIBILITY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + DDP Compatibility + Support 1 rank 3DS Device in DDP board routing. CKE[1], CSN[1], ODT[1] of + PHY are connected to C[0], C[1], C[2] of DRAM + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <array>2</array> + <mssUnits>bool</mssUnits> + <mssAccessorName>ddp_compatibility</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_TSV_8H_SUPPORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + TSV 8H Support + Support 8H 3DS routing in board routing when parity check is disabled + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <array>2</array> + <mssUnits>bool</mssUnits> + <mssAccessorName>tsv_8h_support</mssAccessorName> + </attribute> + +</attributes> |