diff options
5 files changed, 551 insertions, 438 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml index 927bdcf83..8ff5a9df3 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml @@ -120,42 +120,17 @@ <mssAccessorName>mvpd_fwms</mssAccessorName> </attribute> + <!-- user_input_msdg attribute overrides start --> <attribute> - <id>ATTR_MEM_EXP_FIRMWARE_EMULATION_MODE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Enable Special mode for Emulation Support - </description> - <valueType>uint8</valueType> - <initToZero></initToZero> - <enum>NORMAL = 0, EMULATION = 1</enum> - <writeable/> - <mssAccessorName>exp_firmware_emulation_mode</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EXP_CHIP_SELECT</id> + <id>ATTR_MEM_EXP_CS_PRESENT</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> Indicate presence of DRAM at each Chip Select for PHY </description> - <valueType>uint8</valueType> <initToZero></initToZero> + <valueType>uint16</valueType> <writeable/> - <mssAccessorName>exp_chip_select</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EXP_PHY_EQUALIZATION</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Phy Equalization mode enable - </description> - <valueType>uint8</valueType> - <initToZero></initToZero> - <enum>DISABLE = 0, ENABLE = 1</enum> - <writeable/> - <mssAccessorName>exp_phy_equalization</mssAccessorName> + <mssAccessorName>exp_cs_present</mssAccessorName> </attribute> <attribute> @@ -183,70 +158,71 @@ </attribute> <attribute> - <id>ATTR_MEM_EXP_ODT_MAP_CS_WR</id> + <id>ATTR_MEM_EXP_RCD_DIC</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Desired ODT Value to write to the ranks + CA and CS signal Driver Characteristics from F0RC03, F0RC04, F0RC05 </description> - <valueType>uint8</valueType> + <valueType>uint16</valueType> <initToZero></initToZero> <writeable/> - <mssAccessorName>exp_odt_map_cs_wr</mssAccessorName> + <mssAccessorName>exp_rcd_dic</mssAccessorName> </attribute> <attribute> - <id>ATTR_MEM_EXP_ODT_MAP_CS_RD</id> + <id>ATTR_MEM_EXP_RCD_VOLTAGE_CTRL</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Desired ODT Value when reading from the ranks + RCD operating voltage VDD and VrefCA control from F0RC0B and F0RC1x </description> - <valueType>uint8</valueType> + <valueType>uint16</valueType> <initToZero></initToZero> <writeable/> - <mssAccessorName>exp_odt_map_cs_rd</mssAccessorName> + <mssAccessorName>exp_rcd_voltage_ctrl</mssAccessorName> </attribute> <attribute> - <id>ATTR_MEM_EXP_RCD_DIC</id> + <id>ATTR_MEM_EXP_DRAM_ADDRESS_MIRRORING</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - CA and CS signal Driver Characteristics from F0RC03, F0RC04, F0RC05 + Ranks that have address mirroring. + This data is derived from SPD or VPD. + Note: This is a bit-wise map and muliple ranks can be mirrored. </description> - <valueType>uint8</valueType> <initToZero></initToZero> + <valueType>uint8</valueType> + <array>2</array> <writeable/> - <mssAccessorName>exp_rcd_dic</mssAccessorName> + <mssAccessorName>exp_dram_address_mirroring</mssAccessorName> </attribute> <attribute> - <id>ATTR_MEM_EXP_RCD_VOLTAGE_CTRL</id> + <id>ATTR_MEM_EXP_RCD_SLEW_RATE</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - RCD operating voltage VDD and VrefCA control from F0RC0B and F0RC1x + RCD slew rate control from F1RC02,F1RC03,F1RC04,F1RC05 </description> - <valueType>uint8</valueType> <initToZero></initToZero> + <valueType>uint16</valueType> <writeable/> - <mssAccessorName>exp_rcd_voltage_ctrl</mssAccessorName> + <mssAccessorName>exp_rcd_slew_rate</mssAccessorName> </attribute> <attribute> - <id>ATTR_MEM_EXP_DRAM_ADDRESS_MIRRORING</id> + <id>ATTR_MEM_EXP_3DS_HEIGHT</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Ranks that have address mirroring. - This data is derived from SPD or VPD. - Note: This is a bit-wise map and muliple ranks can be mirrored. + Explorer setting for 3DS stack </description> <initToZero></initToZero> - <valueType>uint8</valueType> - <array>2</array> + <valueType>uint16</valueType> + <enum>PLANAR = 0, H2 = 2, H4 = 4, H8 = 8</enum> <writeable/> - <mssAccessorName>exp_dram_address_mirroring</mssAccessorName> + <mssAccessorName>exp_3ds_height</mssAccessorName> </attribute> <attribute> - <id>ATTR_MEM_EXP_SPD_CL</id> + <id>ATTR_MEM_EXP_SPD_CL_SUPPORTED</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> Cas Latency Supported by DRAM @@ -254,19 +230,34 @@ <initToZero></initToZero> <valueType>uint32</valueType> <writeable/> - <mssAccessorName>exp_spd_cl</mssAccessorName> + <mssAccessorName>exp_spd_cl_supported</mssAccessorName> </attribute> <attribute> - <id>ATTR_MEM_EXP_RCD_SLEW_RATE</id> + <id>ATTR_MEM_EXP_SPD_TAA_MIN</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - RCD slew rate control from F1RC02,F1RC03,F1RC04,F1RC05 + Minimum Cas Latency Time (tAAmin) in Picosecond (Byte 24) </description> <initToZero></initToZero> <valueType>uint16</valueType> <writeable/> - <mssAccessorName>exp_rcd_slew_rate</mssAccessorName> + <mssUnits>ps</mssUnits> + <mssAccessorName>exp_spd_taa_min</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EXP_FIRMWARE_EMULATION_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Enable Special mode for Emulation Support + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <mssUnits>bool</mssUnits> + <enum>NORMAL = 0, EMULATION = 1</enum> + <writeable/> + <mssAccessorName>exp_firmware_emulation_mode</mssAccessorName> </attribute> </attributes> diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_eff_attributes.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_eff_attributes.xml new file mode 100644 index 000000000..76b295dd9 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_eff_attributes.xml @@ -0,0 +1,144 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_eff_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2019 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<attributes> + <attribute> + <id>ATTR_MEM_EFF_PSTATES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + This byte defines the allowed number of + P-States for the DDR4 Differential Memory Buffer. + P-States can be thought of as an available performance profile. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <array>2</array> + <writeable/> + <mssAccessorName>pstates</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_BYTE_ENABLES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + These bits are used to activate or deactivate bytes in the + DDR interface of the differential memory + buffer chip. + Right aligned data. + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <array>2</array> + <writeable/> + <mssAccessorName>byte_enables</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_NIBBLE_ENABLES</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + These bits are used to select the active nibbles or DQS on the DDR interface. + Right aligned data. + </description> + <initToZero></initToZero> + <valueType>uint32</valueType> + <array>2</array> + <writeable/> + <mssAccessorName>nibble_enables</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_FOUR_RANK_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + A-Side CA bus drives rank 0/1 + and B-Side CA bus drives rank 2/3, DQ/DQS are + shared across the ranks + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <array>2</array> + <mssUnits>bool</mssUnits> + <mssAccessorName>four_rank_mode</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_MRAM_SUPPORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + MRAM Support + Support timing parameters of Everspin DDR4 MRAM + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <array>2</array> + <mssUnits>bool</mssUnits> + <mssAccessorName>mram_support</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_DDP_COMPATIBILITY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + DDP Compatibility + Support 1 rank 3DS Device in DDP board routing. CKE[1], CSN[1], ODT[1] of + PHY are connected to C[0], C[1], C[2] of DRAM + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <array>2</array> + <mssUnits>bool</mssUnits> + <mssAccessorName>ddp_compatibility</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_TSV_8H_SUPPORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + TSV 8H Support + Support 8H 3DS routing in board routing when parity check is disabled + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, ENABLE = 1</enum> + <writeable/> + <array>2</array> + <mssUnits>bool</mssUnits> + <mssAccessorName>tsv_8h_support</mssAccessorName> + </attribute> + +</attributes> diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml index d10983bdb..348764642 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml @@ -82,7 +82,8 @@ <id>ATTR_MEM_VPD_DQ_MAP</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - [Dimm DQ PIN] The map from the Dual Inline Memory Module + ARRAY[Dimm DQ PIN] + The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin to the Module Package Data (DQ) Pinout </description> <initToZero></initToZero> @@ -95,306 +96,246 @@ <array>72</array> </attribute> - <attribute> - <id>ATTR_MEM_GEARDOWN_MODE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Gear Down Mode. - This is for DDR4 MRS3. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>HALF =0, QUARTER=1</enum> - <writeable/> - <array>2</array> - <mssAccessorName>geardown_mode</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC0F</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none</description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc0f</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_CS_CMD_LATENCY</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - CS to CMD/ADDR Latency. - This is for DDR4 MRS4. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8</enum> - <writeable/> - <array>2</array> - <mssAccessorName>cs_cmd_latency</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_CA_PARITY_LATENCY</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - C/A Parity Latency Mode. This is for DDR4 MRS5. - Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8</enum> - <writeable/> - <array>2</array> - <mssAccessorName>ca_parity_latency</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC02</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - F0RC02: Timing and IBT Control Word; Default value - 0x00. - Values Range from 0-8. No need to calculate; - User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc02</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC0F</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + F0RC0F - Command Latency Adder Control Word; + Default value - 04. Values Range from 00 to 04. + No need to calculate; User can override with desired experimental value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc0f</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC03</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - F0RC03 - CA and CS Signals Driver Characteristics Control Word; - Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc03</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_CS_CMD_LATENCY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + CS to CMD/ADDR Latency. + This is for DDR4 MRS4. + Computed in mss_eff_cnfg. + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8</enum> + <writeable/> + <array>2</array> + <mssAccessorName>cs_cmd_latency</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC04</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; - Default value - 0x05 (Moderate Drive). - Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc04</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_CA_PARITY_LATENCY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + C/A Parity Latency Mode. This is for DDR4 MRS5. + Computed in mss_eff_cnfg. Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8</enum> + <writeable/> + <array>2</array> + <mssAccessorName>ca_parity_latency</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC05</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - F0RC05 - Clock Driver Characteristics Control Word; - Default value - 0x05 (Moderate Drive). - Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc05</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC02</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + F0RC02: Timing and IBT Control Word; Default value - 0x00. + Values Range from 0-8. No need to calculate; + User can override with desired experimental value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc02</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC0B</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description>Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none</description> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC03</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + F0RC03 - CA and CS Signals Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. + Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. + </description> <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc0b</mssAccessorName> - </attribute> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc03</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC1X</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description>F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none</description> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC04</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). + Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. + </description> <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc1x</mssAccessorName> - </attribute> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc04</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F0RC7X</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description>F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none</description> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC05</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + F0RC05 - Clock Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). + Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. + </description> <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f0rc7x</mssAccessorName> - </attribute> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc05</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_DIMM_DDR4_F1RC00</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description>F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none</description> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC0B</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + Operating Voltage VDD and VrefCA Source Control Word; + Read from ATTR_MSS_VOLT_VDDR. Default value - 14. Values Range from 00 to 15 decimal. + No need to calculate; User can override with desired experimental value. + </description> <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array>2</array> - <mssAccessorName>dimm_ddr4_f1rc00</mssAccessorName> - </attribute> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc0b</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_VREF_DQ_TRAIN_VALUE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - vrefdq_train value. This is for DDR4 MRS6. - Computed in mss_eff_cnfg. Each memory channel will have a value. - Creator: mss_eff_cnfg - Consumer:various - Firmware notes: none - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <array> 2 4</array> - <mssAccessorName>vref_dq_train_value</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC1X</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + F0RC1x - Internal VrefCA Control Word; + Default value - 00. Values Range from 00 to 3F. + No need to calculate; User can override with desired experimental value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc1x</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_VREF_DQ_TRAIN_RANGE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - vrefdq_train range. This is for DDR4 MRS6. - Computed in mss_eff_cnfg. Each memory channel will have a value. - Creator: mss_eff_cnfg - Consumer:various - Firmware notes: none - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <enum>RANGE1 = 0, RANGE2 = 1</enum> - <writeable/> - <array> 2 4</array> - <mssAccessorName>vref_dq_train_range</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F0RC7X</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + F0RC7x: IBT Control Word; + Default value - 00. Values Range from 00 to FF.No need to calculate. + User can override with desired experimental value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f0rc7x</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_PSTATES</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Number of p-states used - Always set NumPStates to 1 for Explorer. - </description> - <valueType>uint8</valueType> - <initToZero></initToZero> - <writeable/> - <mssAccessorName>pstates</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F1RC00</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + F1RC00: Data Buffer Interface Driver Characteristics Control Word; + Default value - 00. Values Range from 00 to 0F. No need to calculate. + User can override with desired experimental value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f1rc00</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_BYTE_ENABLES</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Enable/Disable DBYTE macro (clock gating and IO tri-state) - 10-bit bitmap - Right aligned - </description> - <valueType>uint16</valueType> - <initToZero></initToZero> - <writeable/> - <mssAccessorName>byte_enables</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F1RC02</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + F1RC00: Data Buffer Interface Driver Characteristics Control Word; + Default value - 00. Values Range from 00 to 0F. No need to calculate; + User can override with desired experimental value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f1rc02</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_NIBBLE_ENABLES</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Account/Ignore training/dfi_bist result on the selected nibble. - 20-bit bitmap - Right aligned - </description> - <valueType>uint32</valueType> - <initToZero></initToZero> - <writeable/> - <mssAccessorName>nibble_enables</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F1RC03</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + F1RC00: Data Buffer Interface Driver Characteristics Control Word. + Default value - 00. Values Range from 00 to 0F. No need to calculate. + User can override with desired experimental value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f1rc03</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_TAA_MIN</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Timing value used to calculate CAS Latency - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <mssUnits>nck</mssUnits> - <mssAccessorName>taa_min</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F1RC04</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + F1RC00: Data Buffer Interface Driver Characteristics Control Word; + Default value - 00. Values Range from 00 to 0F. No need to calculate. + User can override with desired experimental value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f1rc04</mssAccessorName> + </attribute> - <attribute> - <id>ATTR_MEM_RANK_FOUR_MODE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - DIMM Rank 4 mode enable - </description> - <valueType>uint8</valueType> - <enum>DISABLE = 0, ENABLE = 1</enum> - <initToZero></initToZero> - <writeable/> - <mssAccessorName>rank4_mode</mssAccessorName> - </attribute> + <attribute> + <id>ATTR_MEM_DIMM_DDR4_F1RC05</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM] + F1RC00: Data Buffer Interface Driver Characteristics Control Word. + Default value - 00. Values Range from 00 to 0F. No need to calculate. + User can override with desired experimental value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>dimm_ddr4_f1rc05</mssAccessorName> + </attribute> </attributes> diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml index b34019c60..cec393f11 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml @@ -787,60 +787,4 @@ <mssAccessorName>volt_vpp</mssAccessorName> </attribute> - <attribute> - <id>ATTR_MEM_EFF_MRAM_SUPPORT</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Supports MRAM or not - </description> - <valueType>uint8</valueType> - <initToZero></initToZero> - <enum>NORMAL = 0, EVERSPIN = 1</enum> - <writeable/> - <mssAccessorName>mram_support</mssAccessorName> - </attribute> - - <attribute> - <id>ATTR_MEM_EFF_3DS_HEIGHT</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - ARRAY[DIMM] - Primary SDRAM Package Type. - Decodes Byte 6. - This byte defines the primary set of SDRAMs. - Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = 3DS - </description> - <valueType>uint8</valueType> - <initToZero></initToZero> - <enum>PLANAR = 0, H2 = 2, H4 = 4, H8 = 8</enum> - <writeable/> - <mssAccessorName>3ds_height</mssAccessorName> - </attribute> - -<attribute> - <id>ATTR_MEM_EFF_DDP_COMPATIBLE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - DDP Compatibility - </description> - <valueType>uint8</valueType> - <initToZero></initToZero> - <enum>DISABLE = 0, ENABLE = 1</enum> - <writeable/> - <mssAccessorName>ddp_compatibility</mssAccessorName> - </attribute> - -<attribute> - <id>ATTR_MEM_EFF_TSV8H_SUPPORT</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - TSVH8 Support - </description> - <valueType>uint8</valueType> - <initToZero></initToZero> - <enum>DISABLE = 0, ENABLE = 1</enum> - <writeable/> - <mssAccessorName>tsv8h_support</mssAccessorName> - </attribute> - </attributes> diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml index 008a90974..819336678 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml @@ -100,7 +100,8 @@ <id>ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] DQ and DQS Drive Impedance. + Array[DIMM][RANK] + DQ and DQS Drive Impedance. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -115,9 +116,10 @@ <id>ATTR_MEM_SI_DRAM_PREAMBLE</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. - The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for WRITE preamble. - E.g. 0b00010001 means 2 nCK preamble for both READ and WRITE + Array[DIMM][RANK] + Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. + The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for WRITE preamble. + E.g. 0b00010001 means 2 nCK preamble for both READ and WRITE </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -125,13 +127,15 @@ <enum>READ_PREAMBLE_BIT = 3, WRITE_PREAMBLE_BIT = 7</enum> <mssUnits>nCK</mssUnits> <mssAccessorName>si_dram_preamble</mssAccessorName> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_DRAM_RTT_NOM</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] DRAM side Nominal Termination Resistance in Ohms. + Array[DIMM][RANK] + DRAM side Nominal Termination Resistance in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -146,7 +150,8 @@ <id>ATTR_MEM_SI_DRAM_RTT_PARK</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] DRAM side Park Termination Resistance in Ohms. + Array[DIMM][RANK] + DRAM side Park Termination Resistance in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -161,7 +166,8 @@ <id>ATTR_MEM_SI_DRAM_RTT_WR</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] DRAM side Write Termination Resistance in Ohms. + Array[DIMM][RANK] + DRAM side Write Termination Resistance in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -173,23 +179,101 @@ </attribute> <attribute> + <id>ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM][RANK] + vrefdq_train value. This is for DDR4 MRS6. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2 4</array> + <mssAccessorName>si_vref_dq_train_value</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM][RANK] + vrefdq_train range. This is for DDR4 MRS6. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>RANGE1 = 0, RANGE2 = 1</enum> + <writeable/> + <array>2 4</array> + <mssAccessorName>si_vref_dq_train_range</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_SI_GEARDOWN_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[DIMM][RANK] + Gear Down Mode. + This is for DDR4 MRS3. + Each memory channel will have a value. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <enum>HALF =0, QUARTER=1</enum> + <writeable/> + <array>2 4</array> + <mssAccessorName>si_geardown_mode</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_SI_MC_DRV_DQ_DQS</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Array[DIMM][RANK] + Tx drive impedance for DQ/DQS of all ranks in ohms + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssAccessorName>si_mc_drv_dq_dqs</mssAccessorName> + <array>2 4</array> + </attribute> + + <attribute> + <id>ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Array[DIMM][RANK] + Memory Controller side Receiver Equalization for Data and Data Strobe Lines. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <enum>DISABLE = 0, ENABLE = 1</enum> + <mssAccessorName>si_mc_rcv_eq_dq_dqs</mssAccessorName> + <array>2 4</array> + </attribute> + + <attribute> <id>ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Memory Controller side Drive Equalization for Data and Data Strobe Lines. + Array[DIMM][RANK] + Memory Controller side Drive Equalization for Data and Data Strobe Lines. </description> <initToZero></initToZero> <valueType>uint8</valueType> <writeable/> <enum>DISABLE = 0, FFE = 1</enum> <mssAccessorName>si_mc_drv_eq_dq_dqs</mssAccessorName> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_IMP_CLK</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Memory Controller side Drive Impedance for Clock in Ohms. + Array[DIMM][RANK] + Memory Controller side Drive Impedance for Clock in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -197,13 +281,15 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_clk</mssAccessorName> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and Activate Lines in Ohms. + Array[DIMM][RANK] + Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and Activate Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -211,13 +297,15 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_cmd_addr</mssAccessorName> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_IMP_CNTL</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset Lines in Ohms. + Array[DIMM][RANK] + Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -225,13 +313,15 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_cntl</mssAccessorName> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_IMP_CSCID</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. + Array[DIMM][RANK] + Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -239,13 +329,15 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_cscid</mssAccessorName> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[PSTATE] Memory Controller side Drive Impedance Pull Down for Data and Data Strobe Lines in Ohms. + Array[DIMM][RANK] + Memory Controller side Drive Impedance Pull Down for Data and Data Strobe Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -253,14 +345,15 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_dq_dqs_pull_down</mssAccessorName> - <array>1</array> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[PSTATE] Memory Controller side Drive Impedance Pull Up for Data and Data Strobe Lines in Ohms. + Array[DIMM][RANK] + Memory Controller side Drive Impedance Pull Up for Data and Data Strobe Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -268,14 +361,15 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_imp_dq_dqs_pull_up</mssAccessorName> - <array>1</array> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Memory Controller side Drive Slew Rate for Clock in Ohms. + Array[DIMM][RANK] + Memory Controller side Drive Slew Rate for Clock in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -283,13 +377,15 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_slew_rate_clk</mssAccessorName> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Memory Controller side Drive Slew Rate for Address, Bank Address, Bank Group and Activate Lines in Ohms. + Array[DIMM][RANK] + Memory Controller side Drive Slew Rate for Address, Bank Address, Bank Group and Activate Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -297,13 +393,15 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_slew_rate_cmd_addr</mssAccessorName> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Memory Controller side Drive Slew Rate for Clock Enable, ODT, Parity, and Reset Lines in Ohms. + Array[DIMM][RANK] + Memory Controller side Drive Slew Rate for Clock Enable, ODT, Parity, and Reset Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -311,13 +409,15 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_slew_rate_cntl</mssAccessorName> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Memory Controller side Drive Slew Rate for Chip Select and Chip ID Lines in Ohms. + Array[DIMM][RANK] + Memory Controller side Drive Slew Rate for Chip Select and Chip ID Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -325,13 +425,15 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_slew_rate_cscid</mssAccessorName> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[PSTATE] Memory Controller side Drive Slew Rate for Data and Data Strobe Lines in Ohms. + Array[DIMM][RANK] + Memory Controller side Drive Slew Rate for Data and Data Strobe Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -339,20 +441,7 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_drv_slew_rate_dq_dqs</mssAccessorName> - <array>1</array> - </attribute> - - <attribute> - <id>ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Memory Controller side Receiver Equalization for Data and Data Strobe Lines. - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <writeable/> - <enum>DISABLE = 0, DFE = 1</enum> - <mssAccessorName>si_mc_rcv_eq_dq_dqs</mssAccessorName> + <array>2 4</array> </attribute> <attribute> @@ -367,13 +456,15 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_rcv_imp_alert_n</mssAccessorName> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[PSTATE] Memory Controller side Receiver Impedance. Data and Data Strobe Lines in Ohms. + Array[DIMM][RANK] + Memory Controller side Receiver Impedance. Data and Data Strobe Lines in Ohms. </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -381,15 +472,16 @@ <enum>DISABLE = 0</enum> <mssUnits>ohm</mssUnits> <mssAccessorName>si_mc_rcv_imp_dq_dqs</mssAccessorName> - <array>1</array> + <array>2 4</array> </attribute> <attribute> <id>ATTR_MEM_SI_ODT_RD</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. - The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] + Array[DIMM][RANK] + READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. + The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -402,8 +494,9 @@ <id>ATTR_MEM_SI_ODT_WR</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> - Array[DIMM][RANK] WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. - The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] + Array[DIMM][RANK] + WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. + The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] </description> <initToZero></initToZero> <valueType>uint8</valueType> |
