Additional checks to p9_extract_sbe_rc

- To detect NDD1 or other chip for seeprom & otp addr upd
- pibmem program exception
- otprom program exception
- Use sbe_cs bit to identify the state of pk loader
- Adding CBS_STATUS_REGISTERS,ROOT_CTRL_REGISTERS in xml
- Using ifndef __HOSTBOOT_MODULE while read MBOX registers
- Update all Non-Secure mode RC names

Change-Id: Ic764bbda94d9beb023aa1861cb143bf05b8ff06a
RTC: 174954
CQ: SW404908
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41738
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41770
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

4 files changed, 328 insertions, 163 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.C b/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.C
index b86bdd2b7..ff76b5d8a 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.C
@@ -65,6 +65,13 @@
 ///     4) If in SEEPROM data range, report error if RSP_INFO is non-zero response (0x7-FI2C timeout Error, 0x4-FI2C Seeprom cfg Err, else-FI2C PIB Err)
 ///
 ///     DEFAULT) If non of the above errors are detected then report as UNKNOWN_ERROR
+//
+/////////////////////////////// USE CASES ////////////////////////////////////
+//     1) FSP calling on any proc                                           //
+//     2) HB calling on master proc (after a failed chipop or something)    //
+//     3) HB calling on slave proc before SMP is up (initial sbe start)     //
+//     4) HB calling on slave proc after SMP is up (chipop fail)            //
+//////////////////////////////////////////////////////////////////////////////
 //------------------------------------------------------------------------------
 // *HWP HW Owner        : Soma BhanuTej <soma.bhanu@in.ibm.com>
 // *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
@@ -87,9 +94,10 @@
 
 
 fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip,
-                                    P9_EXTRACT_SBE_RC::RETURN_ACTION& o_return_action, bool i_set_sdb, bool i_unsecure_mode)
+                                    P9_EXTRACT_SBE_RC::RETURN_ACTION& o_return_action,
+                                    bool i_set_sdb,
+                                    bool i_unsecure_mode)
 {
-
     fapi2::buffer<uint64_t> l_data64;
     fapi2::buffer<uint64_t> l_data64_dbgpro;
     fapi2::buffer<uint64_t> l_data64_fi2c_status;
@@ -99,6 +107,7 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target<fapi2::TARGET_TYPE_PROC_
     fapi2::buffer<uint32_t> l_data32_ir;
     fapi2::buffer<uint32_t> l_data32_edr;
     fapi2::buffer<uint32_t> l_data32_iar;
+    fapi2::buffer<uint8_t>  l_is_ndd1;
     bool l_ppe_halt_state = true;
     bool l_data_mchk = false;
     bool otprom_addr_range = false;
@@ -107,7 +116,12 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target<fapi2::TARGET_TYPE_PROC_
     bool otprom_data_range = false;
     bool pibmem_data_range = false;
     bool seeprom_data_range = false;
+    bool l_is_HB_module = false;
     uint32_t HC, MCS, otprom_addr, mem_error, sib_rsp_info;
+    uint32_t SEEPROM_MIN_RANGE;
+    uint32_t SEEPROM_MAX_RANGE;
+    uint32_t MAGIC_NUMBER_MISMATCH_LOCATION;
+    uint32_t OTPROM_IMAGE_END_LOCATION;
 
     // FAPI_ASSERT condition constant
     const bool FAIL = false;
@@ -116,20 +130,55 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target<fapi2::TARGET_TYPE_PROC_
     const uint32_t OTPROM_MAX_RANGE  = 0x000C0378;
     const uint32_t PIBMEM_MIN_RANGE  = 0xFFFE8000;
     const uint32_t PIBMEM_MAX_RANGE  = 0xFFFFFFFF;
-    const uint32_t SEEPROM_MIN_RANGE = 0x80000000;
-    const uint32_t SEEPROM_MAX_RANGE = 0x80038E18;
+    const uint32_t SEEPROM_NDD1_MIN_RANGE = 0x80000000;
+    const uint32_t SEEPROM_NDD1_MAX_RANGE = 0x80038E18;
+    const uint32_t SEEPROM_NOT_NDD1_MIN_RANGE = 0xFF800000;
+    const uint32_t SEEPROM_NOT_NDD1_MAX_RANGE = 0xFF838E18;
+
+    // Interrupt Vector offsets locations
+    const uint32_t OTPROM_PROG_EXCEPTION_LOCATION = 0x000C00E0;
+    const uint32_t PIBMEM_PROG_EXCEPTION_LOCATION = 0xFFFE80E0;
 
-    // OTPROM Address constants as per the image on 28/Sep/2016
+    // OTPROM Address constants as per the image on 12/Jun/2017
     // These values might change on every recomilation of OTPROM binary
-    // Refs : /afs/apd/func/project/tools/cronus/p9/exe/dev/prcd_d/images/sbe_otprom.dis
-    const uint32_t MAGIC_NUMBER_MISMATCH_LOCATION = 0xC0188;
-    const uint32_t OTPROM_IMAGE_END_LOCATION      = 0xC016C;
+    // Refs : /afs/apd/func/project/tools/cronus/p9/exe/dev/prcd_d/images/sim/sbe_otprom_DD2.dis
+    const uint32_t NOT_NDD1_MAGIC_NUMBER_MISMATCH_LOCATION = 0xC0170;
+    const uint32_t NOT_NDD1_OTPROM_IMAGE_END_LOCATION      = 0xC016C;
+    // NDD1 address locations are extracted from HW System by Joachim Fenkes
+    const uint32_t NDD1_MAGIC_NUMBER_MISMATCH_LOCATION     = 0xC015C;
+    const uint32_t NDD1_OTPROM_IMAGE_END_LOCATION          = 0xC0158;
 
     FAPI_INF("p9_extract_sbe_rc : Entering ...");
 
+#ifdef __HOSTBOOT_MODULE
+    l_is_HB_module = true;
+#endif
+
+    FAPI_INF("p9_extract_sbe_rc : Inputs \n\ti_set_sdb = %s \n\ti_unsecure_mode = %s \n\tl_is_HB_module = %s",
+             btos(i_set_sdb), btos(i_unsecure_mode), btos(l_is_HB_module));
+
+    FAPI_DBG("p9_extract_sbe_rc: Reading chip ec attribute");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_EXTRACT_SBE_RC_P9NDD1_CHIPS, i_target_chip, l_is_ndd1));
+
+    if(l_is_ndd1)
+    {
+        FAPI_INF("p9_extract_sbe_rc: Detected as Nimbus DD1 chip");
+        MAGIC_NUMBER_MISMATCH_LOCATION = NDD1_MAGIC_NUMBER_MISMATCH_LOCATION;
+        OTPROM_IMAGE_END_LOCATION = NDD1_OTPROM_IMAGE_END_LOCATION;
+        SEEPROM_MIN_RANGE = SEEPROM_NDD1_MIN_RANGE;
+        SEEPROM_MAX_RANGE = SEEPROM_NDD1_MAX_RANGE;
+    }
+    else
+    {
+        MAGIC_NUMBER_MISMATCH_LOCATION = NOT_NDD1_MAGIC_NUMBER_MISMATCH_LOCATION;
+        OTPROM_IMAGE_END_LOCATION = NOT_NDD1_OTPROM_IMAGE_END_LOCATION;
+        SEEPROM_MIN_RANGE = SEEPROM_NOT_NDD1_MIN_RANGE;
+        SEEPROM_MAX_RANGE = SEEPROM_NOT_NDD1_MAX_RANGE;
+    }
+
     if(i_set_sdb)
     {
-        // Applying SDB setting
+        // Applying SDB setting required in usecase 1 & 3 only
         FAPI_DBG("p9_extract_sbe_rc: Setting chip in SDB mode");
         FAPI_TRY(getCfamRegister(i_target_chip, PERV_SB_CS_FSI, l_data32));
         l_data32.setBit<PERV_SB_CS_SECURE_DEBUG_MODE>();
@@ -146,7 +195,7 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target<fapi2::TARGET_TYPE_PROC_
 
     if (l_data64_dbgpro.getBit<PU_PPE_XIDBGPRO_XSR_HS>())
     {
-        FAPI_INF("p9_extract_sbe_rc : PPE is in HALT state");
+        FAPI_INF("p9_extract_sbe_rc : PPE is in HALT state and SDB is set %s", btos(i_set_sdb));
         l_ppe_halt_state  = true;
     }
     else
@@ -262,19 +311,66 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target<fapi2::TARGET_TYPE_PROC_
         l_data64.extractToRight(l_data32_ir, PU_PPE_XIRAMEDR_XIRAMGA_IR, PU_PPE_XIRAMEDR_XIRAMGA_IR_LEN);
         l_data64.extractToRight(l_data32_edr, PU_PPE_XIRAMEDR_EDR, PU_PPE_XIRAMEDR_EDR_LEN);
 
-        if(MCS == 0x4)
+        if(MCS == 0x4 ||
+           l_data32_iar == PIBMEM_PROG_EXCEPTION_LOCATION ||
+           l_data32_iar == OTPROM_PROG_EXCEPTION_LOCATION )
         {
             if((OTPROM_MIN_RANGE <= l_data32_iar) && (l_data32_iar <= OTPROM_MAX_RANGE))
             {
-                FAPI_DBG("p9_extract_sbe_rc : Program Interrupt occured in OTPROM memory program");
+                FAPI_DBG("p9_extract_sbe_rc : Program Interrupt occured during IVPR pointed to OTPROM memory range");
+
+                if(!l_is_ndd1)
+                {
+                    fapi2::buffer<uint8_t> l_sbe_code_state;
+                    FAPI_DBG("p9_extract_sbe_rc : Reading SB_MSG register to collect SBE Code state bits");
+
+                    if(l_is_HB_module && !i_set_sdb) //HB calling Master Proc or HB calling Slave after SMP
+                    {
+                        FAPI_TRY(getScom(i_target_chip, PERV_SB_MSG_SCOM, l_data64));
+                        l_data64.extractToRight(l_sbe_code_state, 30, 2);
+                    }
+                    else
+                    {
+                        FAPI_TRY(getCfamRegister(i_target_chip, PERV_SB_MSG_FSI, l_data32));
+                        l_data32.extractToRight(l_sbe_code_state, 30, 2);
+                    }
+
+                    if(l_sbe_code_state == 0x1)
+                    {
+                        o_return_action = P9_EXTRACT_SBE_RC::REIPL_UPD_SEEPROM;
+                        FAPI_ASSERT(FAIL, fapi2::EXTRACT_SBE_RC_MAGIC_NUMBER_MISMATCH()
+                                    .set_TARGET_CHIP(i_target_chip),
+                                    "ERROR:Program Interrupt occured, probably MAGIC NUMBER MISMATCH");
+
+                    }
+                    else if(l_sbe_code_state == 0x2)
+                    {
+                        o_return_action = P9_EXTRACT_SBE_RC::REIPL_BKP_SEEPROM;
+                        FAPI_ASSERT(FAIL, fapi2::EXTRACT_SBE_RC_SBE_L1_LOADER_FAIL()
+                                    .set_TARGET_CHIP(i_target_chip),
+                                    "ERROR:Program Interrupt occured during base loader (l1)");
+
+                    }
+                    else if(l_sbe_code_state == 0x3)
+                    {
+                        o_return_action = P9_EXTRACT_SBE_RC::REIPL_BKP_SEEPROM;
+                        FAPI_ASSERT(FAIL, fapi2::EXTRACT_SBE_RC_SBE_L2_LOADER_FAIL()
+                                    .set_TARGET_CHIP(i_target_chip),
+                                    "ERROR:Program Interrupt occured during pk loader")
+                    }
+                    else
+                    {
+                        FAPI_ERR("p9_extract_sbe_rc : SBE code state value = %02X is invalid", l_sbe_code_state);
+                    }
+                }
             }
             else if((PIBMEM_MIN_RANGE <= l_data32_iar) && (l_data32_iar <= PIBMEM_MAX_RANGE))
             {
-                FAPI_DBG("p9_extract_sbe_rc : Program Interrupt occured in PIBMEM memory program");
+                FAPI_ERR("p9_extract_sbe_rc : Program Interrupt occured in PIBMEM memory program");
             }
             else if((SEEPROM_MIN_RANGE <= l_data32_iar) && (l_data32_iar <= SEEPROM_MAX_RANGE))
             {
-                FAPI_DBG("p9_extract_sbe_rc : Program Interrupt occured in SEEPROM memory program");
+                FAPI_ERR("p9_extract_sbe_rc : Program Interrupt occured in SEEPROM memory program");
             }
             else
             {
@@ -408,7 +504,7 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target<fapi2::TARGET_TYPE_PROC_
                 //--  FAPI Asserts section for OTPROM --//
                 o_return_action = P9_EXTRACT_SBE_RC::NO_RECOVERY_ACTION;
                 FAPI_ASSERT(l_data64.getBit<PU_STATUS_REGISTER_UNCORR_ERROR>() != 1,
-                            fapi2::EXTRACT_SBE_RC_OTP_ECC_ERR_INSECURE_MODE()
+                            fapi2::EXTRACT_SBE_RC_OTP_ECC_ERR_NONSECURE_MODE()
                             .set_TARGET_CHIP(i_target_chip),
                             "ERROR:Uncorrectable error detected in OTPROM memory read");
             }
@@ -440,7 +536,7 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target<fapi2::TARGET_TYPE_PROC_
             }
         }
 
-        if(pibmem_addr_range)
+        if(pibmem_addr_range) // PIBMEM status register read is allowed in both Secure & NonSecure mode
         {
             FAPI_DBG("p9_extract_sbe_rc : Reading PIBMEM status register");
             FAPI_TRY(getScom(i_target_chip, PU_PIBMEM_STATUS_REG, l_data64));
@@ -524,148 +620,138 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target<fapi2::TARGET_TYPE_PROC_
             //--  FAPI Asserts section for PIBMEM --//
             o_return_action = P9_EXTRACT_SBE_RC::RESTART_SBE;
             FAPI_ASSERT(l_data64.getBit<PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_PIB>() != 1,
-                        fapi2::EXTRACT_SBE_RC_PIBMEM_ECC_ERR_INSECURE_MODE()
+                        fapi2::EXTRACT_SBE_RC_PIBMEM_ECC_ERR()
                         .set_TARGET_CHIP(i_target_chip),
-                        "ERROR:Uncorrectable error occurred while PIB memory read");
+                        "ERROR:Uncorrectable error occurred while accessing memory via PIB side");
 
             o_return_action = P9_EXTRACT_SBE_RC::RESTART_SBE;
             FAPI_ASSERT(l_data64.getBit<PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_FACES>() != 1,
-                        fapi2::EXTRACT_SBE_RC_PIBMEM_ECC_ERR_INSECURE_MODE()
+                        fapi2::EXTRACT_SBE_RC_PIBMEM_ECC_ERR()
                         .set_TARGET_CHIP(i_target_chip),
-                        "ERROR:Uncorrectable error occurred while fast access interface read");
+                        "ERROR:Uncorrectable error occurred while accessing memory via fast access side");
         }
 
-        if(seeprom_addr_range)
+        if(seeprom_addr_range && i_unsecure_mode)
         {
-            if(i_unsecure_mode)
-            {
-                FAPI_DBG("p9_extract_sbe_rc : Reading FI2CM mode register");
-                FAPI_TRY(getScom(i_target_chip, PU_MODE_REGISTER_B, l_data64));
-                FAPI_DBG("p9_extract_sbe_rc : FI2CM mode : %#018lX", l_data64);
+            FAPI_DBG("p9_extract_sbe_rc : Reading FI2CM mode register");
+            FAPI_TRY(getScom(i_target_chip, PU_MODE_REGISTER_B, l_data64));
+            FAPI_DBG("p9_extract_sbe_rc : FI2CM mode : %#018lX", l_data64);
 
-                l_data32.flush<0>();
-                l_data64.extractToRight(l_data32, 0, 16);
-                uint32_t i2c_speed = l_data32;
-
-                if(i2c_speed < 0x0003)
-                {
-                    o_return_action = P9_EXTRACT_SBE_RC::RESTART_SBE;
-                    FAPI_ASSERT(FAIL, fapi2::EXTRACT_SBE_RC_FI2CM_BIT_RATE_ERR()
-                                .set_TARGET_CHIP(i_target_chip),
-                                "ERROR:Speed on the I2C bit rate divisor is less than min speed value (0x0003), I2C Speed read is %04lX", i2c_speed);
-                }
-            }
+            l_data32.flush<0>();
+            l_data64.extractToRight(l_data32, 0, 16);
+            uint32_t i2c_speed = l_data32;
 
-            if(i_unsecure_mode)
+            if(i2c_speed < 0x0003)
             {
-                FAPI_DBG("p9_extract_sbe_rc : Reading FI2CM status register");
-                FAPI_TRY(getScom(i_target_chip, PU_STATUS_REGISTER_B, l_data64_fi2c_status));
-                FAPI_DBG("p9_extract_sbe_rc : FI2CM status : %#018lX", l_data64_fi2c_status);
-
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_ADDR_NVLD_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Address invalid bit set");
-                }
-
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_WRITE_NVLD_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Write invalid bit set");
-                }
+                o_return_action = P9_EXTRACT_SBE_RC::RESTART_SBE;
+                FAPI_ASSERT(FAIL, fapi2::EXTRACT_SBE_RC_FI2CM_BIT_RATE_ERR_NONSECURE_MODE()
+                            .set_TARGET_CHIP(i_target_chip),
+                            "ERROR:Speed on the I2C bit rate divisor is less than min speed value (0x0003), I2C Speed read is %04lX", i2c_speed);
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_READ_NVLD_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Read invalid bit set");
-                }
+            FAPI_DBG("p9_extract_sbe_rc : Reading FI2CM status register");
+            FAPI_TRY(getScom(i_target_chip, PU_STATUS_REGISTER_B, l_data64_fi2c_status));
+            FAPI_DBG("p9_extract_sbe_rc : FI2CM status : %#018lX", l_data64_fi2c_status);
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_ADDR_P_ERR_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Address parity error bit set");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_ADDR_NVLD_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Address invalid bit set");
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_PAR_ERR_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Data parity error bit set");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_WRITE_NVLD_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Write invalid bit set");
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_LB_PARITY_ERROR_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Local bus parity error bit set");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_READ_NVLD_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Read invalid bit set");
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_ECC_CORRECTED_ERROR_0>())
-                {
-                    FAPI_INF("p9_extract_sbe_rc : FI2CM::WARN:One bit flip was there in data and been corrected");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_ADDR_P_ERR_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Address parity error bit set");
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_ECC_UNCORRECTED_ERROR_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::There are 2 bit flips in read data which cannot be corrected");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_PAR_ERR_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Data parity error bit set");
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_ECC_CONFIG_ERROR_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Control register is ecc_enabled for data_length not equal to 8. OR ECC is enabled for the engine where ECC block is not instantiated");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_LB_PARITY_ERROR_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Local bus parity error bit set");
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_INVALID_COMMAND_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Invalid command bit set");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_ECC_CORRECTED_ERROR_0>())
+            {
+                FAPI_INF("p9_extract_sbe_rc : FI2CM::WARN:One bit flip was there in data and been corrected");
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_PARITY_ERROR_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Parity error bit set");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_ECC_UNCORRECTED_ERROR_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::There are 2 bit flips in read data which cannot be corrected");
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_BACK_END_OVERRUN_ERROR_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Back end overrun error bit set");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_ECC_CONFIG_ERROR_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Control register is ecc_enabled for data_length not equal to 8. OR ECC is enabled for the engine where ECC block is not instantiated");
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_BACK_END_ACCESS_ERROR_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Back end access error bit set");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_INVALID_COMMAND_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Invalid command bit set");
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_ARBITRATION_LOST_ERROR_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Arbitration lost error bit set");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_PARITY_ERROR_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Parity error bit set");
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_NACK_RECEIVED_ERROR_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::NACK receieved error bit set");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_BACK_END_OVERRUN_ERROR_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Back end overrun error bit set");
+            }
 
-                if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_STOP_ERROR_0>())
-                {
-                    FAPI_ERR("p9_extract_sbe_rc : FI2CM::Stop error bit set");
-                }
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_BACK_END_ACCESS_ERROR_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Back end access error bit set");
+            }
 
-                //--  FAPI Asserts section for SEEPROM --//
-                o_return_action = P9_EXTRACT_SBE_RC::REIPL_BKP_SEEPROM;
-                FAPI_ASSERT((l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_ECC_CONFIG_ERROR_0>() != 1           ||
-                             l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_INVALID_COMMAND_0>() != 1        ||
-                             l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_PARITY_ERROR_0>() != 1           ||
-                             l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_BACK_END_OVERRUN_ERROR_0>() != 1 ||
-                             l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_BACK_END_ACCESS_ERROR_0>() != 1  ||
-                             l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_ARBITRATION_LOST_ERROR_0>() != 1 ||
-                             l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_NACK_RECEIVED_ERROR_0>() != 1    ||
-                             l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_STOP_ERROR_0>() != 1),
-                            fapi2::EXTRACT_SBE_RC_FI2C_ERROR()
-                            .set_TARGET_CHIP(i_target_chip),
-                            "FI2C I2C Error detected");
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_ARBITRATION_LOST_ERROR_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Arbitration lost error bit set");
+            }
 
-                o_return_action = P9_EXTRACT_SBE_RC::REIPL_UPD_SEEPROM;
-                FAPI_ASSERT(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_ECC_UNCORRECTED_ERROR_0>() != 1,
-                            fapi2::EXTRACT_SBE_RC_FI2C_ECC_ERR_INSECURE_MODE()
-                            .set_TARGET_CHIP(i_target_chip),
-                            "ERROR:There are 2 bit flips in read data which cannot be corrected");
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_NACK_RECEIVED_ERROR_0>())
+            {
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::NACK receieved error bit set");
             }
-            else
+
+            if(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_STOP_ERROR_0>())
             {
-                // TODO - Read FI2CM status register by performing ramming of local register
+                FAPI_ERR("p9_extract_sbe_rc : FI2CM::Stop error bit set");
             }
+
+            //--  FAPI Asserts section for SEEPROM --//
+            o_return_action = P9_EXTRACT_SBE_RC::REIPL_BKP_SEEPROM;
+            FAPI_ASSERT((l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_ECC_CONFIG_ERROR_0>() != 1           ||
+                         l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_INVALID_COMMAND_0>() != 1        ||
+                         l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_PARITY_ERROR_0>() != 1           ||
+                         l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_BACK_END_OVERRUN_ERROR_0>() != 1 ||
+                         l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_BACK_END_ACCESS_ERROR_0>() != 1  ||
+                         l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_ARBITRATION_LOST_ERROR_0>() != 1 ||
+                         l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_NACK_RECEIVED_ERROR_0>() != 1    ||
+                         l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_BUS_STOP_ERROR_0>() != 1),
+                        fapi2::EXTRACT_SBE_RC_FI2C_ERR_NONSECURE_MODE()
+                        .set_TARGET_CHIP(i_target_chip),
+                        "FI2C I2C Error detected");
+
+            o_return_action = P9_EXTRACT_SBE_RC::REIPL_UPD_SEEPROM;
+            FAPI_ASSERT(l_data64_fi2c_status.getBit<PU_STATUS_REGISTER_B_ECC_UNCORRECTED_ERROR_0>() != 1,
+                        fapi2::EXTRACT_SBE_RC_FI2C_ECC_ERR_NONSECURE_MODE()
+                        .set_TARGET_CHIP(i_target_chip),
+                        "ERROR:There are 2 bit flips in read data which cannot be corrected");
         }
 
         // ------- LEVEL 4 ------ //
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.H b/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.H
index b1514672a..220dbb482 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.H
@@ -38,7 +38,7 @@
 
 #ifndef _P9_EXTRACT_SBE_RC_H_
 #define _P9_EXTRACT_SBE_RC_H_
-
+#define btos(x) ((x)?"TRUE":"FALSE")
 
 #include <fapi2.H>
 
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index ce6e23622..023706697 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -5358,6 +5358,23 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_EXTRACT_SBE_RC_P9NDD1_CHIPS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Use to detect Nimbus DD1 chips in p9_extract_sbe_rc procedure
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x10</value>
+          <test>EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_NO_GPTR_SUPPORT_VIA_MVPD</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_extract_sbe_rc_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_extract_sbe_rc_errors.xml
index ef5b31cd9..5f1bcb4da 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_extract_sbe_rc_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_extract_sbe_rc_errors.xml
@@ -42,6 +42,7 @@
     Action:Retrigger IPL or HRESET [RESTART_SBE]
     </description>
     <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -60,6 +61,7 @@
     Action:Retrigger IPL or HRESET [RESTART_SBE]
     </description>
     <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -75,8 +77,10 @@
     <rc>RC_EXTRACT_SBE_RC_PROGRAM_INTERRUPT</rc>
     <description>
     Program interrupt promoted
-    Action:Code update required [RESTART_SBE]
+    Action:Retrigger IPL or HRESET [RESTART_SBE]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -91,8 +95,10 @@
     <rc>RC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED</rc>
     <description>
     Address scope out of range
-    Action:Code update required [RESTART_SBE]
+    Action:Retrigger IPL or HRESET [RESTART_SBE]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -106,11 +112,13 @@
   <!-- Halt codes for OTPROM -->
   <!-- ******************************************************************** -->
   <hwpError>
-    <rc>RC_EXTRACT_SBE_RC_OTP_ECC_ERR_INSECURE_MODE</rc>
+    <rc>RC_EXTRACT_SBE_RC_OTP_ECC_ERR_NONSECURE_MODE</rc>
     <description>
     Uncorrectable error detected in OTPROM memory read
     Action:No recovery action possible to correct this error [NO_RECOVERY_ACTION]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -127,8 +135,56 @@
     <rc>RC_EXTRACT_SBE_RC_MAGIC_NUMBER_MISMATCH</rc>
     <description>
     SEEPROM magic number didn't match
-    Action:Reload/update of SEEPROM required [REIPL_UPD_SEEPROM]
+    Action:Update of SEEPROM required or switch seeprom [REIPL_UPD_SEEPROM]
+    </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>SBE_EXTERNAL_SCOMMABLE_REGISTERS</id><targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <target>TARGET_CHIP</target>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <priority>MEDIUM</priority>
+    </callout>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_EXTRACT_SBE_RC_SBE_L1_LOADER_FAIL</rc>
+    <description>
+    Program Interrupt occured during base loader
+    Action:Switch seeprom [REIPL_BKP_SEEPROM]
+    </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>SBE_EXTERNAL_SCOMMABLE_REGISTERS</id><targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <target>TARGET_CHIP</target>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <priority>MEDIUM</priority>
+    </callout>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_EXTRACT_SBE_RC_SBE_L2_LOADER_FAIL</rc>
+    <description>
+    Program Interrupt occured during pk loader
+    Action:Switch seeprom [REIPL_BKP_SEEPROM]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -150,6 +206,8 @@
     Branch to SEEPROM didn't happen
     Action:No recovery action possible to correct this error [NO_RECOVERY_ACTION]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -167,6 +225,8 @@
     Halted in OTPROM, but not at an expected halt location
     Action:No recovery action possible to correct this error [NO_RECOVERY_ACTION]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -182,11 +242,13 @@
   <!-- Halt codes for PIBMEM -->
   <!-- ******************************************************************** -->
   <hwpError>
-    <rc>RC_EXTRACT_SBE_RC_PIBMEM_ECC_ERR_INSECURE_MODE</rc>
+    <rc>RC_EXTRACT_SBE_RC_PIBMEM_ECC_ERR</rc>
     <description>
-    Uncorrectable error occurred while PIB memory read
-    Action:Reload/update of PIBMEM required [RESTART_SBE]
+    Uncorrectable error occurred while PIB memory access, Check if REPAIR solution is applied
+    Action:Retrigger IPL or HRESET [RESTART_SBE]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -206,11 +268,13 @@
   <!-- Halt codes for SEEPROM -->
   <!-- ******************************************************************** -->
   <hwpError>
-    <rc>RC_EXTRACT_SBE_RC_FI2CM_BIT_RATE_ERR</rc>
+    <rc>RC_EXTRACT_SBE_RC_FI2CM_BIT_RATE_ERR_NONSECURE_MODE</rc>
     <description>
     I2C bit rate divisor is less than min speed value
-    Action:Attempt an SBE restart [RESTART_SBE]
+    Action:Retrigger IPL or HRESET [RESTART_SBE]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -222,11 +286,13 @@
   </hwpError>
   <!-- ******************************************************************** -->
   <hwpError>
-    <rc>RC_EXTRACT_SBE_RC_FI2C_ERROR</rc>
+    <rc>RC_EXTRACT_SBE_RC_FI2C_ERR_NONSECURE_MODE</rc>
     <description>
     There are an FI2C I2C Error detected
     Action:Switch seeprom [REIPL_BKP_SEEPROM]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -240,11 +306,13 @@
   </hwpError>
   <!-- ******************************************************************** -->
   <hwpError>
-    <rc>RC_EXTRACT_SBE_RC_FI2C_ECC_ERR_INSECURE_MODE</rc>
+    <rc>RC_EXTRACT_SBE_RC_FI2C_ECC_ERR_NONSECURE_MODE</rc>
     <description>
     There are 2 bit flips in read data which cannot be corrected
     Action:Update of SEEPROM required or switch seeprom [REIPL_UPD_SEEPROM]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -265,6 +333,8 @@
     Uncorrectable error detected in OTPROM memory read
     Action:No recovery action possible to correct this error [NO_RECOVERY_ACTION]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -283,6 +353,8 @@
     PIB Timeout error detected
     Action:Warm ipl where we don't switch off VSB just toggle start_cbs from FSP [RESTART_CBS]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -305,6 +377,8 @@
     Scom error detected
     Action:Warm ipl where we don't switch off VSB just toggle start_cbs from FSP [RESTART_CBS]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -322,34 +396,13 @@
   </hwpError>
   <!-- ******************************************************************** -->
   <hwpError>
-    <rc>RC_EXTRACT_SBE_RC_PIBMEM_ECC_ERR</rc>
-    <description>
-    ECC error detected during pibmem access, Check if REPAIR solution is applied
-    Action:Retrigger IPL or HRESET [RESTART_SBE]
-    </description>
-    <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
-    <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
-    <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
-    <collectRegisterFfdc><id>SBE_EXTERNAL_SCOMMABLE_REGISTERS</id><targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
-    <collectRegisterFfdc><id>MIB_EXTERNAL_SCOMMABLE_REGISTERS</id><targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
-    <callout>
-      <target>TARGET_CHIP</target>
-      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-      <priority>HIGH</priority>
-    </callout>
-    <callout>
-      <procedure>CODE</procedure>
-      <priority>LOW</priority>
-    </callout>
-  </hwpError>
-
-  <!-- ******************************************************************** -->
-  <hwpError>
     <rc>RC_EXTRACT_SBE_RC_PIBMEM_PIB_ERR</rc>
     <description>
     Error detected during pibmem access
     Action:Warm ipl where we don't switch off VSB just toggle start_cbs from FSP [RESTART_CBS]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -368,6 +421,8 @@
     FI2C Timeout error detected
     Action:Reload/update of SEEPROM required or switch seeprom [REIPL_BKP_SEEPROM]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -386,6 +441,8 @@
     There are 2 bit flips in read data which cannot be corrected
     Action:Update of SEEPROM required or switch seeprom [REIPL_UPD_SEEPROM]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -404,6 +461,8 @@
     FI2C SEEPROM config error detected
     Action:Warm ipl where we don't switch off VSB just toggle start_cbs from FSP [RESTART_CBS]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -425,6 +484,8 @@
     FI2C PIB error detected
     Action:Warm ipl where we don't switch off VSB just toggle start_cbs from FSP [RESTART_CBS]
     </description>
+    <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
@@ -444,6 +505,7 @@
     Action:Switch seeprom [REIPL_BKP_SEEPROM]
     </description>
     <collectRegisterFfdc><id>CBS_STATUS_REGISTERS</id>            <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
+    <collectRegisterFfdc><id>ROOT_CTRL_REGISTERS_CFAM</id>        <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>I2C_REGISTERS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>PIBMEM_REGISTERS</id>                <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>
     <collectRegisterFfdc><id>OTPROM_STATUS</id>                   <targetType>TARGET_TYPE_PROC_CHIP</targetType><target>TARGET_CHIP</target></collectRegisterFfdc>