From 1f7535040ac87b87cd066fa6e52d54b6b79c863d Mon Sep 17 00:00:00 2001 From: Soma BhanuTej Date: Mon, 12 Jun 2017 04:54:01 -0400 Subject: Additional checks to p9_extract_sbe_rc - To detect NDD1 or other chip for seeprom & otp addr upd - pibmem program exception - otprom program exception - Use sbe_cs bit to identify the state of pk loader - Adding CBS_STATUS_REGISTERS,ROOT_CTRL_REGISTERS in xml - Using ifndef __HOSTBOOT_MODULE while read MBOX registers - Update all Non-Secure mode RC names Change-Id: Ic764bbda94d9beb023aa1861cb143bf05b8ff06a RTC: 174954 CQ: SW404908 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41738 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej Reviewed-by: Joachim Fenkes Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41770 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell --- .../p9/procedures/hwp/perv/p9_extract_sbe_rc.C | 342 +++++++++++++-------- .../p9/procedures/hwp/perv/p9_extract_sbe_rc.H | 2 +- .../xml/attribute_info/chip_ec_attributes.xml | 17 + .../xml/error_info/p9_extract_sbe_rc_errors.xml | 130 ++++++-- 4 files changed, 328 insertions(+), 163 deletions(-) (limited to 'src/import/chips') diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.C b/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.C index b86bdd2b7..ff76b5d8a 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.C @@ -65,6 +65,13 @@ /// 4) If in SEEPROM data range, report error if RSP_INFO is non-zero response (0x7-FI2C timeout Error, 0x4-FI2C Seeprom cfg Err, else-FI2C PIB Err) /// /// DEFAULT) If non of the above errors are detected then report as UNKNOWN_ERROR +// +/////////////////////////////// USE CASES //////////////////////////////////// +// 1) FSP calling on any proc // +// 2) HB calling on master proc (after a failed chipop or something) // +// 3) HB calling on slave proc before SMP is up (initial sbe start) // +// 4) HB calling on slave proc after SMP is up (chipop fail) // +////////////////////////////////////////////////////////////////////////////// //------------------------------------------------------------------------------ // *HWP HW Owner : Soma BhanuTej // *HWP HW Backup Owner : Srinivas V Naga @@ -87,9 +94,10 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target& i_target_chip, - P9_EXTRACT_SBE_RC::RETURN_ACTION& o_return_action, bool i_set_sdb, bool i_unsecure_mode) + P9_EXTRACT_SBE_RC::RETURN_ACTION& o_return_action, + bool i_set_sdb, + bool i_unsecure_mode) { - fapi2::buffer l_data64; fapi2::buffer l_data64_dbgpro; fapi2::buffer l_data64_fi2c_status; @@ -99,6 +107,7 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target l_data32_ir; fapi2::buffer l_data32_edr; fapi2::buffer l_data32_iar; + fapi2::buffer l_is_ndd1; bool l_ppe_halt_state = true; bool l_data_mchk = false; bool otprom_addr_range = false; @@ -107,7 +116,12 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target(); @@ -146,7 +195,7 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target()) { - FAPI_INF("p9_extract_sbe_rc : PPE is in HALT state"); + FAPI_INF("p9_extract_sbe_rc : PPE is in HALT state and SDB is set %s", btos(i_set_sdb)); l_ppe_halt_state = true; } else @@ -262,19 +311,66 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target l_sbe_code_state; + FAPI_DBG("p9_extract_sbe_rc : Reading SB_MSG register to collect SBE Code state bits"); + + if(l_is_HB_module && !i_set_sdb) //HB calling Master Proc or HB calling Slave after SMP + { + FAPI_TRY(getScom(i_target_chip, PERV_SB_MSG_SCOM, l_data64)); + l_data64.extractToRight(l_sbe_code_state, 30, 2); + } + else + { + FAPI_TRY(getCfamRegister(i_target_chip, PERV_SB_MSG_FSI, l_data32)); + l_data32.extractToRight(l_sbe_code_state, 30, 2); + } + + if(l_sbe_code_state == 0x1) + { + o_return_action = P9_EXTRACT_SBE_RC::REIPL_UPD_SEEPROM; + FAPI_ASSERT(FAIL, fapi2::EXTRACT_SBE_RC_MAGIC_NUMBER_MISMATCH() + .set_TARGET_CHIP(i_target_chip), + "ERROR:Program Interrupt occured, probably MAGIC NUMBER MISMATCH"); + + } + else if(l_sbe_code_state == 0x2) + { + o_return_action = P9_EXTRACT_SBE_RC::REIPL_BKP_SEEPROM; + FAPI_ASSERT(FAIL, fapi2::EXTRACT_SBE_RC_SBE_L1_LOADER_FAIL() + .set_TARGET_CHIP(i_target_chip), + "ERROR:Program Interrupt occured during base loader (l1)"); + + } + else if(l_sbe_code_state == 0x3) + { + o_return_action = P9_EXTRACT_SBE_RC::REIPL_BKP_SEEPROM; + FAPI_ASSERT(FAIL, fapi2::EXTRACT_SBE_RC_SBE_L2_LOADER_FAIL() + .set_TARGET_CHIP(i_target_chip), + "ERROR:Program Interrupt occured during pk loader") + } + else + { + FAPI_ERR("p9_extract_sbe_rc : SBE code state value = %02X is invalid", l_sbe_code_state); + } + } } else if((PIBMEM_MIN_RANGE <= l_data32_iar) && (l_data32_iar <= PIBMEM_MAX_RANGE)) { - FAPI_DBG("p9_extract_sbe_rc : Program Interrupt occured in PIBMEM memory program"); + FAPI_ERR("p9_extract_sbe_rc : Program Interrupt occured in PIBMEM memory program"); } else if((SEEPROM_MIN_RANGE <= l_data32_iar) && (l_data32_iar <= SEEPROM_MAX_RANGE)) { - FAPI_DBG("p9_extract_sbe_rc : Program Interrupt occured in SEEPROM memory program"); + FAPI_ERR("p9_extract_sbe_rc : Program Interrupt occured in SEEPROM memory program"); } else { @@ -408,7 +504,7 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target() != 1, - fapi2::EXTRACT_SBE_RC_OTP_ECC_ERR_INSECURE_MODE() + fapi2::EXTRACT_SBE_RC_OTP_ECC_ERR_NONSECURE_MODE() .set_TARGET_CHIP(i_target_chip), "ERROR:Uncorrectable error detected in OTPROM memory read"); } @@ -440,7 +536,7 @@ fapi2::ReturnCode p9_extract_sbe_rc(const fapi2::Target() != 1, - fapi2::EXTRACT_SBE_RC_PIBMEM_ECC_ERR_INSECURE_MODE() + fapi2::EXTRACT_SBE_RC_PIBMEM_ECC_ERR() .set_TARGET_CHIP(i_target_chip), - "ERROR:Uncorrectable error occurred while PIB memory read"); + "ERROR:Uncorrectable error occurred while accessing memory via PIB side"); o_return_action = P9_EXTRACT_SBE_RC::RESTART_SBE; FAPI_ASSERT(l_data64.getBit() != 1, - fapi2::EXTRACT_SBE_RC_PIBMEM_ECC_ERR_INSECURE_MODE() + fapi2::EXTRACT_SBE_RC_PIBMEM_ECC_ERR() .set_TARGET_CHIP(i_target_chip), - "ERROR:Uncorrectable error occurred while fast access interface read"); + "ERROR:Uncorrectable error occurred while accessing memory via fast access side"); } - if(seeprom_addr_range) + if(seeprom_addr_range && i_unsecure_mode) { - if(i_unsecure_mode) - { - FAPI_DBG("p9_extract_sbe_rc : Reading FI2CM mode register"); - FAPI_TRY(getScom(i_target_chip, PU_MODE_REGISTER_B, l_data64)); - FAPI_DBG("p9_extract_sbe_rc : FI2CM mode : %#018lX", l_data64); + FAPI_DBG("p9_extract_sbe_rc : Reading FI2CM mode register"); + FAPI_TRY(getScom(i_target_chip, PU_MODE_REGISTER_B, l_data64)); + FAPI_DBG("p9_extract_sbe_rc : FI2CM mode : %#018lX", l_data64); - l_data32.flush<0>(); - l_data64.extractToRight(l_data32, 0, 16); - uint32_t i2c_speed = l_data32; - - if(i2c_speed < 0x0003) - { - o_return_action = P9_EXTRACT_SBE_RC::RESTART_SBE; - FAPI_ASSERT(FAIL, fapi2::EXTRACT_SBE_RC_FI2CM_BIT_RATE_ERR() - .set_TARGET_CHIP(i_target_chip), - "ERROR:Speed on the I2C bit rate divisor is less than min speed value (0x0003), I2C Speed read is %04lX", i2c_speed); - } - } + l_data32.flush<0>(); + l_data64.extractToRight(l_data32, 0, 16); + uint32_t i2c_speed = l_data32; - if(i_unsecure_mode) + if(i2c_speed < 0x0003) { - FAPI_DBG("p9_extract_sbe_rc : Reading FI2CM status register"); - FAPI_TRY(getScom(i_target_chip, PU_STATUS_REGISTER_B, l_data64_fi2c_status)); - FAPI_DBG("p9_extract_sbe_rc : FI2CM status : %#018lX", l_data64_fi2c_status); - - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Address invalid bit set"); - } - - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Write invalid bit set"); - } + o_return_action = P9_EXTRACT_SBE_RC::RESTART_SBE; + FAPI_ASSERT(FAIL, fapi2::EXTRACT_SBE_RC_FI2CM_BIT_RATE_ERR_NONSECURE_MODE() + .set_TARGET_CHIP(i_target_chip), + "ERROR:Speed on the I2C bit rate divisor is less than min speed value (0x0003), I2C Speed read is %04lX", i2c_speed); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Read invalid bit set"); - } + FAPI_DBG("p9_extract_sbe_rc : Reading FI2CM status register"); + FAPI_TRY(getScom(i_target_chip, PU_STATUS_REGISTER_B, l_data64_fi2c_status)); + FAPI_DBG("p9_extract_sbe_rc : FI2CM status : %#018lX", l_data64_fi2c_status); - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Address parity error bit set"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Address invalid bit set"); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Data parity error bit set"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Write invalid bit set"); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Local bus parity error bit set"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Read invalid bit set"); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_INF("p9_extract_sbe_rc : FI2CM::WARN:One bit flip was there in data and been corrected"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Address parity error bit set"); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::There are 2 bit flips in read data which cannot be corrected"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Data parity error bit set"); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Control register is ecc_enabled for data_length not equal to 8. OR ECC is enabled for the engine where ECC block is not instantiated"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Local bus parity error bit set"); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Invalid command bit set"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_INF("p9_extract_sbe_rc : FI2CM::WARN:One bit flip was there in data and been corrected"); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Parity error bit set"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::There are 2 bit flips in read data which cannot be corrected"); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Back end overrun error bit set"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Control register is ecc_enabled for data_length not equal to 8. OR ECC is enabled for the engine where ECC block is not instantiated"); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Back end access error bit set"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Invalid command bit set"); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Arbitration lost error bit set"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Parity error bit set"); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::NACK receieved error bit set"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Back end overrun error bit set"); + } - if(l_data64_fi2c_status.getBit()) - { - FAPI_ERR("p9_extract_sbe_rc : FI2CM::Stop error bit set"); - } + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Back end access error bit set"); + } - //-- FAPI Asserts section for SEEPROM --// - o_return_action = P9_EXTRACT_SBE_RC::REIPL_BKP_SEEPROM; - FAPI_ASSERT((l_data64_fi2c_status.getBit() != 1 || - l_data64_fi2c_status.getBit() != 1 || - l_data64_fi2c_status.getBit() != 1 || - l_data64_fi2c_status.getBit() != 1 || - l_data64_fi2c_status.getBit() != 1 || - l_data64_fi2c_status.getBit() != 1 || - l_data64_fi2c_status.getBit() != 1 || - l_data64_fi2c_status.getBit() != 1), - fapi2::EXTRACT_SBE_RC_FI2C_ERROR() - .set_TARGET_CHIP(i_target_chip), - "FI2C I2C Error detected"); + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Arbitration lost error bit set"); + } - o_return_action = P9_EXTRACT_SBE_RC::REIPL_UPD_SEEPROM; - FAPI_ASSERT(l_data64_fi2c_status.getBit() != 1, - fapi2::EXTRACT_SBE_RC_FI2C_ECC_ERR_INSECURE_MODE() - .set_TARGET_CHIP(i_target_chip), - "ERROR:There are 2 bit flips in read data which cannot be corrected"); + if(l_data64_fi2c_status.getBit()) + { + FAPI_ERR("p9_extract_sbe_rc : FI2CM::NACK receieved error bit set"); } - else + + if(l_data64_fi2c_status.getBit()) { - // TODO - Read FI2CM status register by performing ramming of local register + FAPI_ERR("p9_extract_sbe_rc : FI2CM::Stop error bit set"); } + + //-- FAPI Asserts section for SEEPROM --// + o_return_action = P9_EXTRACT_SBE_RC::REIPL_BKP_SEEPROM; + FAPI_ASSERT((l_data64_fi2c_status.getBit() != 1 || + l_data64_fi2c_status.getBit() != 1 || + l_data64_fi2c_status.getBit() != 1 || + l_data64_fi2c_status.getBit() != 1 || + l_data64_fi2c_status.getBit() != 1 || + l_data64_fi2c_status.getBit() != 1 || + l_data64_fi2c_status.getBit() != 1 || + l_data64_fi2c_status.getBit() != 1), + fapi2::EXTRACT_SBE_RC_FI2C_ERR_NONSECURE_MODE() + .set_TARGET_CHIP(i_target_chip), + "FI2C I2C Error detected"); + + o_return_action = P9_EXTRACT_SBE_RC::REIPL_UPD_SEEPROM; + FAPI_ASSERT(l_data64_fi2c_status.getBit() != 1, + fapi2::EXTRACT_SBE_RC_FI2C_ECC_ERR_NONSECURE_MODE() + .set_TARGET_CHIP(i_target_chip), + "ERROR:There are 2 bit flips in read data which cannot be corrected"); } // ------- LEVEL 4 ------ // diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.H b/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.H index b1514672a..220dbb482 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_extract_sbe_rc.H @@ -38,7 +38,7 @@ #ifndef _P9_EXTRACT_SBE_RC_H_ #define _P9_EXTRACT_SBE_RC_H_ - +#define btos(x) ((x)?"TRUE":"FALSE") #include diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index ce6e23622..023706697 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -5357,6 +5357,23 @@ + + ATTR_CHIP_EC_FEATURE_EXTRACT_SBE_RC_P9NDD1_CHIPS + TARGET_TYPE_PROC_CHIP + + Use to detect Nimbus DD1 chips in p9_extract_sbe_rc procedure + + + + ENUM_ATTR_NAME_NIMBUS + + 0x10 + EQUAL + + + + + ATTR_CHIP_EC_FEATURE_NO_GPTR_SUPPORT_VIA_MVPD TARGET_TYPE_PROC_CHIP diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_extract_sbe_rc_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_extract_sbe_rc_errors.xml index ef5b31cd9..5f1bcb4da 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_extract_sbe_rc_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_extract_sbe_rc_errors.xml @@ -42,6 +42,7 @@ Action:Retrigger IPL or HRESET [RESTART_SBE] CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -60,6 +61,7 @@ Action:Retrigger IPL or HRESET [RESTART_SBE] CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -75,8 +77,10 @@ RC_EXTRACT_SBE_RC_PROGRAM_INTERRUPT Program interrupt promoted - Action:Code update required [RESTART_SBE] + Action:Retrigger IPL or HRESET [RESTART_SBE] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -91,8 +95,10 @@ RC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED Address scope out of range - Action:Code update required [RESTART_SBE] + Action:Retrigger IPL or HRESET [RESTART_SBE] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -106,11 +112,13 @@ - RC_EXTRACT_SBE_RC_OTP_ECC_ERR_INSECURE_MODE + RC_EXTRACT_SBE_RC_OTP_ECC_ERR_NONSECURE_MODE Uncorrectable error detected in OTPROM memory read Action:No recovery action possible to correct this error [NO_RECOVERY_ACTION] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -127,8 +135,56 @@ RC_EXTRACT_SBE_RC_MAGIC_NUMBER_MISMATCH SEEPROM magic number didn't match - Action:Reload/update of SEEPROM required [REIPL_UPD_SEEPROM] + Action:Update of SEEPROM required or switch seeprom [REIPL_UPD_SEEPROM] + + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP + I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP + SBE_EXTERNAL_SCOMMABLE_REGISTERSTARGET_TYPE_PROC_CHIPTARGET_CHIP + + CODE + HIGH + + + TARGET_CHIP + TARGET_TYPE_PROC_CHIP + MEDIUM + + + + + RC_EXTRACT_SBE_RC_SBE_L1_LOADER_FAIL + + Program Interrupt occured during base loader + Action:Switch seeprom [REIPL_BKP_SEEPROM] + + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP + I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP + SBE_EXTERNAL_SCOMMABLE_REGISTERSTARGET_TYPE_PROC_CHIPTARGET_CHIP + + CODE + HIGH + + + TARGET_CHIP + TARGET_TYPE_PROC_CHIP + MEDIUM + + + + + RC_EXTRACT_SBE_RC_SBE_L2_LOADER_FAIL + + Program Interrupt occured during pk loader + Action:Switch seeprom [REIPL_BKP_SEEPROM] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -150,6 +206,8 @@ Branch to SEEPROM didn't happen Action:No recovery action possible to correct this error [NO_RECOVERY_ACTION] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -167,6 +225,8 @@ Halted in OTPROM, but not at an expected halt location Action:No recovery action possible to correct this error [NO_RECOVERY_ACTION] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -182,11 +242,13 @@ - RC_EXTRACT_SBE_RC_PIBMEM_ECC_ERR_INSECURE_MODE + RC_EXTRACT_SBE_RC_PIBMEM_ECC_ERR - Uncorrectable error occurred while PIB memory read - Action:Reload/update of PIBMEM required [RESTART_SBE] + Uncorrectable error occurred while PIB memory access, Check if REPAIR solution is applied + Action:Retrigger IPL or HRESET [RESTART_SBE] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -206,11 +268,13 @@ - RC_EXTRACT_SBE_RC_FI2CM_BIT_RATE_ERR + RC_EXTRACT_SBE_RC_FI2CM_BIT_RATE_ERR_NONSECURE_MODE I2C bit rate divisor is less than min speed value - Action:Attempt an SBE restart [RESTART_SBE] + Action:Retrigger IPL or HRESET [RESTART_SBE] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -222,11 +286,13 @@ - RC_EXTRACT_SBE_RC_FI2C_ERROR + RC_EXTRACT_SBE_RC_FI2C_ERR_NONSECURE_MODE There are an FI2C I2C Error detected Action:Switch seeprom [REIPL_BKP_SEEPROM] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -240,11 +306,13 @@ - RC_EXTRACT_SBE_RC_FI2C_ECC_ERR_INSECURE_MODE + RC_EXTRACT_SBE_RC_FI2C_ECC_ERR_NONSECURE_MODE There are 2 bit flips in read data which cannot be corrected Action:Update of SEEPROM required or switch seeprom [REIPL_UPD_SEEPROM] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -265,6 +333,8 @@ Uncorrectable error detected in OTPROM memory read Action:No recovery action possible to correct this error [NO_RECOVERY_ACTION] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -283,6 +353,8 @@ PIB Timeout error detected Action:Warm ipl where we don't switch off VSB just toggle start_cbs from FSP [RESTART_CBS] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -305,6 +377,8 @@ Scom error detected Action:Warm ipl where we don't switch off VSB just toggle start_cbs from FSP [RESTART_CBS] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -320,29 +394,6 @@ MEDIUM - - - RC_EXTRACT_SBE_RC_PIBMEM_ECC_ERR - - ECC error detected during pibmem access, Check if REPAIR solution is applied - Action:Retrigger IPL or HRESET [RESTART_SBE] - - I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP - PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP - OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP - SBE_EXTERNAL_SCOMMABLE_REGISTERSTARGET_TYPE_PROC_CHIPTARGET_CHIP - MIB_EXTERNAL_SCOMMABLE_REGISTERSTARGET_TYPE_PROC_CHIPTARGET_CHIP - - TARGET_CHIP - TARGET_TYPE_PROC_CHIP - HIGH - - - CODE - LOW - - - RC_EXTRACT_SBE_RC_PIBMEM_PIB_ERR @@ -350,6 +401,8 @@ Error detected during pibmem access Action:Warm ipl where we don't switch off VSB just toggle start_cbs from FSP [RESTART_CBS] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -368,6 +421,8 @@ FI2C Timeout error detected Action:Reload/update of SEEPROM required or switch seeprom [REIPL_BKP_SEEPROM] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -386,6 +441,8 @@ There are 2 bit flips in read data which cannot be corrected Action:Update of SEEPROM required or switch seeprom [REIPL_UPD_SEEPROM] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -404,6 +461,8 @@ FI2C SEEPROM config error detected Action:Warm ipl where we don't switch off VSB just toggle start_cbs from FSP [RESTART_CBS] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -425,6 +484,8 @@ FI2C PIB error detected Action:Warm ipl where we don't switch off VSB just toggle start_cbs from FSP [RESTART_CBS] + CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP @@ -444,6 +505,7 @@ Action:Switch seeprom [REIPL_BKP_SEEPROM] CBS_STATUS_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP + ROOT_CTRL_REGISTERS_CFAM TARGET_TYPE_PROC_CHIPTARGET_CHIP I2C_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP PIBMEM_REGISTERS TARGET_TYPE_PROC_CHIPTARGET_CHIP OTPROM_STATUS TARGET_TYPE_PROC_CHIPTARGET_CHIP -- cgit v1.2.1