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| author | Andre A. Marin <aamarin@us.ibm.com> | 2019-04-30 18:24:49 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-06-05 22:16:04 -0500 |
| commit | ab3afc32f1e6d9577d42c8e93e3b517cc4d5b910 (patch) | |
| tree | 5182352a48c2b22f7721a72c6123041a01ee2046 /src/import/chips/p9a/procedures/xml/error_info | |
| parent | 7bf4bd00770914cca185a4fbe1898c5a54cc6201 (diff) | |
| download | talos-hostboot-ab3afc32f1e6d9577d42c8e93e3b517cc4d5b910.tar.gz talos-hostboot-ab3afc32f1e6d9577d42c8e93e3b517cc4d5b910.zip | |
Modify initial PRBS patter before DL link training starts
This meant to help the Xilinx FPGA transceivers receive
data more reliably. Since p9 used a PRBS setting of
250 ms, we are modifying the pre-IPL PRBS timer value
from 0b100 to 0b101 (256 ms) to best match it.
Change-Id: I9bb893061ef131e5b0831d36fcd1e36507c7eddd
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76786
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76876
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9a/procedures/xml/error_info')
0 files changed, 0 insertions, 0 deletions
