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authorAndre A. Marin <aamarin@us.ibm.com>2019-04-30 18:24:49 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2019-06-05 22:16:04 -0500
commitab3afc32f1e6d9577d42c8e93e3b517cc4d5b910 (patch)
tree5182352a48c2b22f7721a72c6123041a01ee2046 /src/import/chips/p9a/procedures
parent7bf4bd00770914cca185a4fbe1898c5a54cc6201 (diff)
downloadtalos-hostboot-ab3afc32f1e6d9577d42c8e93e3b517cc4d5b910.tar.gz
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Modify initial PRBS patter before DL link training starts
This meant to help the Xilinx FPGA transceivers receive data more reliably. Since p9 used a PRBS setting of 250 ms, we are modifying the pre-IPL PRBS timer value from 0b100 to 0b101 (256 ms) to best match it. Change-Id: I9bb893061ef131e5b0831d36fcd1e36507c7eddd Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76786 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76876 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9a/procedures')
-rw-r--r--src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H
index 1298699b5..7a11c0863 100644
--- a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H
+++ b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H
@@ -604,7 +604,7 @@ fapi2::ReturnCode setup_mc_config1_helper(const fapi2::Target<T>& i_target)
// CFG_DL0_CFG1_PREIPL_PRBS
l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME,
- TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME_LEN>(l_sim ? PREIPL_PRBS_1US : PREIPL_PRBS_64MS);
+ TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME_LEN>(l_sim ? PREIPL_PRBS_1US : PREIPL_PRBS_256MS);
l_val.template writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_ENA, 1>(1); // Enable
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