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| author | Stephen Glancy <sglancy@us.ibm.com> | 2018-11-08 17:01:16 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-02-13 19:50:23 -0600 |
| commit | b8427c4aa0721c64137494aad82b5cb7ca012bd4 (patch) | |
| tree | 95fa9100791d40e84f21ee4c6cfa881c9ab7ddcc /src/import/chips/p9/procedures/xml | |
| parent | 3ba6748d3f2c361ca1649ba7ec88150fc285274a (diff) | |
| download | talos-hostboot-b8427c4aa0721c64137494aad82b5cb7ca012bd4.tar.gz talos-hostboot-b8427c4aa0721c64137494aad82b5cb7ca012bd4.zip | |
Updates MCA write and read timings
Allows LRDIMM's to pass MCBIST writes and reads
Updates initfile code to use new attributes
Change-Id: I69c19bdc66ca3ab1ace61bbc49101f6ca8267065
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68568
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68573
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 5f11a0646..ff92b3fca 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -3077,6 +3077,34 @@ </attribute> <attribute> + <id>ATTR_MSS_EFF_DPHY_WLO</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + Write latency offset in number of clocks + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits>nCK</mssUnits> + <mssAccessorName>eff_dphy_wlo</mssAccessorName> + <array>2</array> + </attribute> + + <attribute> + <id>ATTR_MSS_EFF_DPHY_RLO</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + Read latency offset in number of clocks + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssUnits>nCK</mssUnits> + <mssAccessorName>eff_dphy_rlo</mssAccessorName> + <array>2</array> + </attribute> + + <attribute> <id>ATTR_EFF_DRAM_TREFI</id> <targetType>TARGET_TYPE_MCS</targetType> <description> |
