Updates MCA write and read timings

Allows LRDIMM's to pass MCBIST writes and reads
Updates initfile code to use new attributes

Change-Id: I69c19bdc66ca3ab1ace61bbc49101f6ca8267065
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68568
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68573
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

8 files changed, 328 insertions, 13 deletions

diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C
index 4efcb0e96..1a27cd2f7 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C
@@ -62,10 +62,10 @@ constexpr uint64_t literal_2401 = 2401;
 constexpr uint64_t literal_2666 = 2666;
 constexpr uint64_t literal_9 = 9;
 constexpr uint64_t literal_10 = 10;
+constexpr uint64_t literal_11 = 11;
 constexpr uint64_t literal_24 = 24;
 constexpr uint64_t literal_266 = 266;
 constexpr uint64_t literal_1866 = 1866;
-constexpr uint64_t literal_11 = 11;
 constexpr uint64_t literal_0b1000 = 0b1000;
 constexpr uint64_t literal_0b011000 = 0b011000;
 constexpr uint64_t literal_0x02 = 0x02;
@@ -146,8 +146,8 @@ fapi2::ReturnCode p9n_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0
         uint64_t l_def_MSS_FREQ_EQ_2133 = ((l_TGT1_ATTR_MSS_FREQ >= literal_1867) && (l_TGT1_ATTR_MSS_FREQ < literal_2134));
         uint64_t l_def_MSS_FREQ_EQ_2400 = ((l_TGT1_ATTR_MSS_FREQ >= literal_2134) && (l_TGT1_ATTR_MSS_FREQ < literal_2401));
         uint64_t l_def_MSS_FREQ_EQ_2666 = (l_TGT1_ATTR_MSS_FREQ >= literal_2666);
-        fapi2::ATTR_MSS_VPD_MR_DPHY_WLO_Type l_TGT2_ATTR_MSS_VPD_MR_DPHY_WLO;
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, TGT2, l_TGT2_ATTR_MSS_VPD_MR_DPHY_WLO));
+        fapi2::ATTR_MSS_EFF_DPHY_WLO_Type l_TGT2_ATTR_MSS_EFF_DPHY_WLO;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_DPHY_WLO, TGT2, l_TGT2_ATTR_MSS_EFF_DPHY_WLO));
         fapi2::ATTR_EFF_DRAM_CWL_Type l_TGT2_ATTR_EFF_DRAM_CWL;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_CWL, TGT2, l_TGT2_ATTR_EFF_DRAM_CWL));
         uint64_t l_def_RANK_SWITCH_TCK = (literal_4 + ((l_TGT1_ATTR_MSS_FREQ - literal_1866) / literal_266));
@@ -458,33 +458,33 @@ fapi2::ReturnCode p9n_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0
             else if ((((l_def_MSS_FREQ_EQ_1866 == literal_1)
                        && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
             {
-                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
+                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
             }
             else if ((((l_def_MSS_FREQ_EQ_2133 == literal_1)
                        && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
             {
-                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
+                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
             }
             else if ((((l_def_MSS_FREQ_EQ_2400 == literal_1)
                        && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
             {
-                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
+                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_10 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
             }
             else if ((((l_def_MSS_FREQ_EQ_2666 == literal_1)
                        && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW))
             {
-                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_10 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
+                l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_11 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) );
             }
 
             if ((l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1))
             {
                 l_scom_buffer.insert<30, 6, 58, uint64_t>(((l_TGT2_ATTR_EFF_DRAM_CWL[l_def_PORT_INDEX] +
-                        l_TGT2_ATTR_MSS_VPD_MR_DPHY_WLO[l_def_PORT_INDEX]) - literal_8) );
+                        l_TGT2_ATTR_MSS_EFF_DPHY_WLO[l_def_PORT_INDEX]) - literal_8) );
             }
             else if ((l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] != literal_1))
             {
                 l_scom_buffer.insert<30, 6, 58, uint64_t>(((l_TGT2_ATTR_EFF_DRAM_CWL[l_def_PORT_INDEX] +
-                        l_TGT2_ATTR_MSS_VPD_MR_DPHY_WLO[l_def_PORT_INDEX]) - literal_9) );
+                        l_TGT2_ATTR_MSS_EFF_DPHY_WLO[l_def_PORT_INDEX]) - literal_8) );
             }
 
             l_scom_buffer.insert<24, 6, 58, uint64_t>(literal_24 );
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
index 1968516fc..287be1eb5 100755
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
@@ -5966,6 +5966,98 @@ fapi_try_exit:
 }
 
 ///
+/// @brief Determines & sets effective PHY RLO values
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+///
+fapi2::ReturnCode eff_rdimm::phy_rlo()
+{
+    uint8_t l_mcs_attr[PORTS_PER_MCS] = {};
+    uint8_t l_vpd = 0;
+
+    // Gets the VPD value
+    FAPI_TRY( mss::vpd_mr_dphy_rlo(iv_mca, l_vpd));
+    FAPI_TRY( eff_dphy_rlo( iv_mcs, &(l_mcs_attr[0])) );
+
+    // Sets up the value
+    l_mcs_attr[iv_port_index] = l_vpd;
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_EFF_DPHY_RLO, iv_mcs, l_mcs_attr) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Determines & sets effective PHY RLO values
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+///
+fapi2::ReturnCode eff_lrdimm::phy_rlo()
+{
+    constexpr uint8_t LR_OFFSET = 1;
+    constexpr uint8_t RLO_MAX = 7;
+    uint8_t l_mcs_attr[PORTS_PER_MCS] = {};
+    uint8_t l_vpd = 0;
+
+    // Gets the VPD value
+    FAPI_TRY( mss::vpd_mr_dphy_rlo(iv_mca, l_vpd));
+    FAPI_TRY( eff_dphy_rlo( iv_mcs, &(l_mcs_attr[0])) );
+
+    // Sets up the value - ensure we don't have a rollover case
+    l_mcs_attr[iv_port_index] = std::min(uint8_t(l_vpd + LR_OFFSET), RLO_MAX);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_EFF_DPHY_RLO, iv_mcs, l_mcs_attr) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Determines & sets effective PHY WLO values
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+///
+fapi2::ReturnCode eff_rdimm::phy_wlo()
+{
+    uint8_t l_mcs_attr[PORTS_PER_MCS] = {};
+    uint8_t l_vpd = 0;
+
+    // Gets the VPD value
+    FAPI_TRY( mss::vpd_mr_dphy_wlo(iv_mca, l_vpd));
+    FAPI_TRY( eff_dphy_wlo( iv_mcs, &(l_mcs_attr[0])) );
+
+    // Sets up the value
+    l_mcs_attr[iv_port_index] = l_vpd;
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_EFF_DPHY_WLO, iv_mcs, l_mcs_attr) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief Determines & sets effective PHY WLO values
+/// @return fapi2::FAPI2_RC_SUCCESS if okay
+///
+fapi2::ReturnCode eff_lrdimm::phy_wlo()
+{
+    constexpr uint8_t LR_OFFSET = 2;
+    uint8_t l_mcs_attr[PORTS_PER_MCS] = {};
+    uint8_t l_vpd = 0;
+
+    // Gets the VPD value
+    FAPI_TRY( mss::vpd_mr_dphy_wlo(iv_mca, l_vpd));
+    FAPI_TRY( eff_dphy_wlo( iv_mcs, &(l_mcs_attr[0])) );
+
+    // Sets up the value - ensure we don't have an underflow case
+    l_mcs_attr[iv_port_index] = (l_vpd < LR_OFFSET) ? 0 : (l_vpd - LR_OFFSET);
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_EFF_DPHY_WLO, iv_mcs, l_mcs_attr) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+///
 /// @brief Determines & sets effective ODT read values
 /// @return fapi2::FAPI2_RC_SUCCESS if okay
 ///
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
index 656a061c5..d56dad024 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
@@ -583,6 +583,19 @@ class eff_dimm
         /// @return fapi2::FAPI2_RC_SUCCESS if okay
         ///
         virtual fapi2::ReturnCode odt_rd() = 0;
+
+        ///
+        /// @brief Determines & sets effective PHY RLO values
+        /// @return fapi2::FAPI2_RC_SUCCESS if okay
+        ///
+        virtual fapi2::ReturnCode phy_rlo() = 0;
+
+        ///
+        /// @brief Determines & sets effective PHY WLO values
+        /// @return fapi2::FAPI2_RC_SUCCESS if okay
+        ///
+        virtual fapi2::ReturnCode phy_wlo() = 0;
+
         ///
         /// @brief Determines & sets effective config for data_mask
         /// @return fapi2::FAPI2_RC_SUCCESS if okay
@@ -1102,6 +1115,19 @@ class eff_lrdimm : public eff_dimm
         virtual fapi2::ReturnCode odt_rd() final;
 
         ///
+        /// @brief Determines & sets effective PHY RLO values
+        /// @return fapi2::FAPI2_RC_SUCCESS if okay
+        ///
+        virtual fapi2::ReturnCode phy_rlo() final;
+
+        ///
+        /// @brief Determines & sets effective PHY WLO values
+        /// @return fapi2::FAPI2_RC_SUCCESS if okay
+        ///
+        virtual fapi2::ReturnCode phy_wlo() final;
+
+
+        ///
         /// @brief Sets the RTT_NOM value from SPD
         /// @return fapi2::FAPI2_RC_SUCCESS if okay
         /// @note used for MRS01
@@ -1422,6 +1448,19 @@ class eff_rdimm : public eff_dimm
         virtual fapi2::ReturnCode odt_rd() final;
 
         ///
+        /// @brief Determines & sets effective PHY RLO values
+        /// @return fapi2::FAPI2_RC_SUCCESS if okay
+        ///
+        virtual fapi2::ReturnCode phy_rlo() final;
+
+        ///
+        /// @brief Determines & sets effective PHY WLO values
+        /// @return fapi2::FAPI2_RC_SUCCESS if okay
+        ///
+        virtual fapi2::ReturnCode phy_wlo() final;
+
+
+        ///
         /// @brief Sets the RTT_NOM value from SPD
         /// @return fapi2::FAPI2_RC_SUCCESS if okay
         /// @note used for MRS01
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
index 089e275d9..45c7ee19c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H
@@ -425,7 +425,7 @@ inline uint64_t twlo_twloe(const fapi2::Target<T>& i_target)
     uint64_t l_twlo_twloe = 0;
     uint8_t l_twldqsen = 0;
 
-    FAPI_TRY( mss::vpd_mr_dphy_wlo(i_target, l_wlo_ck) );
+    FAPI_TRY( mss::eff_dphy_wlo(i_target, l_wlo_ck) );
     FAPI_TRY( mss::twldqsen(i_target, l_twldqsen) );
 
     // TODO RTC:160356 This changes if wlo is signed, which it's not but I wonder if it should
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index 4a452ded7..e27f82f69 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -10364,6 +10364,158 @@ fapi_try_exit:
 }
 
 ///
+/// @brief ATTR_MSS_EFF_DPHY_WLO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Write latency offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode eff_dphy_wlo(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_DPHY_WLO, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(i_target)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_EFF_DPHY_WLO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_EFF_DPHY_WLO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D.1)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Write latency offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode eff_dphy_wlo(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2];
+    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_DPHY_WLO, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(l_mca)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_EFF_DPHY_WLO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_EFF_DPHY_WLO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (E)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Write latency offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode eff_dphy_wlo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_DPHY_WLO, i_target, l_value) );
+    memcpy(o_array, &l_value, 2);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_EFF_DPHY_WLO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_EFF_DPHY_RLO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Read latency offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode eff_dphy_rlo(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_DPHY_RLO, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(i_target)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_EFF_DPHY_RLO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_EFF_DPHY_RLO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D.1)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Read latency offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode eff_dphy_rlo(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2];
+    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_DPHY_RLO, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(l_mca)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_EFF_DPHY_RLO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_EFF_DPHY_RLO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (E)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Read latency offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode eff_dphy_rlo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_DPHY_RLO, i_target, l_value) );
+    memcpy(o_array, &l_value, 2);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_EFF_DPHY_RLO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
 /// @brief ATTR_EFF_DRAM_TREFI getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
 /// @param[out] ref to the value uint16_t
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
index 8674997fd..9a7dbdb6c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2016,2019                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -142,8 +142,8 @@ fapi2::ReturnCode reset_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target)
     uint8_t l_type_index = 0;
     uint8_t l_gen_index = 0;
 
-    FAPI_TRY( mss::vpd_mr_dphy_rlo(i_target, l_rlo) );
-    FAPI_TRY( mss::vpd_mr_dphy_wlo(i_target, l_wlo) );
+    FAPI_TRY( mss::eff_dphy_rlo(i_target, l_rlo) );
+    FAPI_TRY( mss::eff_dphy_wlo(i_target, l_wlo) );
     FAPI_TRY( mss::eff_dram_gen(i_target, &(l_dram_gen[0])) );
     FAPI_TRY( mss::eff_dimm_type(i_target, &(l_dimm_type[0])) );
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
index d4501c1b3..7ce96a63d 100755
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
@@ -121,6 +121,10 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>
 
         FAPI_INF("Running eff_config on %s", mss::c_str(l_dimm) );
 
+        FAPI_TRY(  l_eff_dimm->phy_rlo(),
+                   "Failed phy_rlo for %s", mss::c_str(l_dimm) );
+        FAPI_TRY(  l_eff_dimm->phy_wlo(),
+                   "Failed phy_wlo for %s", mss::c_str(l_dimm) );
         FAPI_TRY( l_eff_dimm->rcd_mfg_id(),
                   "Failed rcd_mfg_id for %s", mss::c_str(l_dimm) );
         FAPI_TRY( l_eff_dimm->register_type(),
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
index 5f11a0646..ff92b3fca 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
@@ -3077,6 +3077,34 @@
     </attribute>
 
     <attribute>
+        <id>ATTR_MSS_EFF_DPHY_WLO</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            Write latency offset in number of clocks
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <writeable/>
+        <mssUnits>nCK</mssUnits>
+        <mssAccessorName>eff_dphy_wlo</mssAccessorName>
+        <array>2</array>
+    </attribute>
+
+    <attribute>
+        <id>ATTR_MSS_EFF_DPHY_RLO</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            Read latency offset in number of clocks
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <writeable/>
+        <mssUnits>nCK</mssUnits>
+        <mssAccessorName>eff_dphy_rlo</mssAccessorName>
+        <array>2</array>
+    </attribute>
+
+    <attribute>
       <id>ATTR_EFF_DRAM_TREFI</id>
       <targetType>TARGET_TYPE_MCS</targetType>
       <description>