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| author | Joe McGill <jmcgill@us.ibm.com> | 2019-06-02 09:25:40 -0400 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-06-05 22:16:48 -0500 |
| commit | 415af5749f8fc062e8185ace2e646c217e3bb876 (patch) | |
| tree | 8b3254f5e6044e5144e55ff4a331f18e4685c37a /src/import/chips/p9/procedures/xml | |
| parent | ab3afc32f1e6d9577d42c8e93e3b517cc4d5b910 (diff) | |
| download | talos-hostboot-415af5749f8fc062e8185ace2e646c217e3bb876.tar.gz talos-hostboot-415af5749f8fc062e8185ace2e646c217e3bb876.zip | |
create attribute to reflect DPLL input frequency
HWP code currently references the CP reference clock frequency as the
basis for DPLL programming.
This commit creates a new attribute to reflect the DPLL input clock
frequency, and sets its default value to 133 MHz, which is correct
for all current systems, regardless of the CP reference clock
frequency -- all p9n, p9c system configurations use a 133 MHz CP reference clock
input, while p9a systems will use 100 MHz.
Change-Id: I01685cb0346cc5b61edd8ff739717875fcf0f3a0
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78220
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78224
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml index 6f8b366f1..a64167bb3 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -39,6 +39,17 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_FREQ_DPLL_REFCLOCK_KHZ</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The frequency of the processor DPLL refclock in kHz. + </description> + <valueType>uint32</valueType> + <platInit/> + <default>133333</default> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_FREQ_MEM_REFCLOCK</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> |
