Update p9_setup_bars for 3 NPU's on Axone

- The PHY0/1 BARS were dropped.  The MMIO bar's 16M space
includes both 2M PHY spaces.
- Added Private Register Interface configuration registers
setup by attributes.

Change-Id: I7c4b6a23f2f46a8f6417b40201eafac57dd50945
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77769
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77777
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 177 insertions, 3 deletions

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml
index 920e0dcf1..88bd4192b 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2015,2018                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2019                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -167,6 +167,20 @@
     <mrwHide/>
   </attribute>
   <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>NPU MMIO (stack2) BAR enable
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
+    <platInit/>
+    <mrwHide/>
+  </attribute>
+  <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
@@ -185,9 +199,71 @@
   </attribute>
   <!-- ********************************************************************* -->
    <attribute>
-    <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id>
+    <id>ATTR_PROC_NPU0_MMIO_BAR_ENABLE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>NPU MMIO (stack2) BAR enable
+    <description>NPU0 MMIO BAR enable
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
+    <platInit/>
+    <mrwHide/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_NPU0_MMIO_BAR_BASE_ADDR_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>NPU MMIO BAR
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes:
+        Defines 16MB range mapped to NPU0 registers
+        Attribute holds offset (relative to chip MMIO origin) to program into
+        chip address range field of BAR -- Bits 15:39 of the RA
+        (excludes system/memory select/group/chip fields)
+    </description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <mrwHide/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_PROC_NPU1_MMIO_BAR_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>NPU1 MMIO BAR enable
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
+    <platInit/>
+    <mrwHide/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_NPU1_MMIO_BAR_BASE_ADDR_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>NPU1 MMIO BAR
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes:
+        Defines 16MB range mapped to NPU1 registers
+        Attribute holds offset (relative to chip MMIO origin) to program into
+        chip address range field of BAR -- Bits 15:39 of the RA
+        (excludes system/memory select/group/chip fields)
+    </description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <mrwHide/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_PROC_NPU2_MMIO_BAR_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>NPU2 MMIO BAR enable
       creator: platform
       consumer: p9_setup_bars
       firmware notes: none
@@ -199,6 +275,104 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
+    <id>ATTR_PROC_NPU2_MMIO_BAR_BASE_ADDR_OFFSET</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>NPU2 MMIO BAR
+      creator: platform
+      consumer: p9_setup_bars
+      firmware notes:
+        Defines 16MB range mapped to NPU2 registers
+        Attribute holds offset (relative to chip MMIO origin) to program into
+        chip address range field of BAR -- Bits 15:39 of the RA
+        (excludes system/memory select/group/chip fields)
+    </description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <mrwHide/>
+  </attribute>
+  <!-- ********************************************************************** -->
+  <attribute>
+    <id>ATTR_PROC_NPU0_PRI_CONFIG</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description> 
+      NPU0 NTL Private Register Interface (PRI) Configuration register settings
+      Array 0 = SM0 value
+            1 = SM1 value
+            2 = SM2 value
+            3 = SM3 value
+      Bits of values:
+      0    PRI_CONFIG_DISABLE: Disable
+      1    Disable (this will disable NTL from decoding the NDL register space)
+      1:2  PRI_CONFIG_NDL: NDL indication sent in the PRI Read/Write access
+            00 = NDL 0
+            01 = NDL 1
+            10 = NDL 2
+            11 = NDL 3
+      3:4 PRI_CONFIG_PHY: Indicates if NTL should decode a PHY register space
+            00 = Decode PHY0 register space
+            01 = Decode PHY1 register space
+            1- = Do not decode any PHY register space
+    </description>
+    <valueType>uint8</valueType>
+    <array>4</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************** -->
+  <attribute>
+    <id>ATTR_PROC_NPU1_PRI_CONFIG</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description> 
+      NPU1 NTL Private Register Interface (PRI) Configuration register settings
+      Array 0 = SM0 value
+            1 = SM1 value
+            2 = SM2 value
+            3 = SM3 value
+      Bits of values:
+      0    PRI_CONFIG_DISABLE: Disable
+      1    Disable (this will disable NTL from decoding the NDL register space)
+      1:2  PRI_CONFIG_NDL: NDL indication sent in the PRI Read/Write access
+            00 = NDL 0
+            01 = NDL 1
+            10 = NDL 2
+            11 = NDL 3
+      3:4 PRI_CONFIG_PHY: Indicates if NTL should decode a PHY register space
+            00 = Decode PHY0 register space
+            01 = Decode PHY1 register space
+            1- = Do not decode any PHY register space
+    </description>
+    <valueType>uint8</valueType>
+    <array>4</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************** -->
+  <attribute>
+    <id>ATTR_PROC_NPU2_PRI_CONFIG</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description> 
+      NPU2 NTL Private Register Interface (PRI) Configuration register settings
+      Array 0 = SM0 value
+            1 = SM1 value
+            2 = SM2 value
+            3 = SM3 value
+      Bits of values:
+      0    PRI_CONFIG_DISABLE: Disable
+      1    Disable (this will disable NTL from decoding the NDL register space)
+      1:2  PRI_CONFIG_NDL: NDL indication sent in the PRI Read/Write access
+            00 = NDL 0
+            01 = NDL 1
+            10 = NDL 2
+            11 = NDL 3
+      3:4 PRI_CONFIG_PHY: Indicates if NTL should decode a PHY register space
+            00 = Decode PHY0 register space
+            01 = Decode PHY1 register space
+            1- = Do not decode any PHY register space
+    </description>
+    <valueType>uint8</valueType>
+    <array>4</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
     <id>ATTR_PROC_PSI_BRIDGE_BAR_ENABLE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>PSI Bridge BAR enable