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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml $ -->
<!-- -->
<!-- OpenPOWER HostBoot Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2018 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- p9_setup_bars_attributes.xml -->
<attributes>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_FSP_BAR_ENABLE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>FSP BAR enable
creator: platform
consumer: p9_setup_bars
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>DISABLE = 0x0, ENABLE = 0x1</enum>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_FSP_BAR_BASE_ADDR_OFFSET</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>FSP BAR
creator: platform
consumer: p9_setup_bars
firmware notes:
Defines range mapped for FSP MMIO
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR -- RA bits 22:43
</description>
<valueType>uint64</valueType>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_FSP_BAR_SIZE</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>FSP BAR size value
creator: platform
consumer: p9_setup_bars
firmware notes: none
</description>
<valueType>uint64</valueType>
<enum>
4_GB = 0xFFFFFC00FFFFFFFF,
2_GB = 0xFFFFFC007FFFFFFF,
1_GB = 0xFFFFFC003FFFFFFF,
512_MB = 0xFFFFFC001FFFFFFF,
256_MB = 0xFFFFFC000FFFFFFF,
128_MB = 0xFFFFFC0007FFFFFF,
64_MB = 0xFFFFFC0003FFFFFF,
32_MB = 0xFFFFFC0001FFFFFF,
16_MB = 0xFFFFFC0000FFFFFF,
8_MB = 0xFFFFFC00007FFFFF,
4_MB = 0xFFFFFC00003FFFFF,
2_MB = 0xFFFFFC00001FFFFF,
1_MB = 0xFFFFFC00000FFFFF
</enum>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_FSP_MMIO_MASK_SIZE</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>FSP MMIO mask size value
creator: platform
consumer: p9_setup_bars
firmware notes:
AND mask applied to RA 32:35 when transmitting address to FSP
NOTE: RA 8:31 are always replaced with zero
</description>
<valueType>uint64</valueType>
<enum>
4_GB = 0x00F0000000000000,
2_GB = 0x0070000000000000,
1_GB = 0x0030000000000000,
512_MB = 0x0010000000000000,
256_MB = 0x0000000000000000
</enum>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_NPU_PHY0_BAR_ENABLE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>NPU PHY0 (stack0) BAR enable
creator: platform
consumer: p9_setup_bars
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>DISABLE = 0x0, ENABLE = 0x1</enum>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_NPU_PHY0_BAR_BASE_ADDR_OFFSET</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>NPU PHY0 (stack0) BAR
creator: platform
consumer: p9_setup_bars
firmware notes:
Defines 2MB range (size implied) mapped to PHY0 registers
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR -- RA bits 22:42
(excludes system/memory select/group/chip fields)
</description>
<valueType>uint64</valueType>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_NPU_PHY1_BAR_ENABLE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>NPU PHY1 (stack1) BAR enable
creator: platform
consumer: p9_setup_bars
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>DISABLE = 0x0, ENABLE = 0x1</enum>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_NPU_PHY1_BAR_BASE_ADDR_OFFSET</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>NPU PHY1 (stack1) BAR
creator: platform
consumer: p9_setup_bars
firmware notes:
Defines 2MB range (size implied) mapped to PHY1 registers
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR -- RA bits 22:42
(excludes system/memory select/group/chip fields)
</description>
<valueType>uint64</valueType>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>NPU MMIO (stack2) BAR
creator: platform
consumer: p9_setup_bars
firmware notes:
Defines 16MB range mapped to all NPU registers
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR -- RA bits 22:39
(excludes system/memory select/group/chip fields)
</description>
<valueType>uint64</valueType>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>NPU MMIO (stack2) BAR enable
creator: platform
consumer: p9_setup_bars
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>DISABLE = 0x0, ENABLE = 0x1</enum>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_PSI_BRIDGE_BAR_ENABLE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>PSI Bridge BAR enable
creator: platform
consumer: p9_setup_bars
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>DISABLE = 0x0, ENABLE = 0x1</enum>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR_OFFSET</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>PSI Bridge BAR base address offset
creator: platform
consumer: p9_setup_bars
firmware notes:
Defines 1MB range (size implied) mapped for PSI host-bridge
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR -- RA bits 22:43
(excludes system/memory select/group/chip fields)
</description>
<valueType>uint64</valueType>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************** -->
<attribute>
<id>ATTR_PROC_NX_RNG_BAR_ENABLE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>NX RNG BAR enable
creator: platform
consumer: p9_rng_init_phase2
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>DISABLE = 0x0, ENABLE = 0x1</enum>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>NX RNG BAR
creator: platform
consumer: p9_rng_init_phase2
firmware notes:
Defines 8KB range (size implied) mapped for NX RNG function
Attributes holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR -- RA bits 22:51
(excludes system/memory select/group/chip fields)
</description>
<valueType>uint64</valueType>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_NX_RNG_FAILED_INT_ENABLE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>Enable optional post of interrupt when both NX RNG noise
sources have failed
creator: platform
consumer: p9_rng_init_phase2
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>DISABLE = 0x0, ENABLE = 0x1</enum>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_NX_RNG_FAILED_INT_ADDR</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>Address used to post interrupt when both NX RNG noise
sources have failed
creator: platform
consumer: p9_rng_init_phase2
firmware notes:
64-bit address representing RA
NOTE: register covers RA 8:51
</description>
<valueType>uint64</valueType>
<platInit/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_INT_CQ_PC_BAR_ENABLE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>INT CQ PC BAR enable
creator: platform
consumer: p9_setup_bars
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>DISABLE = 0x0, ENABLE = 0x1</enum>
<platInit/>
<initToZero/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>INT CQ PC BAR base address offset
creator: platform
consumer: p9_setup_bars
firmware notes:
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR (excludes system/memsel/group/chip fields)
</description>
<valueType>uint64</valueType>
<platInit/>
<initToZero/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET_MASK</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>INT CQ PC BAR base address offset mask
creator: platform
consumer: p9_setup_bars
firmware notes:
Attribute holds offset mask (relative to chip MMIO origin) to program into
chip address range field of BAR mask (excludes system/memsel/group/chip fields)
Value defines which bits of VC_BAR are used during address compares
</description>
<valueType>uint64</valueType>
<platInit/>
<initToZero/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_INT_CQ_VC_BAR_ENABLE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>INT CQ VC BAR enable
creator: platform
consumer: p9_setup_bars
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>DISABLE = 0x0, ENABLE = 0x1</enum>
<platInit/>
<initToZero/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>INT CQ VC BAR base address offset
creator: platform
consumer: p9_setup_bars
firmware notes:
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR (excludes system/memsel/group/chip fields)
</description>
<valueType>uint64</valueType>
<platInit/>
<initToZero/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET_MASK</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>INT CQ VC BAR base address offset mask
creator: platform
consumer: p9_setup_bars
firmware notes:
Attribute holds offset mask (relative to chip MMIO origin) to program into
chip address range field of BAR mask (excludes system/memsel/group/chip fields)
Value defines which bits of VC_BAR are used during address compares
</description>
<valueType>uint64</valueType>
<platInit/>
<initToZero/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_INT_CQ_TM1_BAR_ENABLE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>INT CQ TM1 BAR enable
creator: platform
consumer: p9_setup_bars
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>DISABLE = 0x0, ENABLE = 0x1</enum>
<platInit/>
<initToZero/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_INT_CQ_TM1_BAR_BASE_ADDR_OFFSET</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>INT CQ TM1 BAR base address offset
creator: platform
consumer: p9_setup_bars
firmware notes:
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR (excludes system/memsel/group/chip fields)
</description>
<valueType>uint64</valueType>
<platInit/>
<initToZero/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_INT_CQ_TM1_BAR_PAGE_SIZE</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>INT CQ TM1 BAR page size
creator: platform
consumer: p9_setup_bars
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>4K = 0x0, 64K = 0x1</enum>
<platInit/>
<initToZero/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_INT_CQ_IC_BAR_ENABLE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>INT CQ IC BAR enable
creator: platform
consumer: p9_setup_bars
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>DISABLE = 0x0, ENABLE = 0x1</enum>
<platInit/>
<initToZero/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_INT_CQ_IC_BAR_BASE_ADDR_OFFSET</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>INT CQ IC BAR base address offset
creator: platform
consumer: p9_setup_bars
firmware notes:
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR (excludes system/memsel/group/chip fields)
</description>
<valueType>uint64</valueType>
<platInit/>
<initToZero/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
<attribute>
<id>ATTR_PROC_INT_CQ_IC_BAR_PAGE_SIZE</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>INT CQ IC (Interrupt Controller) BAR page size
creator: platform
consumer: p9_setup_bars
firmware notes: none
</description>
<valueType>uint8</valueType>
<enum>4K = 0x0, 64K = 0x1</enum>
<platInit/>
<initToZero/>
<mrwHide/>
</attribute>
<!-- ********************************************************************* -->
</attributes>
|
