diff options
| author | Yue Du <daviddu@us.ibm.com> | 2017-05-18 16:57:33 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-08-20 10:06:59 -0400 |
| commit | 42e98bd27614cfd29c287deaf20fd5c91e9467bb (patch) | |
| tree | f1c519ddd7aae166f8cdd3ce7f6dc5a9d999b320 /src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml | |
| parent | 7f0a2a2169db091a59ab321d8f7723710a5305d0 (diff) | |
| download | talos-hostboot-42e98bd27614cfd29c287deaf20fd5c91e9467bb.tar.gz talos-hostboot-42e98bd27614cfd29c287deaf20fd5c91e9467bb.zip | |
Istep4: procedures upgrade to level3
Change-Id: I281a7ba91a13f4694de78d65edb8a9ea65e4756e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40733
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44873
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml | 64 |
1 files changed, 31 insertions, 33 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml index c41d931ec..8154051c2 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml @@ -27,102 +27,100 @@ <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_DPLL_LOCK_TIMEOUT</rc> + <rc>RC_CACHE_DPLL_LOCK_TIMEOUT</rc> <description> DPLL is not locking. </description> - <ffdc>EQQPPMDPLLSTAT</ffdc> + <ffdc>EQ_QPPM_DPLL_STAT</ffdc> + <ffdc>DPLL_LOCK_POLL_DELAY_HW_NS</ffdc> + <ffdc>DPLL_LOCK_POLL_TIMEOUT_HW_NS</ffdc> + <ffdc>CACHE_TARGET</ffdc> <callout> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> <priority>HIGH</priority> </callout> <deconfigure> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </deconfigure> <gard> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_DPLLCLKSTART_TIMEOUT</rc> + <rc>RC_CACHE_DPLL_CLK_START_TIMEOUT</rc> <description> dpll clock start timed out. </description> - <ffdc>EQCPLTSTAT</ffdc> + <ffdc>EQ_CPLT_STAT</ffdc> + <ffdc>DPLL_START_POLL_DELAY_HW_NS</ffdc> + <ffdc>DPLL_START_POLL_TIMEOUT_HW_NS</ffdc> + <ffdc>CACHE_TARGET</ffdc> <callout> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> <priority>HIGH</priority> </callout> <deconfigure> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </deconfigure> <gard> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_DPLLCLKSTART_FAILED</rc> + <rc>RC_CACHE_DPLL_CLK_START_FAILED</rc> <description> dpll clock start failed. </description> - <ffdc>EQCLKSTAT</ffdc> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <sbeError/> - <rc>RC_PMPROC_ANEPCLKSTART_TIMEOUT</rc> - <description> - anep clock start timed out. - </description> - <ffdc>EQCPLTSTAT</ffdc> + <ffdc>EQ_CLK_STAT</ffdc> + <ffdc>CACHE_TARGET</ffdc> <callout> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> <priority>HIGH</priority> </callout> <deconfigure> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </deconfigure> <gard> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </gard> </hwpError> |
