Istep4: procedures upgrade to level3

Change-Id: I281a7ba91a13f4694de78d65edb8a9ea65e4756e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40733
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44873
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

5 files changed, 312 insertions, 81 deletions

diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml
index c41d931ec..8154051c2 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml
@@ -27,102 +27,100 @@
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_DPLL_LOCK_TIMEOUT</rc>
+    <rc>RC_CACHE_DPLL_LOCK_TIMEOUT</rc>
     <description>
         DPLL is not locking.
     </description>
-    <ffdc>EQQPPMDPLLSTAT</ffdc>
+    <ffdc>EQ_QPPM_DPLL_STAT</ffdc>
+    <ffdc>DPLL_LOCK_POLL_DELAY_HW_NS</ffdc>
+    <ffdc>DPLL_LOCK_POLL_TIMEOUT_HW_NS</ffdc>
+    <ffdc>CACHE_TARGET</ffdc>
     <callout>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
       </childTargets>
       <priority>HIGH</priority>
     </callout>
     <deconfigure>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
       </childTargets>
     </deconfigure>
     <gard>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
       </childTargets>
     </gard>
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_DPLLCLKSTART_TIMEOUT</rc>
+    <rc>RC_CACHE_DPLL_CLK_START_TIMEOUT</rc>
     <description>
         dpll clock start timed out.
     </description>
-    <ffdc>EQCPLTSTAT</ffdc>
+    <ffdc>EQ_CPLT_STAT</ffdc>
+    <ffdc>DPLL_START_POLL_DELAY_HW_NS</ffdc>
+    <ffdc>DPLL_START_POLL_TIMEOUT_HW_NS</ffdc>
+    <ffdc>CACHE_TARGET</ffdc>
     <callout>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
       </childTargets>
       <priority>HIGH</priority>
     </callout>
     <deconfigure>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
       </childTargets>
     </deconfigure>
     <gard>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
       </childTargets>
     </gard>
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_DPLLCLKSTART_FAILED</rc>
+    <rc>RC_CACHE_DPLL_CLK_START_FAILED</rc>
     <description>
         dpll clock start failed.
     </description>
-    <ffdc>EQCLKSTAT</ffdc>
-  </hwpError>
-  <!-- ********************************************************************* -->
-  <hwpError>
-    <sbeError/>
-    <rc>RC_PMPROC_ANEPCLKSTART_TIMEOUT</rc>
-    <description>
-        anep clock start timed out.
-    </description>
-    <ffdc>EQCPLTSTAT</ffdc>
+    <ffdc>EQ_CLK_STAT</ffdc>
+    <ffdc>CACHE_TARGET</ffdc>
     <callout>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
       </childTargets>
       <priority>HIGH</priority>
     </callout>
     <deconfigure>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
       </childTargets>
     </deconfigure>
     <gard>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
       </childTargets>
     </gard>
   </hwpError>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_initf_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_initf_errors.xml
index 5a2946c82..bf0c1d270 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_initf_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_initf_errors.xml
@@ -26,11 +26,12 @@
 <hwpErrors>
   <!-- ********************************************************************* -->
   <hwpError>
-    <rc>RC_P9_HCD_CACHE_INITF_INCORRECT_EQ_SCAN64_VAL</rc>
+    <rc>RC_NDD1_CACHE_INITF_INCORRECT_EQ_SCAN64_VAL</rc>
     <description>
-        Data mis-match on EQ_SCAN64 
+        Data mis-match on EQ_SCAN64, for Nimbus DD1 MPIPL workaround only 
     </description>
     <ffdc>EQ_SCAN64_VAL</ffdc>
+    <ffdc>CACHE_TARGET</ffdc>
   </hwpError>  
   <!-- ********************************************************************* -->
 </hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_scominit_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_scominit_errors.xml
index d309bdf9c..4ef5be3ce 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_scominit_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_scominit_errors.xml
@@ -27,11 +27,23 @@
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_CACHESCOMINIT_NOGOODCOREINEX</rc>
+    <rc>RC_CACHE_SCOMINIT_NO_GOOD_CORE_IN_EX</rc>
     <description>
         no partial good core in partial good ex, check qcsr configuration
     </description>
     <ffdc>QCSR</ffdc>
+    <ffdc>CACHE_TARGET</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
   </hwpError>
   <!-- ********************************************************************* -->
 </hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml
index e060a8744..1c9e54700 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml
@@ -27,67 +27,170 @@
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_CACHECPLTALIGN_TIMEOUT</rc>
+    <rc>RC_CACHE_CPLT_ALIGN_TIMEOUT</rc>
     <description>
         cache chiplets alignment timed out.
     </description>
-    <ffdc>EQCPLTSTAT0</ffdc>
+    <ffdc>EQ_CPLT_STAT0</ffdc>
+    <ffdc>CACHE_CPLT_ALIGN_POLL_DELAY_HW_NS</ffdc>
+    <ffdc>CACHE_CPLT_ALIGN_POLL_TIMEOUT_HW_NS</ffdc>
+    <ffdc>CACHE_TARGET</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_CACHE_XSTOP</rc>
+    <rc>RC_CACHE_CHECKSTOP_AFTER_CLK_START</rc>
     <description>
-        cache checkstops.
+        cache chiplet detects a checkstop after cache chiplet clock starts.
     </description>
-    <ffdc>EQXFIR</ffdc>
+    <ffdc>EQ_XFIR</ffdc>
+    <ffdc>CACHE_TARGET</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>MEDIUM</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_CACHECLKSYNC_TIMEOUT</rc>
+    <rc>RC_CACHE_CLK_SYNC_TIMEOUT</rc>
     <description>
         L2 EXs clock sync done timed out.
     </description>
-    <ffdc>EQPPMQACSR</ffdc>
+    <ffdc>EQ_QPPM_QACSR</ffdc>
+    <ffdc>CACHE_CLK_SYNC_POLL_DELAY_HW_NS</ffdc>
+    <ffdc>CACHE_CLK_SYNC_POLL_TIMEOUT_HW_NS</ffdc>
+    <ffdc>CACHE_TARGET</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_CACHECLKSTART_FAILED</rc>
+    <rc>RC_CACHE_CLK_START_FAILED</rc>
     <description>
         cache clock start failed.
     </description>
-    <ffdc>EQCLKSTAT</ffdc>
+    <ffdc>EQ_CLK_STAT</ffdc>
+    <ffdc>CACHE_TARGET</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_CACHECLKSTART_TIMEOUT</rc>
+    <rc>RC_CACHE_CLK_START_TIMEOUT</rc>
     <description>
         cache clock start timed out.
     </description>
-    <ffdc>EQCPLTSTAT</ffdc>
+    <ffdc>EQ_CPLT_STAT</ffdc>
+    <ffdc>CACHE_CLK_START_POLL_DELAY_HW_NS</ffdc>
+    <ffdc>CACHE_CLK_START_POLL_TIMEOUT_HW_NS</ffdc>
+    <ffdc>CACHE_TARGET</ffdc>
     <callout>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
       </childTargets>
       <priority>HIGH</priority>
     </callout>
     <deconfigure>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
       </childTargets>
     </deconfigure>
     <gard>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_EQ</childType>
+        <childNumber>EQ_NUMBER_IN_ERROR</childNumber>
       </childTargets>
     </gard>
   </hwpError>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml
index e781d46a1..46b5a8f79 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml
@@ -27,85 +27,202 @@
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_CORECPLTALIGN_TIMEOUT</rc>
+    <rc>RC_CORE_CPLT_ALIGN_TIMEOUT</rc>
     <description>
         core chiplets alignment timed out.
     </description>
-    <ffdc>CORECPLTSTAT0</ffdc>
-  </hwpError>
-  <!-- ********************************************************************* -->
-  <hwpError>
-    <sbeError/>
-    <rc>RC_PMPROC_QUADCPLTALIGN_FAILED</rc>
-    <description>
-        quad chiplets alignment failed.
-    </description>
-    <ffdc>QUADCPLTSTAT0</ffdc>
+    <ffdc>CORE_CPLT_STAT0</ffdc>
+    <ffdc>CORE_CPLT_ALIGN_POLL_DELAY_HW_NS</ffdc>
+    <ffdc>CORE_CPLT_ALIGN_POLL_TIMEOUT_HW_NS</ffdc>
+    <ffdc>CORE_TARGET</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_CORECPLTALIGN_FAILED</rc>
+    <rc>RC_CORE_CPLT_ALIGN_FAILED</rc>
     <description>
         core chiplets alignment failed.
     </description>
-    <ffdc>CORECPLTSTAT0</ffdc>
+    <ffdc>CORE_CPLT_STAT0</ffdc>
+    <ffdc>CORE_TARGET</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_CORE_XSTOP</rc>
+    <rc>RC_CORE_CHECKSTOP_AFTER_CLK_START</rc>
     <description>
-        core checkstops.
+        core chiplet detects a checkstop after core chiplet clock starts.
     </description>
-    <ffdc>COREXFIR</ffdc>
+    <ffdc>CORE_XFIR</ffdc>
+    <ffdc>CORE_TARGET</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>MEDIUM</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_CORECLKSYNC_TIMEOUT</rc>
+    <rc>RC_CORE_CLK_SYNC_TIMEOUT</rc>
     <description>
         core clock sync done timed out.
     </description>
-    <ffdc>COREPPMCACSR</ffdc>
+    <ffdc>CORE_CPPM_CACSR</ffdc>
+    <ffdc>CORE_CLK_SYNC_POLL_DELAY_HW_NS</ffdc>
+    <ffdc>CORE_CLK_SYNC_POLL_TIMEOUT_HW_NS</ffdc>
+    <ffdc>CORE_TARGET</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_CORECLKSTART_FAILED</rc>
+    <rc>RC_CORE_CLK_START_FAILED</rc>
     <description>
         core clock start failed.
     </description>
-    <ffdc>CORECLKSTAT</ffdc>
+    <ffdc>CORE_CLK_STAT</ffdc>
+    <ffdc>CORE_TARGET</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
     <sbeError/>
-    <rc>RC_PMPROC_CORECLKSTART_TIMEOUT</rc>
+    <rc>RC_CORE_CLK_START_TIMEOUT</rc>
     <description>
         core clock start timed out.
     </description>
-    <ffdc>CORECPLTSTAT</ffdc>
+    <ffdc>CORE_CPLT_STAT</ffdc>
+    <ffdc>CORE_CLK_START_POLL_DELAY_HW_NS</ffdc>
+    <ffdc>CORE_CLK_START_POLL_TIMEOUT_HW_NS</ffdc>
+    <ffdc>CORE_TARGET</ffdc>
     <callout>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
       </childTargets>
       <priority>HIGH</priority>
     </callout>
     <deconfigure>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
       </childTargets>
     </deconfigure>
     <gard>
       <childTargets>
         <parent>PROC_CHIP_IN_ERROR</parent>
-        <childType>TARGET_TYPE_EX_CHIPLET</childType>
-        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+        <childType>TARGET_TYPE_CORE</childType>
+        <childNumber>CORE_NUMBER_IN_ERROR</childNumber>
       </childTargets>
     </gard>
   </hwpError>