p9_htm_setup (L2) - Part 2: HTM setup/reset/start

RTC:138851
Change-Id: Icedf9f1a020948c5515edaf92c9de40897b2ad69
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25689
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25691
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 370 insertions, 183 deletions

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_htm_setup_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_htm_setup_attributes.xml
index d1378fdb2..f12661eb6 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_htm_setup_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_htm_setup_attributes.xml
@@ -7,7 +7,7 @@
 <!--                                                                        -->
 <!-- EKB Project                                                            -->
 <!--                                                                        -->
-<!-- COPYRIGHT 2015                                                         -->
+<!-- COPYRIGHT 2015,2016                                                    -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -24,33 +24,27 @@
 <attribute>
   <id>ATTR_NHTM_TRACE_TYPE</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> The Nest HTM trace type desired to be collected.
-                - Platform is to default to DISABLE (0x0).
-                - User can change NHTM trace type (i.e. enable NHTM trace
-                  collection) using Attribute Override.
-                </description>
+  <description> The Nest HTM trace type desired to be collected.  This setting
+                is applied to both NHTM0 and NHTM1.
+  </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, FABRIC = 0x1, EVENT = 0x2, OCC = 0x3 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 <!-- ********************************************************************** -->
 <attribute>
   <id>ATTR_CHTM_TRACE_TYPE</id>
-<!-- TODO: Need to handle CHTM trace targets.
-           See review comments in: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/#/c/21527/ -->
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> The Core HTM trace type desired to be collected.
-                - Platform is to default to DISABLE (0x0)
-                - User can change CHTM trace type (i.e. enable CHTM trace
-                  collection) using Attribute Override.
-                </description>
+  </description>
   <valueType>uint8</valueType>
+  <array>24</array>
   <enum> DISABLE = 0x0, CORE = 0x1, LLAT = 0x2, PPE = 0x3, DMW = 0x4 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <!-- **************************************************
@@ -60,77 +54,74 @@
   <id>ATTR_HTMSC_TTYPEFILT_PAT</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: defines the TTYPE pattern to match in Fabric trace
-                mode.
+                mode.  These bits are used with the ttype Filter Mask to
+                indicate the TTYPE value that should be matched on the rcmd.
                 HTM Ttype Filter Control Register (1:7).
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
   <id>ATTR_HTMSC_TSIZEFILT_PAT</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: defines the TSIZE pattern to match in Fabric trace
-                mode.
+                mode. These bits are used with the tsize filter mask to indicate
+                the TSIZE value that should be matched on the rcmd
                 HTM Ttype Filter Control Register (8:15).
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
+
 <attribute>
   <id>ATTR_HTMSC_TTYPEFILT_MASK</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: TTYPE pattern mask.
-                HTM Ttype Filter Control Register (17:23).
-                If set to 1, do not need to match w/ the pattern.
-                If all mask bits are set, no TTYPE pattern/masking is done
-                - Platform is to default to 0x7F
-                - User can change the value using Attribute Override.
+                If mask bit is clear to 0, then do not need to match w/ the pattern.
+                If all mask bits are clear, no TTYPE pattern/masking is done.
+                The inversion of this attribute value will be programmed into
+                bits 17:23 of HTM Ttype Filter Control Register.
   </description>
   <valueType>uint8</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
   <id>ATTR_HTMSC_TSIZEFILT_MASK</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: TSIZE pattern mask.
-                HTM Ttype Filter Control Register (24:31).
-                If set to 1, do not need to match w/ the Pattern.
-                If all mask bits are set, no TSIZE pattern/masking is done
-                - Platform is to default to 0xFF
-                - User can change the value using Attribute Override.
+                If mask bit is clear to 0, then do not need to match w/ the pattern.
+                If all mask bits are clear, no TSIZE pattern/masking is done.
+                The inversion of this attribute value will be programmed into
+                bits 24:31 of HTM Ttype Filter Control Register.
   </description>
   <valueType>uint8</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
+
 <attribute>
   <id>ATTR_HTMSC_TTYPEFILT_INVERT</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: TTYPE/TSIZE Capture Invert.
                 HTM Ttype Filter Control Register (32).
+                This bit controls the inversion of the ttype/tsize filter.
                 0 : Capture record based on ttype/tsize pattern matching
                 1 : Capture record based on ttype/tsize pattern NOT matching
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> MATCH = 0x0, NOT_MATCH = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -138,16 +129,15 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: CRESP Filter Capture Invert.
                 HTM Ttype Filter Control Register (33).
-                0 : Capture record based on cresp filter pattern matching
-                1 : Capture record based on cresp filter pattern NOT matching
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
+                This bit controls the inversion of the cresp filter.
+                0: Capture record based on cresp filter pattern/mask match
+                1: Capture record based on cresp filter pattern/mask NOT matching.
   </description>
   <valueType>uint8</valueType>
   <enum> MATCH = 0x0, NOT_MATCH = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <!-- **************************************************
@@ -173,13 +163,11 @@
                  In OCC trace mode, defines the occ_trace_data(0:22) pattern
                  to match:
                     0:22  occ_trace_data(0:22) pattern.
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint32</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -187,13 +175,11 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: defines the CRESP Filter pattern in FABRIC trace mode.
                 HTM Filter Control Register (27:31).
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -201,16 +187,27 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM FABRIC: Pattern mask.
                 HTM Filter Control Register (32:54).
-                Bits set to 1 in this mask do not need to match w/ the Filter
-                pattern.
-                If all mask bits are set, No pattern matching is done.
-                - Platform is to default to 0x3FFFFF
-                - User can change the value using Attribute Override.
+                Bits clear to 0 in this mask do not need to match with the
+                Filter Pattern.
+                If all bits are clear, no pattern/masking is done and all
+                Cresp/rcmd are captured in Fabric trace mode and all
+                OCC commands are captured in OCC mode.
+                The inversion of this attribute value will be programmed into
+                bits 32:54 of HTM Ttype Filter Control Register.
+                In Fabric Trace Mode:
+                 32:35: rcmd_ttag(0:3) Group ID Mask
+                 36:38: rcmd_ttag(4:6) Chip ID Mask
+                 39:48: rcmd_ttag(7:16) Unit ID Pattern
+                 49:51: rcmd_scope(0:2) Mask
+                 52:53: rcmd_source(0:1) Mask
+                 54in the : PowerBus PORT MASK (for rcmd and cresp filtering0
+                 In OCC Trace Mode
+                 32:54 occ_trace_data(0:22) Mask
   </description>
   <valueType>uint32</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -218,123 +215,244 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM FABRIC: CRESP Filter Mask.
                 HTM Filter Control Register (59:63).
-                Bits set to 1 in this mask do not need to match w/ the CRESP
+                If mask bit is clear to 0, then do not need to match w/ the CRESP
                 Filter pattern.
-                If all mask bits are set, no pattern matching is done
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
+                If all mask bits are clear, no pattern matching is done.
+                The inversion of this attribute value will be programmed into
+                bits 59:63 of HTM Ttype Filter Control Register.
   </description>
   <valueType>uint8</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <!-- **************************************************
         Attributes for HTM Collection Mode Register
      ************************************************** -->
+
+<!-- **** NHTM attributes only *** 
+-->
 <attribute>
-  <id>ATTR_HTMSC_MODE_CONTENT_SEL</id>
+  <id>ATTR_NHTM_HTMSC_MODE_CONTENT_SEL</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: defines the NHTM trace mode.
                 HTM Collection Mode Register (1:2).
-                - Platform is to default to 0x0 (FABRIC)
-                - User can change the value using Attribute Override.
+                Only FABRIC is supported at this time.
   </description>
   <valueType>uint8</valueType>
   <enum> FABRIC = 0x0, EVENT = 0x1, OCC = 0x2 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Nest HTM: defines if the generated data writes are captured.
+                HTM Collection Mode Register (4).
+                0 - Ignore HTM generated data writes
+                1 - Capture even HTM generated writes if they meet the filtering
+                    criteria.
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Nest HTM: defines if the filtering will apply to ttype=PMISC
+                and ttype=Report Hang commands when filtering is enabled.
+                HTM Collection Mode Register (5).
+                0 - filtering ignored on PMISC
+                1 - Apply filtering to PMISC also
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Nest HTM: defines if Precise cresp mode is enabled.
+                0 - Enable precisce cresp mode
+                1 - Disable precisce cresp mode
+  </description>
+  <valueType>uint8</valueType>
+  <enum> ENABLE = 0x0, DISABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Nest HTM: defines Limit Memory Allocation mode.
+                 0 - Pre-allocate maximum memory buffers (NHTM=8)
+                 1 - Pre-allocate only one half maximum memory buffers
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Nest HTM: defines PMISC only Command trace mode.
+                 0 rCmd amd cResp port 0 only goes to NHTM0
+                 1 rCmd and Cresp port 0 is stored alternately to NHTM0 and
+                   NHTM1, switching based for each valid
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
-</attribute>
-
-<attribute>
-  <id>ATTR_HTMSC_MODE_CAPTURE</id>
-  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> Nest HTM: defines capture mode according to trace mode.
-                HTM Collection Mode Register (4:12).
-                When htm_mode_q(1 TO 2) == 00, i.e. FABRIC
-                  456789012
-                  0xxxx0000 : Ignore HTM generated data writes
-                  1xxxx0000 : Capture htm generated data writes
-                  x0xxx0000 : Filtering ignored on PMISC (always trace PMISC and Report Hang)
-                  x1xxx0000 : Filtering applied on ttype = PMISC and ttype = report hang
-                  xx00x0000 : CRESP Mode: Flush CRESP Queue to avoid overrun (default)
-                  xx01x0000 : CRESP Mode: Reserved
-                  xx10x0000 : CRESP Mode: Enable Precise CRESP Mode
-                  xx11x0000 : CRESP Mode: Ignore CRESP
-                  xxxx00000 : Pre-Allocate maximum memory buffers (8)
-                  xxxx10000 : Pre-Allocate fewer memory buffers (4)
-                When htm_mode_q(1 TO 2) == 01, i.e. OTHER
-                  00000xxxx : Pre-Allocate maximum memory buffers (8)
-                  00001xxxx : Pre-Allocate fewer memory buffers (4)
-                  0000xmmmx : mmm for optional external mux control
-                  0000xxxx0 : Both -other- trace buses to NHTM0
-                  0000xxxx1 : Other trace bus0 to nhtm0, trace bus1 to nhtm1. High BW
-                When htm_mode_q(1 TO 2) == 10, i.e. OCC
-                  00000xxx0 : Pre-Allocate maximum memory buffers (8)
-                  00001xxx0 : Pre-Allocate fewer memory buffers (4)
-                  0000xmmm0 : mmm for optional external mux control
-                - Platform is to default to 0x040 (Precise CRESP, 0b001000000)
-                - User can change the value using Attribute Override.
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_SYNC_STAMP_FORCE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Control the number of cycles to wait to force a synchronization
+                stamp or reset the timer.  For NHTM only.
+                HTM Collection Mode Register (19:21).
+  </description>
+  <valueType>uint8</valueType>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_WRITETOIO</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Use space option. For NHTM only.
+                HTM Collection Mode Register (22).
+                0 = Use HTM_CL_Write op to target system memory.
+                    Do pre-allocation sequence. (default)
+                1 = Use ci_pr_st op to target anywhere else.
+                    Dont do pre-allocate sequence.
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<!-- **** CHTM attributes only ***
+-->
+<attribute>
+  <id>ATTR_CHTM_HTMSC_MODE_CONTENT_SEL</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Core HTM: defines the CHTM trace mode.
+                HTM Collection Mode Register (1:2).
+                Only Direct Memory Write mode (IMA) is supported at this time.
+  </description>
+  <valueType>uint8</valueType>
+  <enum> CI = 0x0, LLAT = 0x1, PPE = 0x2, DMW = 0x3 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_CHTM_HTMSC_MODE_CAPTURE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Core HTM: defines capture mode according to trace mode.
+                HTM Collection Mode Register (4:9).
+                When htm_mode_q(1 TO 2) == 00, i.e. Core Instruction Trace
+                  00xxxx : tc_pc_trace_active asserted when HTM_STAT[Tracing]=1 to purge the ERAT when entering and exitting trace
+                  01xxxx : tc_pc_trace_active asserted when HTM_MODE[HTM_Trace_enable]=1 to purge the ERAT only at the beginning
+                When htm_mode_q(1 TO 2) == 01, i.e. LLAT Trace
+                  0xxxxx : capture on assertion of l2_htm_llat_disp_req, i.e. any dispatch request
+                  1xxxxx : capture on assertion of l2_htm_llat_disp_req AND l2_llat_htm_rcdisp_occurred, i.e. only on passed dispatch
+                  x0xxxx : capture on assertion of l2_htm_llat_disp_req, i.e. loads or stores
+                  x1xxxx : capture on assertion of l2_htm_llat_disp_req AND l2_llat_htm_rcdisp_ld_not_st, i.e. only loads
+                  xx0xxx : capture on assertion of l2_llat_htm_pbl3hit_dval
+                  xx1xxx : no capture on assertion of l2_llat_htm_pbl3hit_dval - enable embedded timestamp
+                When htm_mode_q(1 TO 2) == 11, i.e. Direct Memory Write
+                  1xxxxx : Enable HPMC-IMA Mode
   </description>
   <valueType>uint32</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
+  <id>ATTR_CHTM_HTMSC_MODE_CORE_INSTR_STALL</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> For CHTM only.
+                 0: Core execution is stalled whenever the data buffers are almost full to prevent losing records.
+                 1: Core execution is never stalled and entries may be discarded when buffer is full
+  </description>
+  <valueType>uint8</valueType>
+  <enum> ENABLE = 0x0, DISABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<!-- **** Common attributes for both NHTM & CHTM ***
+-->
+<attribute>
   <id>ATTR_HTMSC_MODE_WRAP</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> Nest HTM: Trace Wrap mode.
+  <description> Trace Wrap mode, used for both NHTM and CHTM
                 HTM Collection Mode Register (13).
-                0 = Stop trace when top of Trace Memory is reached
-                1 = Wrap trace to beginning of Trace Memory
-                - Platform is to default to 0x1
-                - User can change the value using Attribute Override.
+                0 = Wrap trace to beginning of Trace Memory
+                1 = Stop trace when top of Trace Memory is reached
   </description>
   <valueType>uint8</valueType>
-  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <enum> ENABLE = 0x0, DISABLE = 0x1</enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
   <id>ATTR_HTMSC_MODE_DIS_TSTAMP</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> Nest HTM: TimeStamp Writes option.
+  <description> TimeStamp Writes option, used for both NHTM and CHTM
                 HTM Collection Mode Register (14).
                 0 = Write of timestamps enabled to indicate elapsed time
                     between records.
                 1 = Timestamps written only to indicate record loss
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> ENABLE = 0x0, DISABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
   <id>ATTR_HTMSC_MODE_SINGLE_TSTAMP</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> Nest HTM: Overflow Timestamps option.
+  <description> Overflow Timestamps option, used for both NHTM and CHTM.
                 HTM Collection Mode Register (15).
                 0 = Timestamp written to indicate elapsed time overflow.
                 1 = Only one timestamp is written between entries, overflow
                     indication is lost
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -345,14 +463,12 @@
                 0 = Normal trace
                 1 = Ignore incoming trace data and save only markers caused
                     by HTM_TRIG writes,
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -364,48 +480,12 @@
                 0 = htm write ops sent with group scope
                 1 = htm write ops sent with Vg scope using programmed
                     target bits.
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
-  </description>
-  <valueType>uint8</valueType>
-  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
-  <writeable/>
-  <persistRuntime/>
-  <platInit/>
-</attribute>
-
-<attribute>
-  <id>ATTR_HTMSC_MODE_SYNC_STAMP_FORCE</id>
-  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> Nest HTM: Control the number of cycles to wait to force a
-                synchronization stamp or reset the timer.
-                HTM Collection Mode Register (19:21).
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
-  </description>
-  <valueType>uint8</valueType>
-  <writeable/>
-  <persistRuntime/>
-  <platInit/>
-</attribute>
-
-<attribute>
-  <id>ATTR_HTMSC_MODE_WRITETOIO</id>
-  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> Nest HTM: Use space option.
-                HTM Collection Mode Register (22).
-                0 = Use HTM_CL_Write op to target system memory.
-                    Do pre-allocation sequence. (default)
-                1 = Use ci_pr_st op to target anywhere else.
-                    Dont do pre-allocate sequence.
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -415,13 +495,11 @@
                 HTM Collection Mode Register (24:39).
                 Vg Target bits should be configured if HTM_MEM[scope] is Vg
                 or if Disable Group Scope=1
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint32</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <!-- ********************************************************
@@ -432,14 +510,12 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Setting of memory scope for HTM collection.
                 HTM Memory Configuration Register (1:3)
-                - Platform is to default to 0x0 (LOCAL).
-                - User can change HTM scope using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> LOCAL = 0x0, NEARNODE = 0x1, GROUP = 0x3, REMOTE = 0x4, VECTORED = 0x5 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -447,21 +523,63 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Setting of memory priority for HTM collection.
                 HTM Memory Configuration Register (4)
-                - Platform is to default to LOW.
-                - User can change MEM_PRIORITY using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> LOW = 0x0, HIGH = 0x1</enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <!-- ********************************************************
         Attributes for HTM Trigger Control Register
      ******************************************************** -->
 <attribute>
-  <id>ATTR_HTMSC_CTRL_TRIG</id>
+  <id>ATTR_NHTM_CTRL_TRIG</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Setting of Trigger control for NHTM.
+                HTM Trigger Control Register (0:1)
+                  00 local triggers are not forwarded to the PowerBus, it is
+                     inserted into the trace when tracing.  Both local and
+                     global triggers control the HTM
+                  01 local triggers are not forwarded to the PowerBus, it is
+                     inserted into the traCe when tracing.  Only local triggers
+                     control the HTM
+                  1x local triggers are forwarded to the PowerBus, it is not
+                     inserted into the trace when tracing.  Only global
+                     triggers control the HTM
+  </description>
+  <valueType>uint8</valueType>
+  <enum> LOCAL_GLOBAL = 0x0, LOCAL = 0x1, GLOBAL = 0x2 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_CTRL_MARK</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Setting of Mark control for NHTM.
+                HTM Trigger Control Register (4:5)
+                00 local markers are not forwarded to the PowerBus.  Both
+                   local and global markers are inserted into the trace
+                01 local markers are not forwarded to the PowerBus.  Only
+                   local markers are inserted into the trace
+                10 local markers are forwarded to the PowerBus.  Only global
+                   markers are inserted into the trace
+                11 local markers are forwarded to the PowerBus.  Markers
+                   are not inserted into the trace (Fabric Trace Mode)
+  </description>
+  <valueType>uint8</valueType>
+  <enum> LOCAL_GLOBAL = 0x0, LOCAL_MARK = 0x1, GLOBAL_MARK = 0x2,
+         NO_MARK = 0x3 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_CHTM_CTRL_TRIG</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Setting of Trigger control.
                 HTM Trigger Control Register (0:1)
@@ -474,18 +592,16 @@
                   1x local triggers are forwarded to the PowerBus, it is not
                      inserted into the trace when tracing.  Only global
                      triggers control the HTM
-                - Platform is to default to 0x1.
-                - User can change MEM_PRIORITY using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> LOCAL_GLOBAL = 0x0, LOCAL = 0x1, GLOBAL = 0x2 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
-  <id>ATTR_HTMSC_CTRL_MARK</id>
+  <id>ATTR_CHTM_CTRL_MARK</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Setting of Mark control.
                 HTM Trigger Control Register (4:5)
@@ -497,16 +613,13 @@
                    markers are inserted into the trace
                 11 local markers are forwarded to the PowerBus.  Markers
                    are not inserted into the trace (Fabric Trace Mode)
-
-                - Platform is to default to 1.
-                - User can change MEM_PRIORITY using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> LOCAL_GLOBAL = 0x0, LOCAL_MARK = 0x1, GLOBAL_MARK = 0x2,
          NO_MARK = 0x3 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -514,14 +627,12 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Enable Stop on PB Chiplet Debug Trigger 0.
                 HTM Trigger Control Register (6)
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -529,14 +640,12 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Enable Stop on PB Chiplet Debug Trigger 1.
                 HTM Trigger Control Register (7)
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -544,14 +653,12 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Enable trace stop on falling edge of PB chiplet trace run.
                 HTM Trigger Control Register (8)
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -559,14 +666,12 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Enable Stop using OCC Control.
                 HTM Trigger Control Register (9)
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -574,14 +679,96 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Enable Stop on chiplet XSTOP.
                 HTM Trigger Control Register (13)
-                - Platform is to default to 0x1
-                - User can change the value using Attribute Override.
+                Platform to default to 0x1
+  </description>
+  <valueType>uint8</valueType>
+  <enum> ENABLE = 0x0, DISABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_HTMSC_CTRL_CHIP0_STOP</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Stop on PC_TC_DBG_Trigger0
+                1 = stop trigger Core Debug Trigger 0
+                0 = ignore Core Debug Trigger  0
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_HTMSC_CTRL_CHIP1_STOP</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Stop on PC_TC_DBG_Trigger1
+                1 = stop trigger Core Debug Trigger 1
+                0 = ignore Core Debug Trigger  1
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_HTMSC_IMA_PDBAR_SPLIT_CORE_MODE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> This bit controls the indexing of the PDBAR address for the
+                starting address of the write to the PDBAR space.
+                For CHTM only.
+                0 'Big Core' mode.
+                1 'Split Core' mode.
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_HTMSC_IMA_PDBAR_SCOPE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>  This register defines the starting Scope of the PowerBus
+                 operation. The Scope will be increased if necessary however
+                 it is more efficient to have the request issued according to
+                 where the target memory is located.
+                     000 LOCAL scope
+                     001 Reserved
+                     010 NEAR NODE scope (Nn)
+                     011 GROUP scope (G).
+                     100 REMOTE scope (Rn).
+                     101 VECTORED group scope (Vg).
+                     110 Reserved
+                     111 Reserved
+                 Note 1: Since P9 uses a Group Class MCD, the HTM will always
+                 force a 'Nodal' scope to 'Group' scope.  If the scope is
+                 initialized to 'Vectored Group Scope', the HTM_MODE[Vg_Target]
+                 bits must also be initialized.
+  </description>
+  <valueType>uint8</valueType>
+  <enum> LOCAL = 0x0, NEARNODE = 0x2, GROUP = 0x3, REMOTE = 0x4, VECTORED = 0x5 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_HTMSC_IMA_PDBAR_ADDR</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>  IMA Write Physical Base Address
+  </description>
+  <valueType>uint64</valueType>
+  <initToZero/>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 </attributes>