p9_htm_setup (L2) - Part 2: HTM setup/reset/start

RTC:138851
Change-Id: Icedf9f1a020948c5515edaf92c9de40897b2ad69
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25689
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25691
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

20 files changed, 3802 insertions, 1172 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C b/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C
index afccf4e5e..6d7cfbdae 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C
@@ -25,7 +25,7 @@
 /// *HWP HWP Owner   : Joe McGill <jmcgill@us.ibm.com>
 /// *HWP FW Owner    : Thi Tran <thi@us.ibm.com>
 /// *HWP Team        : Nest
-/// *HWP Level       : 1
+/// *HWP Level       : 2
 /// *HWP Consumed by : HB
 ///----------------------------------------------------------------------------
 
@@ -49,7 +49,137 @@ fapi2::ReturnCode aduNHTMControl(
 {
     FAPI_DBG("Entering");
     fapi2::ReturnCode l_rc;
+    uint8_t l_num_attempts = 2;
+    bool l_adu_is_dirty = false;
+    uint32_t l_num_polls = 0;
+    bool l_busy_bit_status = false;
+    adu_status_busy_handler l_busy_handling = EXIT_ON_BUSY;
 
+    // validate input action, set ADU operation parameters
+    p9_ADU_oper_flag l_adu_oper_flag;
+
+    // Setup ADU operation
+    l_adu_oper_flag.setOperationType(p9_ADU_oper_flag::PMISC_OPER);
+    l_adu_oper_flag.setTransactionSize(p9_ADU_oper_flag::TSIZE_2);
+
+    // Acquire ADU lock
+    l_rc = p9_adu_coherent_manage_lock( i_target,
+                                        false,
+                                        true,           // Acquire lock
+                                        l_num_attempts);
+
+    if (l_rc)
+    {
+        FAPI_ERR("Error from p9_adu_coherent_manage_lock (acquire all)");
+
+        if (l_adu_is_dirty)
+        {
+            goto adu_reset_unlock;
+        }
+        else
+        {
+            fapi2::current_err = l_rc;
+            goto fapi_try_exit;
+        }
+    }
+
+    // NOTE: lock is now held, if an operation fails from this point
+    //       to the end of the procedure.
+    // Reset lock
+    l_adu_is_dirty = true;
+    // Reset ADU
+    l_rc = p9_adu_coherent_utils_reset_adu(i_target);
+
+    if (l_rc)
+    {
+        FAPI_ERR("Error from p9_adu_coherent_utils_reset_adu (acquire all)");
+        goto adu_reset_unlock;
+    }
+
+    // issue operation
+    l_rc = p9_adu_coherent_setup_adu(i_target,
+                                     i_addr,
+                                     false,      // write
+                                     l_adu_oper_flag.setFlag());
+
+    if (l_rc)
+    {
+        FAPI_ERR("Error from p9_adu_coherent_setup_adu (op)");
+        goto adu_reset_unlock;
+    }
+
+    // Check status
+    // Wait for operation to be completed (busy bit cleared)
+    l_busy_bit_status = false;
+
+    while (l_num_polls < P9_HTM_START_MAX_STATUS_POLLS)
+    {
+        l_rc = p9_adu_coherent_status_check(i_target,
+                                            l_busy_handling,
+                                            true,
+                                            l_busy_bit_status);
+
+        if (l_rc)
+        {
+            FAPI_ERR("p9_adu_coherent_status_check() returns error");
+            break;
+        }
+
+        if (l_busy_bit_status == true)
+        {
+            l_num_polls++;
+
+            // last try, set handler to expect busy bit clear, if not then
+            // p9_adu_coherent_status_check() will log an error so that
+            // we don't have to deal with the error separately here.
+            if (l_num_polls == (P9_HTM_START_MAX_STATUS_POLLS - 1))
+            {
+                l_busy_handling = EXPECTED_BUSY_BIT_CLEAR;
+            }
+        }
+        else
+        {
+            // Operation done, break out
+            break;
+        }
+    }
+
+    // Unlock ADUs
+    FAPI_DBG("Operation complete, releasing lock for all ADU units in drawer");
+    l_rc = p9_adu_coherent_manage_lock(i_target,
+                                       false,
+                                       false, // Release lock
+                                       l_num_attempts);
+
+    if (l_rc)
+    {
+        FAPI_ERR("Error from p9_adu_coherent_manage_lock (release all)");
+        goto adu_reset_unlock;
+    }
+
+    FAPI_DBG("All ADU locks released");
+    // no error for entire operation
+    l_adu_is_dirty = false;
+
+adu_reset_unlock:
+
+    // if error has occurred and any ADU is dirty,
+    // attempt to reset all ADUs and free locks (propogate rc of original fail)
+    if (l_rc && l_adu_is_dirty)
+    {
+        // save original error for return
+        fapi2::current_err = l_rc;
+        FAPI_INF("Attempting to reset/free lock on all ADUs");
+        // Unlock ADUs
+        // ignore return codes
+        l_rc = p9_adu_coherent_utils_reset_adu(i_target);
+        l_rc = p9_adu_coherent_manage_lock(i_target,
+                                           false, // No lock pick
+                                           false, // Lock release
+                                           1);    // Attempt 1 time
+    }
+
+fapi_try_exit:
     FAPI_DBG("Exiting");
     return fapi2::current_err;
 }
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.H b/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.H
index 0b8192200..ca07d082a 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.H
@@ -25,7 +25,7 @@
 /// *HWP HWP Owner   : Joe McGill <jmcgill@us.ibm.com>
 /// *HWP FW Owner    : Thi Tran <thi@us.ibm.com>
 /// *HWP Team        : Nest
-/// *HWP Level       : 1
+/// *HWP Level       : 2
 /// *HWP Consumed by : HB
 /// ----------------------------------------------------------------------------
 
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_def.H b/src/import/chips/p9/procedures/hwp/nest/p9_htm_def.H
index 7188f9082..439c82f05 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_def.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_def.H
@@ -25,7 +25,7 @@
 /// *HWP HWP Owner   : Joe McGill <jmcgill@us.ibm.com>
 /// *HWP FW Owner    : Thi Tran <thi@us.ibm.com>
 /// *HWP Team        : Nest
-/// *HWP Level       : 1
+/// *HWP Level       : 2
 /// *HWP Consumed by : HB
 /// ----------------------------------------------------------------------------
 #ifndef _P9_HTM_DEF_H_
@@ -39,4 +39,78 @@
 #include <p9_quad_scom_addresses.H>
 #include <p9_quad_scom_addresses_fld.H>
 
+//----------------------------------------------------------------------------
+// Constant definitions
+//----------------------------------------------------------------------------
+const uint8_t NUM_NHTM_ENGINES         = 2;
+const uint8_t NUM_CHTM_ENGINES         = 24;
+const uint8_t NUM_CHTM_REG_MAP_INDEX   = 2;
+const uint32_t P9_HTM_CTRL_TIMEOUT_COUNT  = 20;   // HTM control time-out
+
+// HTM operations delay times for HW/sim
+const uint32_t P9_HTM_CTRL_HW_NS_DELAY     = 50000;
+const uint32_t P9_HTM_CTRL_SIM_CYCLE_DELAY = 50000;
+
+// NHTM
+constexpr uint64_t NHTM_modeRegList[NUM_NHTM_ENGINES] =
+{
+    PU_HTM0_HTM_MODE,
+    PU_HTM1_HTM_MODE
+};
+
+// CHTM
+// Note: Absolute HTM_MODE reg addresses
+//       EX_0_HTM_MODE,             // EX0,  core 0      0x10012200
+//       EX_0_HTM_MODE + 0x100,     // EX0,  core 1      0x10012300
+//       EX_1_CHTMLBS0_HTM_MODE,    // EX1,  core 2      0x10012600
+//       EX_1_CHTMLBS1_HTM_MODE,    // EX1,  core 3      0x10012700
+//       EX_2_HTM_MODE,             // EX2,  core 4      0x11012200
+//       EX_2_HTM_MODE + 0x100,     // EX2,  core 5      0x11012300
+//       EX_3_CHTMLBS0_HTM_MODE,    // EX3,  core 6      0x11012600
+//       EX_3_CHTMLBS1_HTM_MODE,    // EX3,  core 7      0x11012700
+//       EX_4_HTM_MODE,             // EX4,  core 8      0x12012200
+//       EX_4_HTM_MODE + 0x100,     // EX4,  core 9      0x12012300
+//       EX_5_CHTMLBS0_HTM_MODE,    // EX5,  core 10     0x12012600
+//       EX_5_CHTMLBS1_HTM_MODE,    // EX5,  core 11     0x12012700
+//       EX_6_HTM_MODE,             // EX6,  core 12     0x13012200
+//       EX_6_HTM_MODE + 0x100,     // EX6,  core 13     0x13012300
+//       EX_7_CHTMLBS0_HTM_MODE,    // EX7,  core 14     0x13012600
+//       EX_7_CHTMLBS1_HTM_MODE,    // EX7,  core 15     0x13012700
+//       EX_8_HTM_MODE,             // EX8,  core 16     0x14012200
+//       EX_8_HTM_MODE + 0x100,     // EX8,  core 17     0x14012300
+//       EX_9_CHTMLBS0_HTM_MODE,    // EX9,  core 18     0x14012600
+//       EX_9_CHTMLBS1_HTM_MODE,    // EX9,  core 19     0x14012700
+//       EX_10_HTM_MODE,            // EX10, core 20     0x15012200
+//       EX_10_HTM_MODE + 0x100,    // EX10, core 21     0x15012300
+//       EX_11_CHTMLBS0_HTM_MODE,   // EX11, core 22     0x15012600
+//       EX_11_CHTMLBS1_HTM_MODE    // EX11, core 23     0x15012700
+//
+// Note: use EX0 to let scom translation getting the absolute address
+//
+constexpr uint64_t CHTM_modeReg[NUM_CHTM_REG_MAP_INDEX] =
+{
+    EX_0_HTM_MODE,             // Any EX core 0
+    EX_0_HTM_MODE + 0x100
+};   // Any EX core 1
+
+//-----------------
+// Register offsets
+//-----------------
+// Register offsets from HTM Collection Mode Register, for NHTM and CHTM
+const uint32_t HTM_MODE = 0x0;
+const uint32_t HTM_MEM  = 0x1;
+const uint32_t HTM_STAT = 0x2;
+const uint32_t HTM_LAST = 0x3;
+const uint32_t HTM_TRIG = 0x4;
+const uint32_t HTM_CTRL = 0x5;
+
+// Register offsets from HTM Collection Mode Register, for NHTM only
+const uint32_t NHTM_FILT       = 0x6;
+const uint32_t NHTM_TTYPE_FILT = 0x7;
+const uint32_t NHTM_CFG        = 0x8;
+
+// Register offsets from HTM Collection Mode Register, for CHTM only
+const uint32_t HTM_IMA_STATUS  = 0x0A;
+const uint32_t CHTM_PDBAR      = 0x0B;
+
 #endif // _P9_HTM_DEF_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_reset.C b/src/import/chips/p9/procedures/hwp/nest/p9_htm_reset.C
index 8e606292e..d436e2f34 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_reset.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_reset.C
@@ -25,7 +25,7 @@
 /// *HWP HWP Owner   : Joe McGill <jmcgill@us.ibm.com>
 /// *HWP FW Owner    : Thi Tran <thi@us.ibm.com>
 /// *HWP Team        : Nest
-/// *HWP Level       : 1
+/// *HWP Level       : 2
 /// *HWP Consumed by : HB
 ///----------------------------------------------------------------------------
 
@@ -36,6 +36,145 @@
 #include <p9_htm_def.H>
 #include <p9_htm_adu_ctrl.H>
 
+//------------------------------------------------------------------------------
+// Constants
+//------------------------------------------------------------------------------
+// ADU PMISC address bit definition
+const uint8_t ADU_ADDRESS_HTM_RESET_BIT = 49;
+
+///
+/// @brief Reset HTM
+///
+/// @param[in] i_target         Reference to target
+/// @param[in] i_pos            Position of HTM engine to reset
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+template<fapi2::TargetType T>
+fapi2::ReturnCode resetHTM(const fapi2::Target<T>& i_target,
+                           const uint8_t i_pos);
+
+/// TARGET_TYPE_PROC_CHIP (NHTM)
+template<>
+fapi2::ReturnCode resetHTM(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const uint8_t i_pos)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData(0);
+    fapi2::buffer<uint64_t> l_scomData_2(0);
+    uint32_t l_htmPendingActionCount = 0;
+
+    // Verify NHTMs are in "Complete" state
+    // NHTM0
+    FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[0] + HTM_STAT, l_scomData),
+             "resetHTM: getScom returns error: Addr "
+             "0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[0] + HTM_STAT,
+             (uint64_t)fapi2::current_err);
+    // NHTM1
+    FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[1] + HTM_STAT, l_scomData_2),
+             "resetHTM: getScom returns error: Addr "
+             "0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[1] + HTM_STAT,
+             (uint64_t)fapi2::current_err);
+
+    FAPI_ASSERT( l_scomData.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_COMPLETE>() &&
+                 l_scomData_2.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_COMPLETE>(),
+                 fapi2::P9_NHTM_CTRL_BAD_STATE()
+                 .set_TARGET(i_target)
+                 .set_HTM_STATUS_REG_NHTM0(l_scomData)
+                 .set_HTM_STATUS_REG_NHTM1(l_scomData_2),
+                 "resetHTM: NHTM is not in Complete state, can't reset "
+                 "NHTM0 status 0x%016llX, NHTM1 status 0x%016llX",
+                 l_scomData, l_scomData_2);
+
+    // Reset
+    l_scomData = 0;
+    l_scomData.flush<0>().setBit<PU_HTM0_HTM_TRIG_HTMSC_RESET>();
+    FAPI_INF("resetHTM: HTM_TRIG reg reset NHTM: 0x%016llX", l_scomData);
+    FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[0] + HTM_TRIG, l_scomData),
+             "resetHTM: putScom returns error: "
+             "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[0] + HTM_TRIG,
+             (uint64_t)fapi2::current_err);
+    FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[1] + HTM_TRIG, l_scomData),
+             "resetHTM: putScom returns error: "
+             "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[1] + HTM_TRIG,
+             (uint64_t)fapi2::current_err);
+
+    l_htmPendingActionCount = 0;
+    FAPI_INF("resetHTM: Waiting for NHTM Ready bit on NHTMs...", i_pos);
+
+    while (l_htmPendingActionCount < P9_HTM_CTRL_TIMEOUT_COUNT)
+    {
+        FAPI_TRY(fapi2::delay(P9_HTM_CTRL_HW_NS_DELAY,
+                              P9_HTM_CTRL_SIM_CYCLE_DELAY),
+                 "resetHTM: fapi delay returns an error, l_rc 0x%.8X",
+                 (uint64_t)fapi2::current_err);
+
+        // Check ready bit
+        FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[0] + HTM_STAT, l_scomData),
+                 "resetHTM: getScom returns error: "
+                 "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[0] + HTM_STAT,
+                 (uint64_t)fapi2::current_err);
+
+        FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[1] + HTM_STAT, l_scomData_2),
+                 "resetHTM: getScom returns error: "
+                 "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[1] + HTM_STAT,
+                 (uint64_t)fapi2::current_err);
+
+        if ( l_scomData.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_READY>() &&
+             l_scomData_2.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_READY>() )
+        {
+            FAPI_INF("resetHTM: NHTM status = Ready on both NHTMs.");
+            break;
+        }
+
+        // "Ready" is not asserted yet; increment timeout and check again
+        l_htmPendingActionCount++;
+    }
+
+    // Error out if Ready bit is not set after reset
+    FAPI_ASSERT( (l_htmPendingActionCount < P9_HTM_CTRL_TIMEOUT_COUNT),
+                 fapi2::P9_NHTM_CTRL_TIMEOUT()
+                 .set_TARGET(i_target)
+                 .set_DELAY_COUNT(l_htmPendingActionCount)
+                 .set_HTM_STATUS_REG_NHTM0(l_scomData)
+                 .set_HTM_STATUS_REG_NHTM1(l_scomData_2),
+                 "resetHTM: Timeout waiting for Ready bit after reset, Count 0x%.8X, "
+                 "NHTM0 status 0x%016llX, NHTM1 status 0x%016llX",
+                 l_htmPendingActionCount, l_scomData, l_scomData_2);
+
+#if 0
+    // Note:
+    // Save this code in case we want to perform reset via ADU
+    // Build address value
+    l_scomData.flush<0>().setBit<ADU_ADDRESS_HTM_RESET_BIT>();
+
+    // Reset global trigger on the NHTM engines
+    FAPI_TRY(aduNHTMControl(i_target, l_scomData),
+             "resetHTM: aduNHTMControl returns error.");
+#endif
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+/// TARGET_TYPE_CORE (CHTM)
+template<>
+fapi2::ReturnCode resetHTM(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
+                           const uint8_t i_pos)
+
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+
+    // TODO: Need to find out what to do to reset IMA trace.
+
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
 extern "C" {
 
 ///
@@ -47,7 +186,50 @@ extern "C" {
     {
         FAPI_DBG("Entering");
         fapi2::ReturnCode l_rc;
+        uint8_t l_corePos = 0;
+        auto l_modeRegList = std::vector<uint64_t>();
+        auto l_coreChiplets = i_target.getChildren<fapi2::TARGET_TYPE_CORE>();
+
+        uint8_t l_nhtmType;
+        uint8_t l_chtmType[NUM_CHTM_ENGINES];
+
+        // Get ATTR_NHTM_TRACE_TYPE
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_TRACE_TYPE, i_target, l_nhtmType),
+                 "p9_htm_reset: Error getting ATTR_NHTM_TRACE_TYPE, l_rc 0x%.8X",
+                 (uint64_t)fapi2::current_err);
+
+        // Get ATTR_CHTM_TRACE_TYPE
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHTM_TRACE_TYPE, i_target,
+                               l_chtmType),
+                 "p9_htm_reset: Error getting ATTR_CHTM_TRACE_TYPE, l_rc 0x%.8X",
+                 (uint64_t)fapi2::current_err);
+
+        // Reset NHTM trace
+        // Note: reset NHTM0 will also reset NHTM1 in global mode
+        if (l_nhtmType != fapi2::ENUM_ATTR_NHTM_TRACE_TYPE_DISABLE)
+        {
+            FAPI_TRY( resetHTM(i_target, 0),
+                      "p9_htm_reset: resetHTM() returns error NHTM"
+                      "l_rc 0x%.8X", (uint64_t)fapi2::current_err );
+        }
+
+        // Reset CHTM
+        for (auto l_core : l_coreChiplets)
+        {
+            // Get the core position
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_core, l_corePos),
+                     "Error getting ATTR_CHIP_UNIT_POS");
+            FAPI_DBG("Reset HTM on core %u....", l_corePos);
+
+            if (l_chtmType[l_corePos] != fapi2::ENUM_ATTR_CHTM_TRACE_TYPE_DISABLE)
+            {
+                FAPI_TRY(resetHTM(l_core, l_corePos),
+                         "p9_htm_reset: resetHTM() returns error: CHTM %u, "
+                         "l_rc 0x%.8X", l_corePos, (uint64_t)fapi2::current_err );
+            }
+        }
 
+    fapi_try_exit:
         FAPI_DBG("Exiting");
         return fapi2::current_err;
     }
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_reset.H b/src/import/chips/p9/procedures/hwp/nest/p9_htm_reset.H
index 683f8b4ef..717f3e57f 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_reset.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_reset.H
@@ -25,7 +25,7 @@
 /// *HWP HWP Owner   : Joe McGill <jmcgill@us.ibm.com>
 /// *HWP FW Owner    : Thi Tran <thi@us.ibm.com>
 /// *HWP Team        : Nest
-/// *HWP Level       : 1
+/// *HWP Level       : 2
 /// *HWP Consumed by : HB
 /// ----------------------------------------------------------------------------
 
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_htm_setup.C
index a893ef318..351bf800f 100755
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_setup.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_setup.C
@@ -16,6 +16,23 @@
 /* deposited with the U.S. Copyright Office.                              */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: chips/p9/procedures/hwp/nest/p9_htm_setup.C $                 */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2015,2016                                                    */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
 ///----------------------------------------------------------------------------
 /// @file  p9_htm_setup.C
 ///
@@ -29,7 +46,7 @@
 /// *HWP HWP Owner   : Joe McGill <jmcgill@us.ibm.com>
 /// *HWP FW Owner    : Thi Tran <thi@us.ibm.com>
 /// *HWP Team        : Nest
-/// *HWP Level       : 1
+/// *HWP Level       : 2
 /// *HWP Consumed by : HB
 ///----------------------------------------------------------------------------
 
@@ -37,24 +54,1395 @@
 // Includes
 //------------------------------------------------------------------------------
 #include <p9_htm_setup.H>
+#include <p9_htm_def.H>
+#include <p9_htm_start.H>
+#include <p9_htm_reset.H>
 
-extern "C" {
-
+///----------------------------------------------------------------------------
+/// Constants
+///----------------------------------------------------------------------------
+const uint64_t IMA_EVENT_MASK_VALUE                            = 0x0004008000000000;
+const uint8_t NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL_BIT    = 5;
+const uint8_t NHTM_HTMSC_MODE_CAPTURE_CRESP_MODE_BIT_START     = 6;
+const uint8_t NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION_BIT = 8;
 
 ///----------------------------------------------------------------------------
-/// Function definitions
+/// Struct HTM_CTRL_attrs_t
 ///----------------------------------------------------------------------------
+///
+/// @struct HTM_CTRL_attrs_t
+/// Contains processor chip attribute values that are needed to perform
+/// the setup of HTM_CTRL register.
+/// The attributes are common for both NHTM and CHTM traces.
+///
+struct HTM_CTRL_attrs_t
+{
+    ///
+    /// @brief getAttrs
+    /// Function that reads all attributes needed to program HTM_CTRL reg.
+    ///
+    /// @param[in] i_target    Reference to processor chip target
+    ///
+    /// @return FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    fapi2::ReturnCode getAttrs(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+    // --------------------------------------
+    // Attributes to setup HTM_CTRL reg
+    // --------------------------------------
+    uint8_t    iv_nhtmCtrlTrig;            // ATTR_NHTM_CTRL_TRIG
+    uint8_t    iv_nhtmCtrlMark;            // ATTR_NHTM_CTRL_MARK
+    uint8_t    iv_chtmCtrlTrig;            // ATTR_CHTM_CTRL_TRIG
+    uint8_t    iv_chtmCtrlMark;            // ATTR_CHTM_CTRL_MARK
+    uint8_t    iv_ctrlDbg0Stop;            // ATTR_HTMSC_CTRL_DBG0_STOP
+    uint8_t    iv_ctrlDbg1Stop;            // ATTR_HTMSC_CTRL_DBG1_STOP
+    uint8_t    iv_ctrlRunStop;             // ATTR_HTMSC_CTRL_RUN_STOP
+    uint8_t    iv_ctrlOtherDbg0Stop;       // ATTR_HTMSC_CTRL_OTHER_DBG0_STOP (NHTM only)
+    uint8_t    iv_ctrlXstopStop;           // ATTR_HTMSC_CTRL_XSTOP_STOP
+    uint8_t    iv_ctrlChip0Stop;           // ATTR_HTMSC_CTRL_CHIP0_STOP (CHTM only)
+    uint8_t    iv_ctrlChip1Stop;           // ATTR_HTMSC_CTRL_CHIP1_STOP (CHTM only)
+};
+
+// See doxygen in struct definition.
+fapi2::ReturnCode HTM_CTRL_attrs_t::getAttrs(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+
+    // ATTR_NTMSC_CTRL_TRIG
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_CTRL_TRIG, i_target, iv_nhtmCtrlTrig),
+             "getAttrs: Error getting ATTR_HTMSC_CTRL_TRIG, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // ATTR_NTMSC_CTRL_MARK
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_CTRL_MARK, i_target, iv_nhtmCtrlMark),
+             "getAttrs: Error getting ATTR_HTMSC_CTRL_MARK, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // ATTR_CHTM_CTRL_MARK
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHTM_CTRL_TRIG, i_target, iv_chtmCtrlTrig),
+             "getAttrs: Error getting ATTR_HTMSC_CTRL_TRIG, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // ATTR_NTMSC_CTRL_MARK
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHTM_CTRL_MARK, i_target, iv_chtmCtrlMark),
+             "getAttrs: Error getting ATTR_HTMSC_CTRL_MARK, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // ATTR_HTMSC_CTRL_DBG0_STOP
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_CTRL_DBG0_STOP, i_target,
+                           iv_ctrlDbg0Stop),
+             "getAttrs: Error getting ATTR_HTMSC_CTRL_DBG0_STOP, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // ATTR_HTMSC_CTRL_DBG1_STOP
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_CTRL_DBG1_STOP, i_target,
+                           iv_ctrlDbg1Stop),
+             "getAttrs: Error getting ATTR_HTMSC_CTRL_DBG1_STOP, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // ATTR_HTMSC_CTRL_RUN_STOP
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_CTRL_RUN_STOP, i_target,
+                           iv_ctrlRunStop),
+             "getAttrs: Error getting ATTR_HTMSC_CTRL_RUN_STOP, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // ATTR_HTMSC_CTRL_OTHER_DBG0_STOP (NHTM)
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_CTRL_OTHER_DBG0_STOP, i_target,
+                           iv_ctrlOtherDbg0Stop),
+             "getAttrs: Error getting ATTR_HTMSC_CTRL_OTHER_DBG0_STOP, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // ATTR_HTMSC_CTRL_XSTOP_STOP
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_CTRL_XSTOP_STOP, i_target,
+                           iv_ctrlXstopStop),
+             "getAttrs: Error getting ATTR_HTMSC_CTRL_XSTOP_STOP, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // ATTR_HTMSC_CTRL_CHIP0_STOP (CHTM)
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_CTRL_CHIP0_STOP, i_target,
+                           iv_ctrlChip0Stop),
+             "getAttrs: Error getting ATTR_HTMSC_CTRL_CHIP0_STOP, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // ATTR_HTMSC_CTRL_CHIP1_STOP (CHTM)
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_CTRL_CHIP1_STOP, i_target,
+                           iv_ctrlChip1Stop),
+             "getAttrs: Error getting ATTR_HTMSC_CTRL_CHIP1_STOP, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // Display generic HTM_CTRL attributes
+    FAPI_DBG("  ATTR_NHTM_CTRL_TRIG            0x%.8X", iv_nhtmCtrlTrig);
+    FAPI_DBG("  ATTR_NHTM_CTRL_MARK            0x%.8X", iv_nhtmCtrlMark);
+    FAPI_DBG("  ATTR_CHTM_CTRL_TRIG            0x%.8X", iv_chtmCtrlTrig);
+    FAPI_DBG("  ATTR_CHTM_CTRL_MARK            0x%.8X", iv_chtmCtrlMark);
+    FAPI_DBG("  ATTR_HTMSC_CTRL_DBG0_STOP       0x%.8X", iv_ctrlDbg0Stop);
+    FAPI_DBG("  ATTR_HTMSC_CTRL_DBG1_STOP       0x%.8X", iv_ctrlDbg1Stop);
+    FAPI_DBG("  ATTR_HTMSC_CTRL_RUN_STOP        0x%.8X", iv_ctrlRunStop);
+    FAPI_DBG("  ATTR_HTMSC_CTRL_OTHER_DBG0_STOP 0x%.8X", iv_ctrlOtherDbg0Stop);
+    FAPI_DBG("  ATTR_HTMSC_CTRL_XSTOP_STOP      0x%.8X", iv_ctrlXstopStop);
+    FAPI_DBG("  ATTR_HTMSC_CTRL_CHIP0_STOP      0x%.8X", iv_ctrlChip0Stop);
+    FAPI_DBG("  ATTR_HTMSC_CTRL_CHIP1_STOP      0x%.8X", iv_ctrlChip1Stop);
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+
+///
+/// @brief This function sets up CHTM_PDBAR reg for CHTM.
+///
+/// @param[in] i_target    Reference to core target
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode setup_CHTM_PDBAR(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData(0);
+    uint8_t l_uint8_attr = 0;
+    uint64_t l_uint64_attr = 0;
+    uint8_t l_pos = 0;
+
+    // Get the proc target to read attribute settings
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_proc =
+        i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+
+    // Get the EX parent of this core to program the register
+    fapi2::Target<fapi2::TARGET_TYPE_EX> l_ex =
+        i_target.getParent<fapi2::TARGET_TYPE_EX>();
+
+    // Get this core's position
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target, l_pos),
+             "Error getting ATTR_CHIP_UNIT_POS");
+
+    // --------------------------------------
+    // Attributes to setup CHTM_PDBAR reg
+    // --------------------------------------
+
+    // ATTR_HTMSC_IMA_PDBAR_SPLIT_CORE_MODE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_IMA_PDBAR_SPLIT_CORE_MODE, l_proc,
+                           l_uint8_attr),
+             "setup_CHTM_PDBAR: Error getting ATTR_HTMSC_IMA_PDBAR_SPLIT_CORE_MODE, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_IMA_PDBAR_SPLIT_CORE_MODE 0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_IMA_PDBAR_SPLIT_CORE_MODE_DISABLE) ?
+    l_scomData.clearBit<EX_HTM_IMA_PDBAR_HTMSC_ENABLE_SPLIT_CORE>() :
+    l_scomData.setBit<EX_HTM_IMA_PDBAR_HTMSC_ENABLE_SPLIT_CORE>();
+
+    // ATTR_HTMSC_IMA_PDBAR_SCOPE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_IMA_PDBAR_SCOPE, l_proc,
+                           l_uint8_attr),
+             "setup_CHTM_PDBAR: Error getting ATTR_HTMSC_IMA_PDBAR_SCOPE, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_IMA_PDBAR_SCOPE 0x%.8X", l_uint8_attr);
+    l_scomData.insertFromRight<EX_HTM_IMA_PDBAR_HTMSC_SCOPE,
+                               EX_HTM_IMA_PDBAR_HTMSC_SCOPE_LEN>
+                               (l_uint8_attr);
+
+    // ATTR_HTMSC_IMA_PDBAR_ADDR
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_IMA_PDBAR_ADDR, l_proc,
+                           l_uint64_attr),
+             "setup_CHTM_PDBAR: Error getting ATTR_HTMSC_IMA_PDBAR_ADDR, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_IMA_PDBAR_ADDR 0x%.16llX", l_uint64_attr);
+    // Bits 8:50
+    l_scomData.insert<EX_HTM_IMA_PDBAR_HTMSC, EX_HTM_IMA_PDBAR_HTMSC_LEN,
+                      EX_HTM_IMA_PDBAR_HTMSC>(l_uint64_attr);
+
+    // Display CHTM_PDBAR reg setup value
+    FAPI_INF("setupChtm: CHTM_PDBAR reg setup: 0x%016llX", l_scomData);
+
+    // Write HW
+    FAPI_TRY(fapi2::putScom(l_ex,  CHTM_modeReg[l_pos % 2] + CHTM_PDBAR,
+                            l_scomData),
+             "setupChtm: putScom returns error: Addr 0x%016llX, l_rc 0x%.8X",
+             CHTM_modeReg[l_pos % 2] + CHTM_PDBAR,  (uint64_t)fapi2::current_err);
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+
+///
+/// @brief This function sets up IMA_EVENT_MASK reg for CHTM.
+///
+/// @param[in] i_target    Reference to core target
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode setup_IMA_EVENT_MASK(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData(IMA_EVENT_MASK_VALUE);
+    uint8_t l_pos = 0;
+
+    // Get the EX parent of this core to program the register
+    fapi2::Target<fapi2::TARGET_TYPE_EX> l_ex =
+        i_target.getParent<fapi2::TARGET_TYPE_EX>();
+
+    // Get this core's position
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target, l_pos),
+             "Error getting ATTR_CHIP_UNIT_POS");
+
+    // Display IMA_EVENT_MASK reg setup value
+    FAPI_INF("setupChtm: IMA_EVENT_MASK reg setup: 0x%016llX", l_scomData);
+
+    // Write HW
+    FAPI_TRY(fapi2::putScom(l_ex, EX_IMA_EVENT_MASK, l_scomData),
+             "setup_IMA_EVENT_MASK: putScom returns error: Addr 0x%016llX, l_rc 0x%.8X",
+             EX_IMA_EVENT_MASK,  (uint64_t)fapi2::current_err);
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+///
+/// @brief This function sets up the NHTM_FILT based on attribute settings.
+///
+/// @param[in] i_target    Reference to processor chip target
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode setup_NHTM_FILT(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData(0);
+    uint8_t l_uint8_attr = 0;
+    uint32_t l_uint32_attr = 0;
+
+    // Setup data value to program NHTM_FILT reg
+
+    // ATTR_HTMSC_FILT_PAT
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_FILT_PAT, i_target,
+                           l_uint32_attr),
+             "setup_NHTM_FILT: Error getting ATTR_HTMSC_FILT_PAT, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_FILT_PAT        0x%.8X", l_uint32_attr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_FILT_HTMSC_PAT,
+                               PU_HTM0_HTM_FILT_HTMSC_PAT_LEN>
+                               (l_uint32_attr);
+
+    // ATTR_HTMSC_FILT_CRESP_PAT
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_FILT_CRESP_PAT, i_target,
+                           l_uint8_attr),
+             "setup_NHTM_FILT: Error getting ATTR_HTMSC_FILT_CRESP_PAT, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_FILT_CRESP_PAT  0x%.8X", l_uint8_attr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_FILT_HTMSC_CRESP_PAT,
+                               PU_HTM0_HTM_FILT_HTMSC_CRESP_PAT_LEN>
+                               (l_uint8_attr);
+
+    // ATTR_HTMSC_FILT_MASK
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_FILT_MASK, i_target,
+                           l_uint32_attr),
+             "setup_NHTM_FILT: Error getting ATTR_HTMSC_FILT_MASK, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_FILT_MASK       0x%.8X", l_uint32_attr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_FILT_HTMSC_MASK,
+                               PU_HTM0_HTM_FILT_HTMSC_MASK_LEN>
+                               (~l_uint32_attr);
+
+    // ATTR_HTMSC_FILT_CRESP_MASK
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_FILT_CRESP_MASK, i_target,
+                           l_uint8_attr),
+             "setup_NHTM_FILT: Error getting ATTR_HTMSC_FILT_CRESP_MASK, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_FILT_CRESP_MASK 0x%.8X", l_uint8_attr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_FILT_HTMSC_CRESP_MASK,
+                               PU_HTM0_HTM_FILT_HTMSC_CRESP_MASK_LEN>
+                               (~l_uint8_attr);
+
+    // Display NHTM_FILT reg setup value
+    FAPI_INF("setup_NHTM_FILT: NHTM_FILT reg setup: 0x%016llX",
+             l_scomData);
+
+    // Write HW, program both NHTM0 and NHTM1
+    for (uint8_t ii = 0; ii < NUM_NHTM_ENGINES; ii++)
+    {
+        FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[ii] + NHTM_FILT,
+                                l_scomData),
+                 "setup_NHTM_FILT: putScom returns error: Addr 0x%016llX, "
+                 "l_rc 0x%.8X", NHTM_modeRegList[ii] + NHTM_FILT,
+                 (uint64_t)fapi2::current_err);
+    }
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+
+///
+/// @brief This function sets up the NHTM_TTYPE_FILT based on attribute settings.
+///        It's used on FABRIC trace type only.
+///
+/// @param[in] i_target    Reference to processor chip target
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode setup_NHTM_TTYPE_FILT(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData(0);
+    uint8_t l_uint8_attr = 0;
+
+    // Setup data value to program NHTM_TTYPE_FILT reg
+
+    // ATTR_HTMSC_TTYPEFILT_PAT
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_TTYPEFILT_PAT, i_target,
+                           l_uint8_attr),
+             "setup_NHTM_TTYPE_FILT: Error getting ATTR_HTMSC_TTYPEFILT_PAT, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_TTYPEFILT_PAT        0x%.8X", l_uint8_attr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_TTYPEFILT_HTMSC_PAT,
+                               PU_HTM0_HTM_TTYPEFILT_HTMSC_PAT_LEN>
+                               (l_uint8_attr);
+
+    // ATTR_HTMSC_TSIZEFILT_PAT
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_TSIZEFILT_PAT, i_target,
+                           l_uint8_attr),
+             "setup_NHTM_TTYPE_FILT: Error getting ATTR_HTMSC_TSIZEFILT_PAT, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_TSIZEFILT_PAT        0x%.8X", l_uint8_attr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT,
+                               PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT_LEN>
+                               (l_uint8_attr);
+
+    // Set ATTR_HTMSC_TTYPEFILT_MASK
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_TTYPEFILT_MASK, i_target,
+                           l_uint8_attr),
+             "setup_NHTM_TTYPE_FILT: Error getting ATTR_HTMSC_TTYPEFILT_MASK, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_TTYPEFILT_MASK       0x%.8X", l_uint8_attr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_TTYPEFILT_HTMSC_MASK,
+                               PU_HTM0_HTM_TTYPEFILT_HTMSC_MASK_LEN>
+                               (~l_uint8_attr);
+
+    // ATTR_HTMSC_TSIZEFILT_MASK
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_TSIZEFILT_MASK, i_target,
+                           l_uint8_attr),
+             "setup_NHTM_TTYPE_FILT: Error getting ATTR_HTMSC_TSIZEFILT_MASK, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_TSIZEFILT_MASK       0x%.8X", l_uint8_attr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK,
+                               PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK_LEN>
+                               (~l_uint8_attr);
+
+    // ATTR_HTMSC_TTYPEFILT_INVERT
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_TTYPEFILT_INVERT, i_target,
+                           l_uint8_attr),
+             "setup_NHTM_TTYPE_FILT: Error getting ATTR_HTMSC_TTYPEFILT_INVERT, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_TTYPEFILT_INVERT     0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_TTYPEFILT_INVERT_MATCH) ?
+    l_scomData.clearBit<PU_HTM0_HTM_TTYPEFILT_HTMSC_INVERT>() :
+    l_scomData.setBit<PU_HTM0_HTM_TTYPEFILT_HTMSC_INVERT>();
+
+    // ATTR_HTMSC_CRESPFILT_INVERT
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_CRESPFILT_INVERT, i_target,
+                           l_uint8_attr),
+             "setup_NHTM_TTYPE_FILT: Error getting ATTR_HTMSC_CRESPFILT_INVERT, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_CRESPFILT_INVERT     0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_CRESPFILT_INVERT_MATCH) ?
+    l_scomData.clearBit<PU_HTM0_HTM_TTYPEFILT_HTMSC_CRESPFILT_INVERT>() :
+    l_scomData.setBit<PU_HTM0_HTM_TTYPEFILT_HTMSC_CRESPFILT_INVERT>();
+
+    // Display NHTM_TTYPE_FILT reg setup value
+    FAPI_INF("setupNhtm: NHTM_TTYPE_FILT reg setup: 0x%016llX", l_scomData);
+
+    // Write HW, program both NHTM0 and NHTM1
+    for (uint8_t ii = 0; ii < NUM_NHTM_ENGINES; ii++)
+    {
+        FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[ii] + NHTM_TTYPE_FILT,
+                                l_scomData),
+                 "setup_NHTM_TTYPE_FILT: putScom returns error: Addr 0x%016llX, "
+                 "l_rc 0x%.8X", NHTM_modeRegList[ii] + NHTM_TTYPE_FILT,
+                 (uint64_t)fapi2::current_err);
+    }
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+///
+/// @brief This function sets up the HTM_CTRL register.
+///
+/// @tparam T template parameter, passed in target.
+/// @param[in] i_target            Reference to HW target
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+template<fapi2::TargetType T>
+fapi2::ReturnCode setup_HTM_CTRL(const fapi2::Target<T>& i_target);
+
+///
+/// TARGET_TYPE_PROC_CHIP (NHTM trace)
+///
+template<>
+fapi2::ReturnCode setup_HTM_CTRL(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData(0);
+    HTM_CTRL_attrs_t l_HTM_CTRL;
+
+    // Setup data value to program HTM_CTRL reg
+    // Note: Register bit definitions are the same for both NHTM0 and NHTM1
+
+    // Get the proc attributes needed to perform HTM_CTRL setup
+    FAPI_TRY(l_HTM_CTRL.getAttrs(i_target),
+             "l_HTM_CTRL.getAttrs() returns an error, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // Set CTRL_TRIG
+    l_scomData.insertFromRight <PU_HTM0_HTM_CTRL_HTMSC_TRIG,
+                               PU_HTM0_HTM_CTRL_HTMSC_TRIG_LEN>
+                               (l_HTM_CTRL.iv_nhtmCtrlTrig);
+
+    // Set CTRL_MARK
+    l_scomData.insertFromRight <PU_HTM0_HTM_CTRL_HTMSC_MARK,
+                               PU_HTM0_HTM_CTRL_HTMSC_MARK_LEN>
+                               (l_HTM_CTRL.iv_nhtmCtrlMark);
+
+    // Set CTRL_DBG0_STOP
+    (l_HTM_CTRL.iv_ctrlDbg0Stop == fapi2::ENUM_ATTR_HTMSC_CTRL_DBG0_STOP_DISABLE) ?
+    l_scomData.clearBit<PU_HTM0_HTM_CTRL_HTMSC_DBG0_STOP>() :
+    l_scomData.setBit<PU_HTM0_HTM_CTRL_HTMSC_DBG0_STOP>();
+
+    // Set CTRL_DBG1_STOP
+    (l_HTM_CTRL.iv_ctrlDbg1Stop == fapi2::ENUM_ATTR_HTMSC_CTRL_DBG1_STOP_DISABLE) ?
+    l_scomData.clearBit<PU_HTM0_HTM_CTRL_HTMSC_DBG1_STOP>() :
+    l_scomData.setBit<PU_HTM0_HTM_CTRL_HTMSC_DBG1_STOP>();
+
+    // Set CTRL_RUN_STOP
+    (l_HTM_CTRL.iv_ctrlRunStop == fapi2::ENUM_ATTR_HTMSC_CTRL_RUN_STOP_DISABLE) ?
+    l_scomData.clearBit<PU_HTM0_HTM_CTRL_HTMSC_RUN_STOP>() :
+    l_scomData.setBit<PU_HTM0_HTM_CTRL_HTMSC_RUN_STOP>();
+
+    // Set CTRL_OTHER_DBG0_STOP
+    (l_HTM_CTRL.iv_ctrlOtherDbg0Stop == fapi2::ENUM_ATTR_HTMSC_CTRL_OTHER_DBG0_STOP_DISABLE) ?
+    l_scomData.clearBit<PU_HTM0_HTM_CTRL_HTMSC_OTHER_DBG0_STOP>() :
+    l_scomData.setBit<PU_HTM0_HTM_CTRL_HTMSC_OTHER_DBG0_STOP>();
+
+    // Set CTRL_XSTOP_STOP
+    (l_HTM_CTRL.iv_ctrlXstopStop == fapi2::ENUM_ATTR_HTMSC_CTRL_XSTOP_STOP_DISABLE) ?
+    l_scomData.clearBit<PU_HTM0_HTM_CTRL_HTMSC_XSTOP_STOP>() :
+    l_scomData.setBit<PU_HTM0_HTM_CTRL_HTMSC_XSTOP_STOP>();
+
+    // Display HTM_CTRL reg setup value
+    FAPI_INF("setup_HTM_CTRL: HTM_CTRL reg setup: 0x%016llX", l_scomData);
+
+    // Write data to HTM_CTRL
+    // Program both NHTM0 and NHTM1
+    for (uint8_t ii = 0; ii < NUM_NHTM_ENGINES; ii++)
+    {
+        FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[ii] + HTM_CTRL,
+                                l_scomData),
+                 "setup_HTM_CTRL: putScom returns error: Addr 0x%016llX, "
+                 "l_rc 0x%.8X", NHTM_modeRegList[ii],
+                 (uint64_t)fapi2::current_err);
+    }
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+///
+/// TARGET_TYPE_CORE (CHTM trace)
+///
+template<>
+fapi2::ReturnCode setup_HTM_CTRL(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+
+    // For IMA trace, no need to program HTM_CTRL.
+    // Place holder for other CHTM trace setup when they are suppored.
+
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+///
+/// @brief getMemSmallSize
+/// Utility function that returns the Trace Memory Size setting for
+/// HTM_MEM register based on input HTM trace size.
+///
+/// @param[in]  i_size      HTM trace size
+/// @param[out] o_htmSize   Trace memory size value
+/// @param[out] o_smallSize Trace memory size small value
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode getTraceMemSizeValues(const uint64_t i_size,
+                                        htm_size_t& o_htmSize,
+                                        bool& o_smallSize)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+
+    switch (i_size)
+    {
+        // Note: NTHM and CHTM have the same size definitions.
+        //       Use NHTM enum values here for both case.
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_16_MB:
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_512_MB:
+            o_htmSize = HTM_512M_OR_16M;
+            break;
+
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_32_MB:
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_1_GB:
+            o_htmSize = HTM_1G_OR_32M;
+            break;
+
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_64_MB:
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_2_GB:
+            o_htmSize = HTM_2G_OR_64M;
+            break;
+
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_128_MB:
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_4_GB:
+            o_htmSize = HTM_4G_OR_128M;
+            break;
+
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_256_MB:
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_8_GB:
+            o_htmSize = HTM_8G_OR_256M;
+            break;
+
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_16_GB:
+            o_htmSize = HTM_16G_OR_512M;
+            break;
+
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_32_GB:
+            o_htmSize = HTM_32G_OR_1G;
+            break;
+
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_64_GB:
+            o_htmSize = HTM_64G_OR_2G;
+            break;
+
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_128_GB:
+            o_htmSize = HTM_128G_OR_4G;
+            break;
+
+        case fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_256_GB:
+            o_htmSize = HTM_256G_OR_8G;
+            break;
+
+        default:
+            FAPI_ASSERT(false,
+                        fapi2::HTM_SETUP_PROC_BAR_SIZE()
+                        .set_PROC_BAR_SIZE(i_size),
+                        "getAttrs: Invalid proc BAR size value: "
+                        "0x%016llX", i_size);
+            break;
+    }
+
+    // If memsize >= 512MB, set small memory size to false
+    if (i_size >= fapi2::ENUM_ATTR_PROC_NHTM_BAR_SIZE_512_MB)
+    {
+        o_smallSize = false;
+    }
+    else
+    {
+        o_smallSize = true;
+    }
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+///
+/// @brief This function sets up the HTM_MEM register.
+///
+/// @tparam T template parameter, passed in target.
+/// @param[in] i_target            Reference to HW target
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+template<fapi2::TargetType T>
+fapi2::ReturnCode setup_HTM_MEM(const fapi2::Target<T>& i_target);
+
+///
+/// TARGET_TYPE_PROC_CHIP (NHTM trace)
+///
+template<>
+fapi2::ReturnCode setup_HTM_MEM(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData;
+    uint8_t l_uint8_attr = 0;
+    htm_size_t l_barHtmSize;
+    bool l_smallSize;
+    uint64_t l_barAddr;
+    uint64_t l_barSize;
+
+    // Setup data value to program HTM_MEM reg
+    // Note: Register bit definitions are the same for both NHTM0 and NHTM1
+
+    // ATTR_PROC_NHTM_BAR_BASE_ADDR
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NHTM_BAR_BASE_ADDR, i_target,
+                           l_barAddr),
+             "setup_HTM_MEM: Error getting ATTR_PROC_NHTM_BAR_BASE_ADDR, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+
+    // ATTR_PROC_NHTM_BAR_SIZES
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NHTM_BAR_SIZE, i_target,
+                           l_barSize),
+             "setup_HTM_MEM: Error getting ATTR_PROC_NHTM_BAR_SIZE, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+
+    l_scomData = 0;
+
+    // ATTR_HTMSC_MEM_SCOPE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MEM_SCOPE, i_target, l_uint8_attr),
+             "setup_HTM_MEM: Error getting ATTR_HTMSC_MEM_SCOPE, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MEM_SCOPE            0x%.8X", l_uint8_attr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_MEM_HTMSC_SCOPE,
+                               PU_HTM0_HTM_MEM_HTMSC_SCOPE_LEN>
+                               (l_uint8_attr);
+
+    // ATTR_HTMSC_MEM_PRIORITY
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MEM_PRIORITY, i_target, l_uint8_attr),
+             "setup_HTM_MEM: Error getting ATTR_HTMSC_MEM_PRIORITY, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MEM_PRIORITY         0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_MEM_PRIORITY_LOW) ?
+    l_scomData.clearBit<PU_HTM0_HTM_MEM_HTMSC_PRIORITY>() :   // LOW
+    l_scomData.setBit<PU_HTM0_HTM_MEM_HTMSC_PRIORITY>();      // HIGH
+
+    // Set base addr
+    // Right shift PROC HTM Bar Base addr 24 bits to align to 16MB trace memory.
+    FAPI_DBG("  ATTR_PROC_NHTM_BAR_BASE_ADDR 0x%.16llX", l_barAddr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_MEM_HTMSC_BASE,
+                               PU_HTM0_HTM_MEM_HTMSC_BASE_LEN>
+                               (l_barAddr >> 24);
+
+    // Get HTM size
+    FAPI_TRY(getTraceMemSizeValues(l_barSize, l_barHtmSize, l_smallSize),
+             "getTraceMemSizeValues() returns error, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // Set bar size (ATTR_PROC_NHTM_BAR_SIZES)
+    FAPI_DBG("  ATTR_PROC_NHTM_BAR_SIZE  0x%.16llX", l_barSize);
+    FAPI_DBG("  HTMSC_SIZE 0x%.16llX", l_barHtmSize);
+    l_scomData.insertFromRight<PU_HTM0_HTM_MEM_HTMSC_SIZE,
+                               PU_HTM0_HTM_MEM_HTMSC_SIZE_LEN>
+                               (l_barHtmSize);
+
+    // Set mem size
+    FAPI_DBG("  Small Mem Size[%u]          0x%.8X", (uint32_t)l_smallSize);
+    (l_smallSize == true) ?
+    l_scomData.setBit<PU_HTM0_HTM_MEM_HTMSC_SIZE_SMALL>() :
+    l_scomData.clearBit<PU_HTM0_HTM_MEM_HTMSC_SIZE_SMALL>();
+
+    // Display HTM_MEM value to write to HW
+    FAPI_INF("setup_HTM_MEM: HTM_MEM reg setup: 0x%016llX", l_scomData);
+
+    // Write config data into HTM_MEM
+    // Note: Yes, write same value to both engines.
+    for (uint8_t ii = 0; ii < NUM_NHTM_ENGINES; ii++)
+    {
+        FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[ii] + HTM_MEM,
+                                l_scomData),
+                 "setup_HTM_MEM: putScom returns error (1): Addr 0x%016llX, "
+                 "l_rc 0x%.8X",  NHTM_modeRegList[ii] + HTM_MEM,
+                 (uint64_t)fapi2::current_err);
+
+        // MEM_ALLOC must switch from 0->1 for this setup to complete
+        l_scomData.setBit<PU_HTM0_HTM_MEM_HTMSC_ALLOC>();
+        FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[ii] + HTM_MEM,
+                                l_scomData),
+                 "setup_HTM_MEM: putScom returns error (2): Addr 0x%016llX, "
+                 "l_rc 0x%.8X", NHTM_modeRegList[ii] + HTM_MEM,
+                 (uint64_t)fapi2::current_err);
+    }
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+///
+/// TARGET_TYPE_CORE (CHTM trace)
+///
+template<>
+fapi2::ReturnCode setup_HTM_MEM(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+
+    // For IMA trace, no need to program HTM_MEM.
+    // Place holder for other CHTM trace setup when they are suppored.
+
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+
+///
+/// @brief This function sets up the HTM_MODE register.
+///
+/// @tparam T template parameter, passed in target.
+/// @param[in] i_target            Reference to HW target
+/// @param[in] i_traceType         Trace type
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+template<fapi2::TargetType T>
+fapi2::ReturnCode setup_HTM_MODE(const fapi2::Target<T>& i_target,
+                                 const uint8_t i_traceType);
+
+///
+/// TARGET_TYPE_PROC_CHIP (NHTM trace)
+///
+template<>
+fapi2::ReturnCode setup_HTM_MODE(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const uint8_t i_traceType)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData(0);
+    uint8_t l_uint8_attr = 0;
+    uint32_t l_uint32_attr = 0;
+
+    // Setup data value to program HTM_MODE reg
+    // Note:
+    //    - Register bit definitions are the same for both NHTM0 and NHTM1
+    //    - i_traceType may be needed later when more trace type is supported.
+
+    // Enable HTM
+    l_scomData.setBit<PU_HTM0_HTM_MODE_HTMSC_ENABLE>();
+
+    // ATTR_NHTM_HTMSC_MODE_CONTENT_SEL
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_HTMSC_MODE_CONTENT_SEL, i_target,
+                           l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_NHTM_HTMSC_MODE_CONTENT_SEL, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_NHTM_HTMSC_MODE_CONTENT_SEL      0x%.8X", l_uint8_attr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_MODE_HTMSC_CONTENT_SEL,
+                               PU_HTM0_HTM_MODE_HTMSC_CONTENT_SEL_LEN>
+                               (l_uint8_attr);
+
+    // ATTR_NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES,
+                           i_target, l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES 0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES_DISABLE) ?
+    l_scomData.clearBit<PU_HTM0_HTM_MODE_HTMSC_CAPTURE>() :
+    l_scomData.setBit<PU_HTM0_HTM_MODE_HTMSC_CAPTURE>();
+
+    // ATTR_NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL,
+                           i_target, l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL 0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL_DISABLE) ?
+    l_scomData.clearBit<NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL_BIT>() :
+    l_scomData.setBit<NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL_BIT>();
+
+    // ATTR_NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE,
+                           i_target, l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE 0x%.8X", l_uint8_attr);
+    // Clear CRESP mode bits (6:7)
+    l_scomData.clearBit<NHTM_HTMSC_MODE_CAPTURE_CRESP_MODE_BIT_START, 2>();
+
+    if (l_uint8_attr == fapi2::ENUM_ATTR_NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE_ENABLE)
+    {
+        // Set bits 6:7 to 0b10 for Precise cresp mode
+        l_scomData.setBit<NHTM_HTMSC_MODE_CAPTURE_CRESP_MODE_BIT_START>();
+    }
+
+    // ATTR_NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION,
+                           i_target, l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION 0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION_DISABLE) ?
+    l_scomData.clearBit<NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION_BIT>() :
+    l_scomData.setBit<NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION_BIT>();
+
+    // ATTR_NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD,
+                           i_target, l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD 0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD_DISABLE) ?
+    l_scomData.clearBit<NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION_BIT>() :
+    l_scomData.setBit<NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION_BIT>();
+
+    // ATTR_HTMSC_MODE_WRAP
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MODE_WRAP, i_target,
+                           l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_HTMSC_MODE_WRAP, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MODE_WRAP                  0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_MODE_WRAP_DISABLE) ?
+    l_scomData.clearBit<PU_HTM0_HTM_MODE_HTMSC_WRAP>() :
+    l_scomData.setBit<PU_HTM0_HTM_MODE_HTMSC_WRAP>();
+
+    // ATTR_HTMSC_MODE_DIS_TSTAMP
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MODE_DIS_TSTAMP, i_target,
+                           l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_HTMSC_MODE_DIS_TSTAMP, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MODE_DIS_TSTAMP            0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_MODE_DIS_TSTAMP_DISABLE) ?
+    l_scomData.setBit<PU_HTM0_HTM_MODE_HTMSC_DIS_TSTAMP>() :
+    l_scomData.clearBit<PU_HTM0_HTM_MODE_HTMSC_DIS_TSTAMP>();
+
+    // ATTR_HTMSC_MODE_SINGLE_TSTAMP
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MODE_SINGLE_TSTAMP, i_target,
+                           l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_HTMSC_MODE_SINGLE_TSTAMP, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MODE_SINGLE_TSTAMP         0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_MODE_SINGLE_TSTAMP_DISABLE) ?
+    l_scomData.clearBit<PU_HTM0_HTM_MODE_HTMSC_SINGLE_TSTAMP>() :
+    l_scomData.setBit<PU_HTM0_HTM_MODE_HTMSC_SINGLE_TSTAMP>();
+
+    // ATTR_HTMSC_MODE_MARKERS_ONLY
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MODE_MARKERS_ONLY, i_target,
+                           l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_HTMSC_MODE_MARKERS_ONLY, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MODE_MARKERS_ONLY          0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_MODE_MARKERS_ONLY_DISABLE) ?
+    l_scomData.clearBit<PU_HTM0_HTM_MODE_HTMSC_MARKERS_ONLY>() :
+    l_scomData.setBit<PU_HTM0_HTM_MODE_HTMSC_MARKERS_ONLY>();
+
+    // ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE,
+                           i_target, l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE, "
+             "l_rc 0x%.8X",  (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE 0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE_DISABLE) ?
+    l_scomData.clearBit<PU_HTM0_HTM_MODE_HTMSC_DIS_FORCE_GROUP_SCOPE>() :
+    l_scomData.setBit<PU_HTM0_HTM_MODE_HTMSC_DIS_FORCE_GROUP_SCOPE>();
+
+    // ATTR_NHTM_HTMSC_MODE_SYNC_STAMP_FORCE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_HTMSC_MODE_SYNC_STAMP_FORCE, i_target,
+                           l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_NHTM_HTMSC_MODE_SYNC_STAMP_FORCE, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_NHTM_HTMSC_MODE_SYNC_STAMP_FORCE 0x%.8X", l_uint8_attr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_MODE_HTMSC_SYNC_STAMP_FORCE,
+                               PU_HTM0_HTM_MODE_HTMSC_SYNC_STAMP_FORCE_LEN>
+                               (l_uint8_attr);
+
+    // ATTR_NHTM_HTMSC_MODE_WRITETOIO
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_HTMSC_MODE_WRITETOIO,
+                           i_target, l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_NHTM_HTMSC_MODE_WRITETOIO, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_NHTM_HTMSC_MODE_WRITETOIO        0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_NHTM_HTMSC_MODE_WRITETOIO_DISABLE) ?
+    l_scomData.clearBit<PU_HTM0_HTM_MODE_HTMSC_WRITETOIO>() :
+    l_scomData.setBit<PU_HTM0_HTM_MODE_HTMSC_WRITETOIO>();
+
+    // ATTR_HTMSC_MODE_VGTARGET
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MODE_VGTARGET, i_target,
+                           l_uint32_attr),
+             "setup_HTM_MODE: Error getting ATTR_HTMSC_MODE_VGTARGET, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MODE_VGTARGET              0x%.8X", l_uint32_attr);
+    l_scomData.insertFromRight<PU_HTM0_HTM_MODE_HTMSC_VGTARGET,
+                               PU_HTM0_HTM_MODE_HTMSC_VGTARGET_LEN>
+                               (l_uint32_attr);
+
+    // Display HTM_MODE reg setup value
+    FAPI_INF("setup_HTM_MODE: HTM_MODE reg setup: 0x%016llX", l_scomData);
+
+    // Program both NHTM0 and NHTM1
+    for (uint8_t ii = 0; ii < NUM_NHTM_ENGINES; ii++)
+    {
+        FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[ii], l_scomData),
+                 "setup_HTM_MODE: putScom returns error: "
+                 "Addr 0x%016llX, l_rc 0x%.8X",
+                 NHTM_modeRegList[ii],  (uint64_t)fapi2::current_err);
+    }
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+///
+/// TARGET_TYPE_CORE (CHTM trace)
+///
+template<>
+fapi2::ReturnCode setup_HTM_MODE(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_traceType)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData(0);
+    uint8_t l_uint8_attr = 0;
+    uint32_t l_uint32_attr = 0;
+    uint8_t l_pos = 0;
+
+    // Setup data value to program HTM_MODE reg
+    // Note:
+    //    - i_traceType may be needed later when more trace type is supported.
+
+    // Get the proc target to read common CHTM attribute settings
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_proc =
+        i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+    // Get the EX parent of this core to program the register
+    fapi2::Target<fapi2::TARGET_TYPE_EX> l_ex =
+        i_target.getParent<fapi2::TARGET_TYPE_EX>();
+
+    // Enable HTM
+    l_scomData.setBit<EX_HTM_MODE_HTMSC_ENABLE>();
+
+    // ATTR_CHTM_HTMSC_MODE_CONTENT_SEL
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHTM_HTMSC_MODE_CONTENT_SEL, l_proc,
+                           l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_CHTM_HTMSC_MODE_CONTENT_SEL, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_CHTM_HTMSC_MODE_CONTENT_SEL      0x%.8X", l_uint8_attr);
+    l_scomData.insertFromRight<EX_HTM_MODE_HTMSC_CONTENT_SEL,
+                               EX_HTM_MODE_HTMSC_CONTENT_SEL_LEN>
+                               (l_uint8_attr);
+
+    // ATTR_CHTM_HTMSC_MODE_CAPTURE
+    // For CHTM IMA mode (Direct Memory Write), Capture mode bit 4 is used
+    // to enable/disable IMA trace.  This bit will be controlled in
+    // p9_htm_start/stop for IMA instead.
+
+    // ATTR_HTMSC_MODE_WRAP
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MODE_WRAP, l_proc,
+                           l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_HTMSC_MODE_WRAP, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MODE_WRAP                  0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_MODE_WRAP_DISABLE) ?
+    l_scomData.clearBit<EX_HTM_MODE_HTMSC_WRAP>() :
+    l_scomData.setBit<EX_HTM_MODE_HTMSC_WRAP>();
+
+    // ATTR_HTMSC_MODE_DIS_TSTAMP
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MODE_DIS_TSTAMP, l_proc,
+                           l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_HTMSC_MODE_DIS_TSTAMP, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MODE_DIS_TSTAMP            0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_MODE_DIS_TSTAMP_DISABLE) ?
+    l_scomData.setBit<EX_HTM_MODE_HTMSC_DIS_TSTAMP>() :
+    l_scomData.clearBit<EX_HTM_MODE_HTMSC_DIS_TSTAMP>();
+
+    // ATTR_HTMSC_MODE_SINGLE_TSTAMP
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MODE_SINGLE_TSTAMP, l_proc,
+                           l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_HTMSC_MODE_SINGLE_TSTAMP, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MODE_SINGLE_TSTAMP         0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_MODE_SINGLE_TSTAMP_DISABLE) ?
+    l_scomData.clearBit<EX_HTM_MODE_HTMSC_SINGLE_TSTAMP>() :
+    l_scomData.setBit<EX_HTM_MODE_HTMSC_SINGLE_TSTAMP>();
+
+    // ATTR_CHTM_HTMSC_MODE_CORE_INSTR_STALL
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHTM_HTMSC_MODE_CORE_INSTR_STALL, l_proc,
+                           l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_CHTM_HTMSC_MODE_CORE_INSTR_STALL, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_CHTM_HTMSC_MODE_CORE_INSTR_STALL 0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_CHTM_HTMSC_MODE_CORE_INSTR_STALL_DISABLE) ?
+    l_scomData.setBit<EX_HTM_MODE_HTMSC_DIS_STALL>() :
+    l_scomData.clearBit<EX_HTM_MODE_HTMSC_DIS_STALL>();
+
+    // ATTR_HTMSC_MODE_MARKERS_ONLY
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MODE_MARKERS_ONLY, l_proc, l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_HTMSC_MODE_MARKERS_ONLY, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MODE_MARKERS_ONLY          0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_MODE_MARKERS_ONLY_DISABLE) ?
+    l_scomData.clearBit<EX_HTM_MODE_HTMSC_MARKERS_ONLY>() :
+    l_scomData.setBit<EX_HTM_MODE_HTMSC_MARKERS_ONLY>();
+
+    // ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE,
+                           l_proc, l_uint8_attr),
+             "setup_HTM_MODE: Error getting ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE, "
+             "l_rc 0x%.8X",  (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE 0x%.8X", l_uint8_attr);
+    (l_uint8_attr == fapi2::ENUM_ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE_DISABLE) ?
+    l_scomData.clearBit<EX_HTM_MODE_HTMSC_DIS_GROUP>() :
+    l_scomData.setBit<EX_HTM_MODE_HTMSC_DIS_GROUP>();
+
+    // ATTR_HTMSC_MODE_VGTARGET
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HTMSC_MODE_VGTARGET, l_proc,
+                           l_uint32_attr),
+             "setup_HTM_MODE: Error getting ATTR_HTMSC_MODE_VGTARGET, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+    FAPI_DBG("  ATTR_HTMSC_MODE_VGTARGET              0x%.8X", l_uint32_attr);
+    l_scomData.insertFromRight<EX_HTM_MODE_HTMSC_VGTARGET,
+                               EX_HTM_MODE_HTMSC_VGTARGET_LEN>
+                               (l_uint32_attr);
+
+    // Display HTM_MODE reg setup value
+    FAPI_INF("setup_HTM_MODE: HTM_MODE reg setup: 0x%016llX", l_scomData);
+
+    // Write to HW
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target, l_pos),
+             "Error getting ATTR_CHIP_UNIT_POS");
+    FAPI_TRY(fapi2::putScom(l_ex, CHTM_modeReg[l_pos % 2] + HTM_MODE, l_scomData),
+             "setup_HTM_MODE: putScom returns error: "
+             "Addr 0x%016llX, l_rc 0x%.8X",
+             CHTM_modeReg[l_pos % 2] + HTM_MODE, (uint64_t)fapi2::current_err);
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+
+///
+/// @brief Verify HTM engine is in correct state before setting up.
+///
+/// @tparam T template parameter, passed in target.
+/// @param[in] i_target            Reference to HW target
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+template<fapi2::TargetType T>
+fapi2::ReturnCode checkHtmState(const fapi2::Target<T>& i_target);
+
+///
+/// TARGET_TYPE_PROC_CHIP (NHTM trace)
+///
+template<>
+fapi2::ReturnCode checkHtmState(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData(0);
+    fapi2::buffer<uint64_t> l_scomData_2(0);
+
+    // Read HTM_STATE
+    FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[0] + HTM_STAT,
+                            l_scomData),
+             "checkHtmState: getScom returns error: Addr 0x%016llX, "
+             "l_rc 0x%.8X", NHTM_modeRegList[0] + HTM_STAT,
+             (uint64_t)fapi2::current_err);
+
+    FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[1] + HTM_STAT,
+                            l_scomData_2),
+             "checkHtmState: getScom returns error: Addr 0x%016llX, "
+             "l_rc 0x%.8X", NHTM_modeRegList[1] + HTM_STAT,
+             (uint64_t)fapi2::current_err);
+
+    // HTM must be in "Complete", "Repair", or "Blank" state
+    // Bit positions are same for HTM0 and HTM1
+    FAPI_ASSERT( ( (l_scomData == 0) && (l_scomData_2 == 0) ) ||  // Blank
+                 ( l_scomData.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_COMPLETE>() &&
+                   l_scomData_2.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_COMPLETE>() ) ||
+                 ( l_scomData.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_REPAIR>() &&
+                   l_scomData_2.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_REPAIR>() ),
+                 fapi2::P9_NHTM_CTRL_BAD_STATE()
+                 .set_TARGET(i_target)
+                 .set_HTM_STATUS_REG_NHTM0(l_scomData)
+                 .set_HTM_STATUS_REG_NHTM1(l_scomData_2),
+                 "checkHtmState: Can not setup HTM with current HTM state "
+                 "NHTM0 status 0x%016llX, NHTM1 status 0x%016llX",
+                 l_scomData, l_scomData_2);
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+///
+/// TARGET_TYPE_CORE (CHTM trace)
+///
+template<>
+fapi2::ReturnCode checkHtmState(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData(0);
+    uint8_t l_pos = 0;
+
+    // Get the EX parent of this core
+    fapi2::Target<fapi2::TARGET_TYPE_EX> l_ex =
+        i_target.getParent<fapi2::TARGET_TYPE_EX>();
+
+    // Get the core position
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target, l_pos),
+             "Error getting ATTR_CHIP_UNIT_POS");
+
+    // Read HTM_STATE
+    FAPI_TRY(fapi2::getScom(l_ex, CHTM_modeReg[l_pos % 2] + HTM_STAT, l_scomData),
+             "checkHtmState: getScom returns error: Addr 0x%016llX, "
+             "l_rc 0x%.8X", CHTM_modeReg[l_pos % 2] + HTM_STAT,
+             (uint64_t)fapi2::current_err);
+
+    // HTM must be in "Complete", "Repair", or "Blank" state
+    FAPI_ASSERT( (l_scomData == 0) ||
+                 (l_scomData.getBit<EX_HTM_STAT_HTMCO_STATUS_COMPLETE>()) ||
+                 (l_scomData.getBit<EX_HTM_STAT_HTMCO_STATUS_REPAIR>()),
+                 fapi2::P9_CHTM_CTRL_BAD_STATE()
+                 .set_TARGET(l_ex)
+                 .set_HTM_STATUS_REG(l_scomData),
+                 "checkHtmState: Can not setup HTM with current HTM state "
+                 "0x%016llX", l_scomData);
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+///
+/// @brief Get trace types from attributes and verify they are valid.
+///
+///
+/// @param[in]  i_target           Reference to processor chip target
+/// @param[out] o_nhtmTraceType    NHTM trace type
+/// @param[out] o_chtmTraceType    CHTM trace type
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode getTraceTypes(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    uint8_t& o_nhtmTraceType,
+    uint8_t o_chtmTraceType[])
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    char l_targetStr[fapi2::MAX_ECMD_STRING_LEN];
+    uint8_t l_chtmTraceType[NUM_CHTM_ENGINES];
+
+    // Display target
+    fapi2::toString(i_target, l_targetStr, fapi2::MAX_ECMD_STRING_LEN);
+    FAPI_INF("Target %s: HTM setup attributes", l_targetStr);
+
+    // Get ATTR_NHTM_TRACE_TYPE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_TRACE_TYPE, i_target,
+                           o_nhtmTraceType),
+             "getTraceTypes: Error getting ATTR_NHTM_TRACE_TYPE, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // Show NHTM trace type
+    FAPI_INF("    NHTM type: %u", o_nhtmTraceType);
+
+    // Currently only support NHTM FABRIC type
+    FAPI_ASSERT( (o_nhtmTraceType == fapi2::ENUM_ATTR_NHTM_TRACE_TYPE_DISABLE) ||
+                 (o_nhtmTraceType == fapi2::ENUM_ATTR_NHTM_TRACE_TYPE_FABRIC),
+                 fapi2::NHTM_TRACE_TYPE_NOT_SUPPORTED()
+                 .set_NHTM_TRACE_TYPE(o_nhtmTraceType),
+                 "getTraceTypes: NHTM trace type is not supported: "
+                 "0x%.8X", o_nhtmTraceType);
+
+    // Get ATTR_CHTM_TRACE_TYPE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHTM_TRACE_TYPE, i_target,
+                           l_chtmTraceType),
+             "getTraceTypes: Error getting ATTR_CHTM_TRACE_TYPE, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+    memcpy(o_chtmTraceType, l_chtmTraceType, sizeof(l_chtmTraceType));
+
+    // Show CHTM trace type
+    for (uint8_t ii = 0; ii < NUM_CHTM_ENGINES; ii++)
+    {
+        FAPI_INF("    CHTM type: Core[%u] %u", ii, o_chtmTraceType[ii]);
+    }
+
+    // Verify each core trace type, all so set flag
+    // to indicate if any core trace is enabled.
+    for (uint8_t ii = 0; ii < NUM_CHTM_ENGINES; ii++)
+    {
+        if (o_chtmTraceType[ii] != fapi2::ENUM_ATTR_CHTM_TRACE_TYPE_DISABLE)
+        {
+            // Currently only support CHTM DMW (IMA) type
+            FAPI_ASSERT( (o_chtmTraceType[ii] == fapi2::ENUM_ATTR_CHTM_TRACE_TYPE_DISABLE) ||
+                         (o_chtmTraceType[ii] == fapi2::ENUM_ATTR_CHTM_TRACE_TYPE_DMW),
+                         fapi2::CHTM_TRACE_TYPE_NOT_SUPPORTED()
+                         .set_CORE_POS(ii)
+                         .set_CHTM_TRACE_TYPE(o_chtmTraceType[ii]),
+                         "getTraceTypes: CHTM trace type is not supported: "
+                         "Core #%u, TraceType 0x%.8X", ii, o_chtmTraceType[ii]);
+        }
+    }
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+extern "C" {
 
 ///
 /// @brief p9_htm_setup procedure entry point
 /// See doxygen in p9_htm_setup.H
 ///
     fapi2::ReturnCode p9_htm_setup(
-        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const bool i_start)
     {
-        FAPI_DBG("Entering p9_htm_setup");
+        FAPI_INF("Entering p9_htm_setup");
         fapi2::ReturnCode l_rc;
+        uint8_t l_nhtmType = 0;
+        uint8_t l_chtmType[NUM_CHTM_ENGINES];
+        uint8_t l_corePos = 0;
+        auto l_coreChiplets = i_target.getChildren<fapi2::TARGET_TYPE_CORE>();
+        bool l_htmEnabled = false;
+
+        // ----------------------------------------------
+        // Check if NTHM/CHTM trace is enabled
+        // ----------------------------------------------
+        FAPI_TRY(getTraceTypes(i_target, l_nhtmType, l_chtmType),
+                 "isTraceEnabled() returns an error, l_rc 0x%.8X",
+                 (uint64_t)fapi2::current_err);
+
+        // ----------------------------------------------
+        // Setup NHTM trace
+        // ----------------------------------------------
+        if (l_nhtmType != fapi2::ENUM_ATTR_NHTM_TRACE_TYPE_DISABLE)
+        {
+            l_htmEnabled = true;
+
+            // 1. Check HW state
+            FAPI_TRY(checkHtmState(i_target),
+                     "checkHtmState() returns an error, l_rc 0x%.8X",
+                     (uint64_t)fapi2::current_err);
+
+            // 2. Setup HTM_MODE reg
+            FAPI_TRY(setup_HTM_MODE(i_target, l_nhtmType),
+                     "setup_HTM_MODE() returns an error, l_rc 0x%.8X",
+                     (uint64_t)fapi2::current_err);
+
+            // 3. Setup HTM_MEM reg
+            FAPI_TRY(setup_HTM_MEM(i_target),
+                     "setup_HTM_MODE() returns an error, l_rc 0x%.8X",
+                     (uint64_t)fapi2::current_err);
+
+            // 4. Setup HTM_CTRL reg
+            FAPI_TRY(setup_HTM_CTRL(i_target),
+                     "setup_HTM_CTRL() returns an error, l_rc 0x%.8X",
+                     (uint64_t)fapi2::current_err);
+
+            // 5. Setup NHTM_FILT reg
+            FAPI_TRY(setup_NHTM_FILT(i_target),
+                     "setup_NHTM_FILT() returns an error, l_rc 0x%.8X",
+                     (uint64_t)fapi2::current_err);
+
+            // 6. Setup NHTM_TTYPE_FILT reg (FABRIC trace type only)
+            if (l_nhtmType == fapi2::ENUM_ATTR_NHTM_TRACE_TYPE_FABRIC)
+            {
+                FAPI_TRY(setup_NHTM_TTYPE_FILT(i_target),
+                         "setup_NHTM_TTYPE_FILT() returns an error, l_rc 0x%.8X",
+                         (uint64_t)fapi2::current_err);
+            }
+        }
+
+        // ----------------------------------------------
+        // Setup CHTM trace
+        // ----------------------------------------------
+        for (auto l_core : l_coreChiplets)
+        {
+            // Note:
+            //   - PHYP will setup CHTM IMA trace, nothing to do during IPL.
+            //   - IMA setup code is left here for reference only.  It should
+            //     not be invoked unless ATTR_CHTM_TRACE_TYPE = DMW.
+            //   - Other CHTM trace types are not supported until Nimbus DD2.0.
+            //     ATTR_CHTM_TRACE_TYPE should be DISABLE for Nimbus 1.0.
+
+            // Get the core position
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_core, l_corePos),
+                     "Error getting ATTR_CHIP_UNIT_POS");
+
+            // Skip if CHTM is disable on this core
+            if (l_chtmType[l_corePos] == fapi2::ENUM_ATTR_CHTM_TRACE_TYPE_DISABLE)
+            {
+                continue;
+            }
+
+            l_htmEnabled = true;
+            FAPI_INF("p9_htm_setup: Setup CHTM for core unit %u", l_corePos);
+
+            // 1. Check HW state
+            FAPI_TRY(checkHtmState(l_core),
+                     "checkHtmState() returns an error, l_rc 0x%.8X",
+                     (uint64_t)fapi2::current_err);
+
+            // DMW (IMA) trace type only
+            if (l_chtmType[l_corePos] == fapi2::ENUM_ATTR_CHTM_TRACE_TYPE_DMW)
+            {
+                // 2. Setup CHTM_PDBAR reg
+                FAPI_TRY(setup_CHTM_PDBAR(l_core),
+                         "setup_CHTM_PDBAR() returns an error, l_rc 0x%.8X",
+                         (uint64_t)fapi2::current_err);
+
+                // 3. Setup IMA_EVENT_MASK
+                FAPI_TRY(setup_IMA_EVENT_MASK(l_core),
+                         "setup_CHTM_PDBAR() returns an error, l_rc 0x%.8X",
+                         (uint64_t)fapi2::current_err);
+            }
+
+            // 4. Setup HTM_MODE reg
+            FAPI_TRY(setup_HTM_MODE(l_core, l_chtmType[l_corePos]),
+                     "setup_HTM_MODE() returns an error, l_rc 0x%.8X",
+                     (uint64_t)fapi2::current_err);
+        }
+
+        // Perform reset/start only if certain trace is enabled.
+        if (l_htmEnabled == true)
+        {
+            // ----------------------------------------------
+            // Reset HTMs
+            // ----------------------------------------------
+            FAPI_TRY(p9_htm_reset(i_target),
+                     "p9_htm_reset() returns an error, l_rc 0x%.8X",
+                     (uint64_t)fapi2::current_err);
+
+            // ----------------------------------------------
+            // Start collect both NHTM and CHTM traces
+            // ----------------------------------------------
+            if (i_start == true)
+            {
+                FAPI_TRY(p9_htm_start(i_target),
+                         "p9_htm_start() returns an error, l_rc 0x%.8X",
+                         (uint64_t)fapi2::current_err);
+            }
+        }
 
+    fapi_try_exit:
         FAPI_DBG("Exiting p9_htm_setup");
         return fapi2::current_err;
     }
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_setup.H b/src/import/chips/p9/procedures/hwp/nest/p9_htm_setup.H
index c7cbf57a0..0bbf64cfe 100755
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_setup.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_setup.H
@@ -21,15 +21,16 @@
 ///
 /// @brief Perform p9_htm_setup on a processor chip
 ///
-/// The purpose of this procedure is to setup and start HTM on a processor
+/// The purpose of this procedure is to setup HTM on a processor
 /// chip.
+///
 /// Some start/setup attributes are used as part of the setup process.
 ///
 /// ----------------------------------------------------------------------------
 /// *HWP HWP Owner   : Joe McGill <jmcgill@us.ibm.com>
 /// *HWP FW Owner    : Thi Tran <thi@us.ibm.com>
 /// *HWP Team        : Nest
-/// *HWP Level       : 1
+/// *HWP Level       : 2
 /// *HWP Consumed by : HB
 /// ----------------------------------------------------------------------------
 
@@ -43,7 +44,26 @@
 
 // Function pointer typedef definition for HWP call support
 typedef fapi2::ReturnCode (*p9_htm_setup_FP_t)(
-    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+    const bool i_start);
+
+//----------------------------------------------------------------------------
+// Constant definitions
+//----------------------------------------------------------------------------
+// Size selected via HTM_MEM.MEM_SIZE_SMALL (bit 13)
+enum htm_size_t
+{
+    HTM_512M_OR_16M = 0x0,
+    HTM_1G_OR_32M   = 0x1,
+    HTM_2G_OR_64M   = 0x3,
+    HTM_4G_OR_128M  = 0x7,
+    HTM_8G_OR_256M  = 0xF,
+    HTM_16G_OR_512M = 0x1F,
+    HTM_32G_OR_1G   = 0x3F,
+    HTM_64G_OR_2G   = 0x7F,
+    HTM_128G_OR_4G  = 0xFF,
+    HTM_256G_OR_8G  = 0x1FF
+};
 
 //------------------------------------------------------------------------------
 // Function prototypes
@@ -54,14 +74,17 @@ extern "C"
 ///
 /// @brief p9_htm_setup procedure
 ///
-/// This HWP is to setup the HTM on the input processor chip.
+/// The purpose of this procedure is to setup HTM on a processor
+/// chip.
 ///
-/// @param[in]    i_target   Reference to TARGET_TYPE_PROC_CHIP target
+/// @param[in]    i_target   Reference to TARGET_TYPE_PROC_CHIP target.
+/// @param[in]    i_start    Start HTM after setup.
 ///
 /// @return FAPI2_RC_SUCCESS if success, else error code.
 ///
     fapi2::ReturnCode p9_htm_setup(
-        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const bool i_start = true);
 
 } // extern "C"
 
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_setup.mk b/src/import/chips/p9/procedures/hwp/nest/p9_htm_setup.mk
index c564fcbd2..e793ad730 100755
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_setup.mk
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_setup.mk
@@ -7,7 +7,7 @@
 #
 # EKB Project
 #
-# COPYRIGHT 2015
+# COPYRIGHT 2015,2016
 # [+] International Business Machines Corp.
 #
 #
@@ -17,4 +17,9 @@
 #
 # IBM_PROLOG_END_TAG
 PROCEDURE=p9_htm_setup
+OBJS+=p9_htm_start.o
+OBJS+=p9_htm_reset.o
+OBJS+=p9_htm_adu_ctrl.o
+OBJS+=p9_adu_coherent_utils.o
+OBJS+=p9_fbc_utils.o
 $(call BUILD_PROCEDURE)
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_start.C b/src/import/chips/p9/procedures/hwp/nest/p9_htm_start.C
index b7c70f0ae..af1c9bdb1 100755
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_start.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_start.C
@@ -29,7 +29,7 @@
 /// *HWP HWP Owner   : Joe McGill <jmcgill@us.ibm.com>
 /// *HWP FW Owner    : Thi Tran <thi@us.ibm.com>
 /// *HWP Team        : Nest
-/// *HWP Level       : 1
+/// *HWP Level       : 2
 /// *HWP Consumed by : HB
 ///----------------------------------------------------------------------------
 
@@ -37,6 +37,140 @@
 // Includes
 //------------------------------------------------------------------------------
 #include <p9_htm_start.H>
+#include <p9_htm_def.H>
+#include <p9_htm_adu_ctrl.H>
+
+//------------------------------------------------------------------------------
+// Constants
+//------------------------------------------------------------------------------
+
+// ADU PMISC address bit definition
+const uint8_t ADU_ADDRESS_HTM_START_BIT = 46;
+
+///
+/// @brief Start HTM collection
+///
+/// @param[in] i_target         Reference to target
+/// @param[in] i_pos            Position of HTM engine to start
+/// @param[in] i_traceType      Trace type
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+template<fapi2::TargetType T>
+fapi2::ReturnCode startHTM(const fapi2::Target<T>& i_target,
+                           const uint8_t i_pos,
+                           const uint8_t i_traceType);
+
+/// TARGET_TYPE_PROC_CHIP (NHTM)
+template<>
+fapi2::ReturnCode startHTM(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const uint8_t i_pos,
+    const uint8_t i_traceType)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData(0);
+    fapi2::buffer<uint64_t> l_scomData_2(0);
+
+    // Engines must be in ready or pause state
+    FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[0] + HTM_STAT, l_scomData),
+             "startHTM: getScom returns error: "
+             "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[0] + HTM_STAT,
+             (uint64_t)fapi2::current_err);
+    FAPI_TRY(fapi2::getScom(i_target, NHTM_modeRegList[1] + HTM_STAT, l_scomData_2),
+             "startHTM: getScom returns error: "
+             "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[1] + HTM_STAT,
+             (uint64_t)fapi2::current_err);
+
+    FAPI_ASSERT( (l_scomData.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_READY>() ||
+                  l_scomData.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_PAUSED>()) &&
+                 (l_scomData_2.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_READY>() ||
+                  l_scomData_2.getBit<PU_HTM0_HTM_STAT_HTMCO_STATUS_PAUSED>()),
+                 fapi2::P9_NHTM_CTRL_BAD_STATE()
+                 .set_TARGET(i_target)
+                 .set_HTM_STATUS_REG_NHTM0(l_scomData)
+                 .set_HTM_STATUS_REG_NHTM1(l_scomData_2),
+                 "startHTM: NHTM is not in Ready state, can't start "
+                 "NHTM0 status 0x%016llX, NHTM1 status 0x%016llX",
+                 l_scomData, l_scomData_2);
+
+    // Set HTM_TRIG's MARK_VALID
+    l_scomData = 0;
+    l_scomData.setBit<PU_HTM0_HTM_TRIG_HTMSC_MARK_VALID>();
+    FAPI_INF("startHTM: HTM_TRIG reg Start: 0x%016llX", l_scomData);
+
+    FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[0] + HTM_TRIG, l_scomData),
+             "startHTM: putScom returns error: "
+             "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[0] + HTM_TRIG,
+             (uint64_t)fapi2::current_err);
+
+    FAPI_TRY(fapi2::putScom(i_target, NHTM_modeRegList[1] + HTM_TRIG, l_scomData),
+             "startHTM: putScom returns error: "
+             "Addr 0x%016llX, l_rc 0x%.8X", NHTM_modeRegList[1] + HTM_TRIG,
+             (uint64_t)fapi2::current_err);
+
+    // Note: Use global PMISC ADU start command to better synchornize
+    //       the traces of NHTM0 and NHTM1
+
+    // Build address value
+    l_scomData.flush<0>().setBit<ADU_ADDRESS_HTM_START_BIT>();
+
+    // Start global trigger on the NHTM engines
+    FAPI_TRY(aduNHTMControl(i_target, l_scomData),
+             "startHTM: aduNHTMControl returns error.");
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+/// TARGET_TYPE_CORE (CHTM)
+template<>
+fapi2::ReturnCode startHTM(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
+                           const uint8_t i_pos,
+                           const uint8_t i_traceType)
+{
+    FAPI_DBG("Entering");
+    fapi2::ReturnCode l_rc;
+    fapi2::buffer<uint64_t> l_scomData(0);
+    uint32_t l_imaHTMEnable = 0b100000000; // Set bit 4 of HTM_MODE to enable IMA
+
+    // Get the EX parent of this core
+    fapi2::Target<fapi2::TARGET_TYPE_EX> l_ex =
+        i_target.getParent<fapi2::TARGET_TYPE_EX>();
+
+    // IMA trace
+    if (i_traceType == fapi2::ENUM_ATTR_CHTM_TRACE_TYPE_DMW)
+    {
+        // Get HTM_MODE reg
+        FAPI_TRY(fapi2::getScom(l_ex, CHTM_modeReg[i_pos % 2] + HTM_MODE, l_scomData),
+                 "startHTM: getScom returns error: "
+                 "Addr 0x%016llX, l_rc 0x%.8X",
+                 CHTM_modeReg[i_pos % 2] + HTM_MODE, (uint64_t)fapi2::current_err);
+
+        // Enable IMA capture
+        l_scomData.insertFromRight<EX_HTM_MODE_HTMSC_CAPTURE,
+                                   EX_HTM_MODE_HTMSC_CAPTURE_LEN>
+                                   (l_imaHTMEnable);
+        FAPI_INF("startHTM: HTM_MODE reg setup: 0x%016llX", l_scomData);
+        FAPI_TRY(fapi2::putScom(l_ex, CHTM_modeReg[i_pos % 2] + HTM_MODE, l_scomData),
+                 "startHTM: putScom returns error: "
+                 "Addr 0x%016llX, l_rc 0x%.8X", CHTM_modeReg[i_pos % 2] + HTM_MODE,
+                 (uint64_t)fapi2::current_err);
+
+        // Display HTM_IMA_STATUS reg value
+        FAPI_TRY(fapi2::getScom(l_ex, EX_HTM_IMA_STATUS, l_scomData),
+                 "startHTM: getScom returns error: Addr "
+                 "0x%016llX, l_rc 0x%.8X", EX_HTM_IMA_STATUS,
+                 (uint64_t)fapi2::current_err);
+        FAPI_INF("startHTM: HTM_IMA_STATUS: 0x%016llX", l_scomData);
+    }
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
 
 extern "C" {
 
@@ -47,10 +181,66 @@ extern "C" {
     fapi2::ReturnCode p9_htm_start(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     {
-        FAPI_DBG("Entering p9_htm_start");
+        FAPI_DBG("Entering");
         fapi2::ReturnCode l_rc;
+        uint8_t l_nhtmType;
+        uint8_t l_chtmType[NUM_CHTM_ENGINES];
+        uint8_t l_corePos = 0;
+        auto l_modeRegList = std::vector<uint64_t>();
+        auto l_coreChiplets = i_target.getChildren<fapi2::TARGET_TYPE_CORE>();
+        fapi2::buffer<uint64_t> l_scomData(0);
+
+        // Display attribute trace setup values
+
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NHTM_TRACE_TYPE, i_target,
+                               l_nhtmType),
+                 "p9_htm_start: Error getting ATTR_NHTM_TRACE_TYPE, l_rc 0x%.8X",
+                 (uint64_t)fapi2::current_err);
+        FAPI_INF("p9_htm_start: NHTM type: 0x%.8X", l_nhtmType);
+
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHTM_TRACE_TYPE, i_target,
+                               l_chtmType),
+                 "p9_htm_start: Error getting ATTR_CHTM_TRACE_TYPE, l_rc 0x%.8X",
+                 (uint64_t)fapi2::current_err);
+        FAPI_INF("p9_htm_start: CHTM type:");
+
+        for (uint8_t ii = 0; ii < NUM_CHTM_ENGINES; ii++)
+        {
+            FAPI_INF("              Core[%u] 0x%.8X", ii, l_chtmType[ii]);
+        }
+
+        // Start NHTM
+        if (l_nhtmType != fapi2::ENUM_ATTR_NHTM_TRACE_TYPE_DISABLE)
+        {
+            // Start trace for both NHTM0 and NHTM1
+            // Note: We want to synch the trace for both NHTM engines as much
+            //       as possible, so do not loop on individual engine
+            //       here.  The startHTM function will check state and issue
+            //       a global ADU command to start both engines.
+            FAPI_TRY( startHTM(i_target, 0, l_nhtmType),
+                      "p9_htm_start: startHTM() returns error NHTM"
+                      "l_rc 0x%.8X", (uint64_t)fapi2::current_err );
+        }
+
+        // Start CHTM
+        for (auto l_core : l_coreChiplets)
+        {
+            // Get the core position
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_core, l_corePos),
+                     "Error getting ATTR_CHIP_UNIT_POS");
+
+            if (l_chtmType[l_corePos] != fapi2::ENUM_ATTR_CHTM_TRACE_TYPE_DISABLE)
+            {
+                FAPI_DBG("Start HTM on core %u....", l_corePos);
+                FAPI_TRY(startHTM(l_core, l_corePos, l_chtmType[l_corePos]),
+                         "p9_htm_start: startHTM() returns error: CHTM %u, "
+                         "l_rc 0x%.8X", l_corePos, (uint64_t)fapi2::current_err );
+            }
+
+        }
 
-        FAPI_DBG("Exiting p9_htm_start");
+    fapi_try_exit:
+        FAPI_DBG("Exiting");
         return fapi2::current_err;
     }
 
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_start.H b/src/import/chips/p9/procedures/hwp/nest/p9_htm_start.H
index 2f6a8b808..15d0e81fd 100755
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_start.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_start.H
@@ -29,7 +29,7 @@
 /// *HWP HWP Owner   : Joe McGill <jmcgill@us.ibm.com>
 /// *HWP FW Owner    : Thi Tran <thi@us.ibm.com>
 /// *HWP Team        : Nest
-/// *HWP Level       : 1
+/// *HWP Level       : 2
 /// *HWP Consumed by : HB
 /// ----------------------------------------------------------------------------
 
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_start.mk b/src/import/chips/p9/procedures/hwp/nest/p9_htm_start.mk
index 8ed68e02d..33c9eb1ab 100755
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_start.mk
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_start.mk
@@ -7,7 +7,7 @@
 #
 # EKB Project
 #
-# COPYRIGHT 2015
+# COPYRIGHT 2015,2016
 # [+] International Business Machines Corp.
 #
 #
@@ -17,4 +17,6 @@
 #
 # IBM_PROLOG_END_TAG
 PROCEDURE=p9_htm_start
+OBJS+=p9_htm_adu_ctrl.o
+OBJS+=p9_adu_coherent_utils.o
 $(call BUILD_PROCEDURE)
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
index 81e513758..21e3aa7be 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
@@ -191,11 +191,13 @@ struct EffGroupingProcAttrs
     // Public data
     uint64_t iv_memBaseAddr = 0;    // ATTR_PROC_MEM_BASE
     uint64_t iv_mirrorBaseAddr = 0; // ATTR_PROC_MIRROR_BASE
-    uint64_t iv_htmBarSizes[NUM_OF_HTM_REGIONS] = {0, 0}; // ATTR_PROC_HTM_BAR_SIZES
+    uint64_t iv_nhtmBarSize;       // ATTR_PROC_NHTM_BAR_SIZE
+    uint64_t iv_chtmBarSizes[NUM_OF_CHTM_REGIONS];  // ATTR_PROC_CHTM_BAR_SIZES
+
     uint64_t iv_occSandboxSize = 0; // ATTR_PROC_OCC_SANDBOX_SIZE
-    uint32_t iv_fabricSystemId = 0; // ATTR_FABRIC_SYSTEM_ID
-    uint8_t  iv_fabricGroupId = 0;  // ATTR_FABRIC_GROUP_ID
-    uint8_t  iv_fabricChipId = 0;   // ATTR_FABRIC_CHIP_ID
+    uint32_t iv_fabricSystemId = 0; // ATTR_PROC_FABRIC_SYSTEM_ID
+    uint8_t  iv_fabricGroupId = 0;  // ATTR_PROC_FABRIC_GROUP_ID
+    uint8_t  iv_fabricChipId = 0;   // ATTR_PROC_FABRIC_CHIP_ID
 };
 
 
@@ -238,9 +240,14 @@ fapi2::ReturnCode EffGroupingProcAttrs::getAttrs(
     FAPI_DBG("Entering EffGroupingProcAttrs::getAttrs");
     fapi2::ReturnCode l_rc;
 
-    // Get Hardware Trace Macro (HTM) bar size
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_HTM_BAR_SIZES, i_target, iv_htmBarSizes),
-             "Error getting ATTR_PROC_HTM_BAR_SIZES, l_rc 0x%.8X",
+    // Get Nest Hardware Trace Macro (NHTM) bar size
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NHTM_BAR_SIZE, i_target, iv_nhtmBarSize),
+             "Error getting ATTR_PROC_HTM_BAR_SIZE, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
+    // Get Core Hardware Trace Macro (CHTM) bar size
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_CHTM_BAR_SIZES, i_target, iv_chtmBarSizes),
+             "Error getting ATTR_PROC_CHTM_BAR_SIZES, l_rc 0x%.8X",
              (uint64_t)fapi2::current_err);
 
     // Get On Chip Controler (OCC) sandbox size
@@ -252,19 +259,19 @@ fapi2::ReturnCode EffGroupingProcAttrs::getAttrs(
     // Get Fabric system ID
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, i_target,
                            iv_fabricSystemId),
-             "Error getting ATTR_FABRIC_SYSTEM_ID, l_rc 0x%.8X",
+             "Error getting ATTR_PROC_FABRIC_SYSTEM_ID, l_rc 0x%.8X",
              (uint64_t)fapi2::current_err);
 
     // Get Fabric group ID
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target,
                            iv_fabricGroupId),
-             "Error getting ATTR_FABRIC_GROUP_ID, l_rc 0x%.8X",
+             "Error getting ATTR_PROC_FABRIC_GROUP_ID, l_rc 0x%.8X",
              (uint64_t)fapi2::current_err);
 
     // Get Fabric chip ID
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target,
                            iv_fabricChipId),
-             "Error getting ATTR_FABRIC_CHIP_ID, l_rc 0x%.8X",
+             "Error getting ATTR_PROC_FABRIC_CHIP_ID, l_rc 0x%.8X",
              (uint64_t)fapi2::current_err);
 
     // Figure out memory base addresses for this proc and
@@ -275,12 +282,17 @@ fapi2::ReturnCode EffGroupingProcAttrs::getAttrs(
 
     // Display attribute values
     FAPI_INF("EffGroupingProcAttrs::getAttrs: ");
-    FAPI_INF("  ATTR_PROC_HTM_BAR_SIZES[0] 0x%.16llX", iv_htmBarSizes[0]);
-    FAPI_INF("  ATTR_PROC_HTM_BAR_SIZES[1] 0x%.16llX", iv_htmBarSizes[1]);
+    FAPI_INF("  ATTR_PROC_NHTM_BAR_SIZE 0x%.16llX", iv_nhtmBarSize);
+
+    for (uint8_t ii = 0; ii < NUM_OF_CHTM_REGIONS; ii++)
+    {
+        FAPI_INF("  ATTR_PROC_CHTM_BAR_SIZES[%u] 0x%.16llX", ii, iv_chtmBarSizes[ii]);
+    }
+
     FAPI_INF("  ATTR_PROC_OCC_SANDBOX_SIZE 0x%.16llX", iv_occSandboxSize);
-    FAPI_INF("  ATTR_FABRIC_SYSTEM_ID 0x%.8X", iv_fabricSystemId);
-    FAPI_INF("  ATTR_FABRIC_GROUP_ID 0x%.8X", iv_fabricGroupId);
-    FAPI_INF("  ATTR_FABRIC_CHIP_ID 0x%.8X", iv_fabricChipId);
+    FAPI_INF("  ATTR_PROC_FABRIC_SYSTEM_ID 0x%.8X", iv_fabricSystemId);
+    FAPI_INF("  ATTR_PROC_FABRIC_GROUP_ID 0x%.8X", iv_fabricGroupId);
+    FAPI_INF("  ATTR_PROC_FABRIC_CHIP_ID 0x%.8X", iv_fabricChipId);
     FAPI_INF("  ATTR_PROC_MEM_BASE 0x%.16llX", iv_memBaseAddr);
     FAPI_INF("  ATTR_PROC_MIRROR_BASE 0x%.16llX", iv_mirrorBaseAddr);
 
@@ -650,7 +662,7 @@ struct EffGroupingBaseSizeData
         memset(iv_mirror_bases_ack, 0, sizeof(iv_mirror_bases_ack));
         memset(iv_mirror_sizes, 0, sizeof(iv_mirror_sizes));
         memset(iv_mirror_sizes_ack, 0, sizeof(iv_mirror_sizes_ack));
-        memset(iv_htm_bar_bases, 0, sizeof(iv_htm_bar_bases));
+        memset(iv_chtm_bar_bases, 0, sizeof(iv_chtm_bar_bases));
     }
 
     ///
@@ -710,7 +722,8 @@ struct EffGroupingBaseSizeData
     uint64_t iv_mirror_sizes_ack[NUM_MIRROR_REGIONS];
 
     uint64_t iv_occ_sandbox_base = 0;
-    uint64_t iv_htm_bar_bases[NUM_OF_HTM_REGIONS];
+    uint64_t iv_nhtm_bar_base = 0;
+    uint64_t iv_chtm_bar_bases[NUM_OF_CHTM_REGIONS];
 };
 
 // See description in struct definition
@@ -805,9 +818,18 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr(
 
     uint64_t l_totalSize = 0;
     uint8_t l_memHole = 0;
-    uint64_t l_htmSize = i_procAttrs.iv_htmBarSizes[0] +
-                         i_procAttrs.iv_htmBarSizes[1];
-    uint64_t l_htmOccSize = l_htmSize +
+
+    // Calculate total HTM size
+    uint64_t l_nhtmSize = i_procAttrs.iv_nhtmBarSize;
+
+    uint64_t l_chtmSize = 0;
+
+    for (uint8_t ii = 0; ii < NUM_OF_CHTM_REGIONS; ii++)
+    {
+        l_chtmSize += i_procAttrs.iv_chtmBarSizes[ii];
+    }
+
+    uint64_t l_htmOccSize = l_nhtmSize + l_chtmSize +
                             i_procAttrs.iv_occSandboxSize;
 
     // No HTM/OCC size desired, get out with FAPI2_RC_SUCCESS (by default).
@@ -838,8 +860,8 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr(
         FAPI_ASSERT(l_totalSize >= l_htmOccSize,
                     fapi2::MSS_EFF_GROUPING_NO_SPACE_FOR_HTM_OCC_BAR()
                     .set_TOTAL_SIZE(l_totalSize)
-                    .set_HTM_BAR_SIZE_1(i_procAttrs.iv_htmBarSizes[0])
-                    .set_HTM_BAR_SIZE_2(i_procAttrs.iv_htmBarSizes[1])
+                    .set_NHTM_TOTAL_BAR_SIZE(l_nhtmSize)
+                    .set_CHTM_TOTAL_BAR_SIZE(l_chtmSize)
                     .set_OCC_SANDBOX_BAR_SIZE(i_procAttrs.iv_occSandboxSize)
                     .set_MIRROR_PLACEMENT_POLICY(i_sysAttrs.iv_selectiveMode),
                     "EffGroupingBaseSizeData::set_HTM_OCC_base_addr: Required memory "
@@ -868,8 +890,8 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr(
             FAPI_ASSERT(iv_memory_sizes[l_index] >= l_htmOccSize,
                         fapi2::MSS_EFF_GROUPING_HTM_OCC_BAR_NOT_POSSIBLE()
                         .set_TOTAL_SIZE(l_totalSize)
-                        .set_HTM_BAR_SIZE_1(i_procAttrs.iv_htmBarSizes[0])
-                        .set_HTM_BAR_SIZE_2(i_procAttrs.iv_htmBarSizes[1])
+                        .set_NHTM_TOTAL_BAR_SIZE(l_nhtmSize)
+                        .set_CHTM_TOTAL_BAR_SIZE(l_chtmSize)
                         .set_OCC_SANDBOX_BAR_SIZE(i_procAttrs.iv_occSandboxSize)
                         .set_MIRROR_PLACEMENT_POLICY(i_sysAttrs.iv_selectiveMode),
                         "EffGroupingBaseSizeData::set_HTM_OCC_base_addr: Memory HTM/OCC "
@@ -892,23 +914,30 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr(
                                    (l_temp_size - l_non_mirroring_size);
 
         // Setting HTM & OCC Base addresses
-        if (l_htmSize < i_procAttrs.iv_occSandboxSize)
+        if ( (l_nhtmSize + l_chtmSize) < i_procAttrs.iv_occSandboxSize)
         {
-            iv_occ_sandbox_base = iv_mem_bases[l_index] +
-                                  iv_memory_sizes[l_index];
-            iv_htm_bar_bases[0] = iv_occ_sandbox_base +
-                                  i_procAttrs.iv_occSandboxSize;
-            iv_htm_bar_bases[1] = iv_htm_bar_bases[0] +
-                                  i_procAttrs.iv_htmBarSizes[0];
+            iv_occ_sandbox_base = iv_mem_bases[l_index] + iv_memory_sizes[l_index];
+            iv_nhtm_bar_base = iv_occ_sandbox_base + i_procAttrs.iv_occSandboxSize;
+            iv_chtm_bar_bases[0] = iv_nhtm_bar_base + i_procAttrs.iv_nhtmBarSize;
+
+            for (uint8_t ii = 1; ii < NUM_OF_CHTM_REGIONS; ii++)
+            {
+                iv_chtm_bar_bases[ii] = iv_chtm_bar_bases[ii - 1] +
+                                        i_procAttrs.iv_chtmBarSizes[ii - 1];
+            }
         }
         else
         {
-            iv_htm_bar_bases[0] = iv_mem_bases[l_index] +
-                                  iv_memory_sizes[l_index];
-            iv_htm_bar_bases[1] = iv_htm_bar_bases[0] +
-                                  i_procAttrs.iv_htmBarSizes[0];
-            iv_occ_sandbox_base = iv_htm_bar_bases[1] +
-                                  i_procAttrs.iv_htmBarSizes[1];
+            iv_nhtm_bar_base = iv_mem_bases[l_index] + iv_memory_sizes[l_index];
+            iv_chtm_bar_bases[0] = iv_nhtm_bar_base + i_procAttrs.iv_nhtmBarSize;
+
+            for (uint8_t ii = 1; ii < NUM_OF_CHTM_REGIONS; ii++)
+            {
+                iv_chtm_bar_bases[ii] = iv_chtm_bar_bases[ii - 1] +
+                                        i_procAttrs.iv_chtmBarSizes[ii - 1];
+            }
+
+            iv_occ_sandbox_base = iv_chtm_bar_bases[23] + i_procAttrs.iv_chtmBarSizes[23];
         }
 
         FAPI_INF("EffGroupingBaseSizeData::set_HTM_OCC_base_addr: NORMAL");
@@ -916,9 +945,14 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr(
                  l_totalSize, l_htmOccSize);
         FAPI_INF("  Index: %d, iv_mem_bases 0x%.16llX, iv_memory_sizes 0x%.16llX",
                  l_index, iv_mem_bases[l_index], iv_memory_sizes[l_index]);
-        FAPI_INF("HTM_BASE[0] 0x%.16llX, HTM_BASE[1] 0x%.16llX, OCC_BASE 0x%.16llX",
-                 iv_htm_bar_bases[0], iv_htm_bar_bases[1],
-                 iv_occ_sandbox_base);
+        FAPI_INF("NHTM_BASE 0x%.16llX", iv_nhtm_bar_base);
+
+        for (uint8_t ii = 0; ii < NUM_OF_CHTM_REGIONS; ii++)
+        {
+            FAPI_INF("CHTM_BASE[%u] 0x%.16llX", ii, iv_chtm_bar_bases[ii]);
+        }
+
+        FAPI_INF("OCC_BASE 0x%.16llX", iv_occ_sandbox_base);
     }
     // MEM_MIRROR_PLACEMENT_POLICY_FLIPPED
     else if (i_sysAttrs.iv_selectiveMode ==
@@ -942,8 +976,8 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr(
         FAPI_ASSERT(l_totalSize >= l_htmOccSize,
                     fapi2::MSS_EFF_GROUPING_NO_SPACE_FOR_HTM_OCC_BAR()
                     .set_TOTAL_SIZE(l_totalSize)
-                    .set_HTM_BAR_SIZE_1(i_procAttrs.iv_htmBarSizes[0])
-                    .set_HTM_BAR_SIZE_2(i_procAttrs.iv_htmBarSizes[1])
+                    .set_NHTM_TOTAL_BAR_SIZE(l_nhtmSize)
+                    .set_CHTM_TOTAL_BAR_SIZE(l_chtmSize)
                     .set_OCC_SANDBOX_BAR_SIZE(i_procAttrs.iv_occSandboxSize)
                     .set_MIRROR_PLACEMENT_POLICY(i_sysAttrs.iv_selectiveMode),
                     "EffGroupingBaseSizeData::set_HTM_OCC_base_addr: Required memory "
@@ -971,8 +1005,8 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr(
             FAPI_ASSERT(iv_mirror_sizes[l_index] >= l_htmOccSize,
                         fapi2::MSS_EFF_GROUPING_HTM_OCC_BAR_NOT_POSSIBLE()
                         .set_TOTAL_SIZE(l_totalSize)
-                        .set_HTM_BAR_SIZE_1(i_procAttrs.iv_htmBarSizes[0])
-                        .set_HTM_BAR_SIZE_2(i_procAttrs.iv_htmBarSizes[1])
+                        .set_NHTM_TOTAL_BAR_SIZE(l_nhtmSize)
+                        .set_CHTM_TOTAL_BAR_SIZE(l_chtmSize)
                         .set_OCC_SANDBOX_BAR_SIZE(i_procAttrs.iv_occSandboxSize)
                         .set_MIRROR_PLACEMENT_POLICY(i_sysAttrs.iv_selectiveMode),
                         "EffGroupingBaseSizeData::set_HTM_OCC_base_addr Memory HTM/OCC "
@@ -994,23 +1028,30 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr(
         iv_mirror_sizes[l_index] = iv_mirror_sizes[l_index] -
                                    (l_temp_size - l_mirroring_size);
 
-        if (l_htmSize < i_procAttrs.iv_occSandboxSize)
+        if ( (l_nhtmSize + l_chtmSize) < i_procAttrs.iv_occSandboxSize)
         {
-            iv_occ_sandbox_base = iv_mirror_bases[l_index] +
-                                  iv_mirror_sizes[l_index];
-            iv_htm_bar_bases[0] = iv_occ_sandbox_base +
-                                  i_procAttrs.iv_occSandboxSize;
-            iv_htm_bar_bases[1] = iv_htm_bar_bases[0] +
-                                  i_procAttrs.iv_htmBarSizes[0];
+            iv_occ_sandbox_base = iv_mirror_bases[l_index] + iv_mirror_sizes[l_index];
+            iv_nhtm_bar_base = iv_occ_sandbox_base + i_procAttrs.iv_occSandboxSize;
+            iv_chtm_bar_bases[0] = iv_nhtm_bar_base + i_procAttrs.iv_nhtmBarSize;
+
+            for (uint8_t ii = 1; ii < NUM_OF_CHTM_REGIONS; ii++)
+            {
+                iv_chtm_bar_bases[ii] = iv_chtm_bar_bases[ii - 1] +
+                                        i_procAttrs.iv_chtmBarSizes[ii - 1];
+            }
         }
         else
         {
-            iv_htm_bar_bases[0] = iv_mirror_bases[l_index] +
-                                  iv_mirror_sizes[l_index];
-            iv_htm_bar_bases[1] = iv_htm_bar_bases[0] +
-                                  i_procAttrs.iv_htmBarSizes[0];
-            iv_occ_sandbox_base = iv_htm_bar_bases[1] +
-                                  i_procAttrs.iv_htmBarSizes[1];
+            iv_nhtm_bar_base = iv_mirror_bases[l_index] + iv_mirror_sizes[l_index];
+            iv_chtm_bar_bases[0] = iv_nhtm_bar_base + i_procAttrs.iv_nhtmBarSize;
+
+            for (uint8_t ii = 1; ii < NUM_OF_CHTM_REGIONS; ii++)
+            {
+                iv_chtm_bar_bases[ii] = iv_chtm_bar_bases[ii - 1] +
+                                        i_procAttrs.iv_chtmBarSizes[ii - 1];
+            }
+
+            iv_occ_sandbox_base = iv_chtm_bar_bases[23] + i_procAttrs.iv_chtmBarSizes[23];
         }
 
         FAPI_INF("EffGroupingBaseSizeData::set_HTM_OCC_base_addr: FLIPPED");
@@ -1019,9 +1060,14 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr(
         FAPI_INF("  Index: %d, iv_mirror_bases 0x%.16llX, "
                  "iv_mirror_sizes 0x%.16llX",
                  l_index, iv_mirror_bases[l_index], iv_mirror_sizes[l_index]);
-        FAPI_INF("HTM_BASE[0] 0x%.16llX, HTM_BASE[1] 0x%.16llX, OCC_BASE 0x%.16llX",
-                 iv_htm_bar_bases[0], iv_htm_bar_bases[1],
-                 iv_occ_sandbox_base);
+        FAPI_INF("NHTM_BASE 0x%.16llX", iv_nhtm_bar_base);
+
+        for (uint8_t ii = 0; ii < NUM_OF_CHTM_REGIONS; ii++)
+        {
+            FAPI_INF("CHTM_BASE[%u] 0x%.16llX", ii, iv_chtm_bar_bases[ii]);
+        }
+
+        FAPI_INF("OCC_BASE 0x%.16llX", iv_occ_sandbox_base);
     }
 
 fapi_try_exit:
@@ -1070,12 +1116,18 @@ fapi2::ReturnCode EffGroupingBaseSizeData::setBaseSizeAttr(
              "Error setting ATTR_MSS_MCS_GROUP_32, l_rc 0x%.8X",
              (uint64_t)fapi2::current_err);
 
-    // Set ATTR_PROC_HTM_BAR_BASE_ADDR
-    FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_HTM_BAR_BASE_ADDR, i_target,
-                           iv_htm_bar_bases),
+    // Set ATTR_PROC_NHTM_BAR_BASE_ADDR
+    FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_NHTM_BAR_BASE_ADDR, i_target,
+                           iv_nhtm_bar_base),
              "Error setting ATTR_PROC_HTM_BAR_BASE_ADDR, "
              "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
 
+    // Set ATTR_PROC_CHTM_BAR_BASE_ADDR
+    FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_CHTM_BAR_BASE_ADDR, i_target,
+                           iv_chtm_bar_bases),
+             "Error setting ATTR_PROC_CHTM_BAR_BASE_ADDR, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+
     // Set ATTR_PROC_OCC_SANDBOX_BASE_ADDR
     FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_OCC_SANDBOX_BASE_ADDR, i_target,
                            iv_occ_sandbox_base),
@@ -1123,8 +1175,13 @@ fapi2::ReturnCode EffGroupingBaseSizeData::setBaseSizeAttr(
         FAPI_INF("ATTR_PROC_MEM_SIZES_ACK[%u]: 0x%.16llX", ii, iv_memory_sizes_ack[ii]);
     }
 
-    FAPI_INF("ATTR_PROC_HTM_BAR_BASE_ADDR[0] : 0x%.16llX", iv_htm_bar_bases[0]);
-    FAPI_INF("ATTR_PROC_HTM_BAR_BASE_ADDR[1] : 0x%.16llX", iv_htm_bar_bases[1]);
+    FAPI_INF("ATTR_PROC_NHTM_BAR_BASE_ADDR : 0x%.16llX", iv_nhtm_bar_base);
+
+    for (uint8_t ii = 0; ii < NUM_OF_CHTM_REGIONS; ii++)
+    {
+        FAPI_INF("ATTR_PROC_CHTM_BAR_BASE_ADDR[%u] : 0x%.16llX", ii, iv_chtm_bar_bases[ii]);
+    }
+
     FAPI_INF("ATTR_PROC_OCC_SANDBOX_BASE_ADDR: 0x%.16llX", iv_occ_sandbox_base);
 
     // Display mirror mode attribute values
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.H b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.H
index e5ed16009..e1e3443e2 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.H
@@ -64,7 +64,7 @@ const uint8_t BASE_ADDR = 3;         // Base Address
 // Number of memory regions
 const uint8_t NUM_NON_MIRROR_REGIONS = 8;
 const uint8_t NUM_MIRROR_REGIONS = 4;
-const uint8_t NUM_OF_HTM_REGIONS = 2; // 2 HTM memory regions
+const uint8_t NUM_OF_CHTM_REGIONS = 24;        // 24 CHTM memory regions
 const uint8_t NUM_OF_ALT_MEM_REGIONS = 2; // 2 memory holes
 
 // ------------------------------------------------------
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
index 342c16821..8520c0368 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
@@ -898,28 +898,73 @@
 </attribute>
 <!-- ********************************************************************** -->
 <attribute>
-  <id>ATTR_PROC_HTM_BAR_BASE_ADDR</id>
+  <id>ATTR_PROC_NHTM_BAR_BASE_ADDR</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> The base addresses where the HTM traces start.  They are
-                calculated based on the HTM trace sizes requested by users.
-                There are two different HTM trace areas, thus two different
-                base addresses.
+  <description> The base address where the NHTM traces start.  They are
+                calculated based on the NHTM trace size requested by user.
+                This address in memory will be the location where NHTM0/1
+                traces are output.
+                Set by p9_mss_eff_grouping.
+                Used by p9_setup_bars and p9_htm_setup.
+  </description>
+  <valueType>uint64</valueType>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************* -->
+<attribute>
+  <id>ATTR_PROC_NHTM_BAR_SIZE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The amount of memory a user can reserve to store NHTM traces.
+                This amount will be used to store both NHTM0 and NHTM1 traces.
+                Used by p9_mss_eff_grouping.
+  </description>
+  <valueType>uint64</valueType>
+  <enum>
+    256_GB = 0x0000004000000000,
+    128_GB = 0x0000002000000000,
+     64_GB = 0x0000001000000000,
+     32_GB = 0x0000000800000000,
+     16_GB = 0x0000000400000000,
+      8_GB = 0x0000000200000000,
+      4_GB = 0x0000000100000000,
+      2_GB = 0x0000000080000000,
+      1_GB = 0x0000000040000000,
+    512_MB = 0x0000000020000000,
+    256_MB = 0x0000000010000000,
+    128_MB = 0x0000000008000000,
+     64_MB = 0x0000000004000000,
+     32_MB = 0x0000000002000000,
+     16_MB = 0x0000000001000000,
+      ZERO = 0x0000000000000000
+  </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_CHTM_BAR_BASE_ADDR</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The base addresses where the CHTM traces start.  They are
+                calculated based on the CHTM trace sizes requested by users.
+                There are 24 different CHTM regions, thus 24 different sizes.
+                Each region is to store HTM trace for a core.
                 Set by p9_mss_eff_grouping.
                 Used by p9_setup_bars.
   </description>
   <valueType>uint64</valueType>
-  <array>2</array>
+  <array>24</array>
   <writeable/>
   <persistRuntime/>
 </attribute>
 <!-- ********************************************************************* -->
 <attribute>
-  <id>ATTR_PROC_HTM_BAR_SIZES</id>
+  <id>ATTR_PROC_CHTM_BAR_SIZES</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> The amount of memory a user can reserve to store HTM traces.
-                There are two different HTM trace areas, thus two different
-                sizes (For example, one to store NHTM0 and one forNHTM1).
-                Set by user via attribute override.
+  <description> The amount of memory a user can reserve to store CHTM traces.
+                There are 24 cores, thus 24 different sizes.
                 Used by p9_mss_eff_grouping.
   </description>
   <valueType>uint64</valueType>
@@ -941,10 +986,12 @@
      16_MB = 0x0000000001000000,
       ZERO = 0x0000000000000000
   </enum>
-  <array>2</array>
+  <array>24</array>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
 </attribute>
+
 <!-- ********************************************************************** -->
 <attribute>
   <id>ATTR_PROC_OCC_SANDBOX_BASE_ADDR</id>
@@ -963,8 +1010,6 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> The amount of memory a user can reserve to store OCC sandbox
                 functions.
-                Platform is to initialize this attribute to 0 (default).
-                Set by user via attribute override.
                 Used by p9_mss_eff_grouping.
   </description>
   <valueType>uint64</valueType>
@@ -986,7 +1031,7 @@
      16_MB = 0x0000000001000000,
       ZERO = 0x0000000000000000
   </enum>
-  <platInit/>
+  <writeable/>
   <persistRuntime/>
 </attribute>
 <!-- ********************************************************************** -->
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_htm_setup_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_htm_setup_attributes.xml
index d1378fdb2..f12661eb6 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_htm_setup_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_htm_setup_attributes.xml
@@ -7,7 +7,7 @@
 <!--                                                                        -->
 <!-- EKB Project                                                            -->
 <!--                                                                        -->
-<!-- COPYRIGHT 2015                                                         -->
+<!-- COPYRIGHT 2015,2016                                                    -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -24,33 +24,27 @@
 <attribute>
   <id>ATTR_NHTM_TRACE_TYPE</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> The Nest HTM trace type desired to be collected.
-                - Platform is to default to DISABLE (0x0).
-                - User can change NHTM trace type (i.e. enable NHTM trace
-                  collection) using Attribute Override.
-                </description>
+  <description> The Nest HTM trace type desired to be collected.  This setting
+                is applied to both NHTM0 and NHTM1.
+  </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, FABRIC = 0x1, EVENT = 0x2, OCC = 0x3 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 <!-- ********************************************************************** -->
 <attribute>
   <id>ATTR_CHTM_TRACE_TYPE</id>
-<!-- TODO: Need to handle CHTM trace targets.
-           See review comments in: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/#/c/21527/ -->
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> The Core HTM trace type desired to be collected.
-                - Platform is to default to DISABLE (0x0)
-                - User can change CHTM trace type (i.e. enable CHTM trace
-                  collection) using Attribute Override.
-                </description>
+  </description>
   <valueType>uint8</valueType>
+  <array>24</array>
   <enum> DISABLE = 0x0, CORE = 0x1, LLAT = 0x2, PPE = 0x3, DMW = 0x4 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <!-- **************************************************
@@ -60,77 +54,74 @@
   <id>ATTR_HTMSC_TTYPEFILT_PAT</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: defines the TTYPE pattern to match in Fabric trace
-                mode.
+                mode.  These bits are used with the ttype Filter Mask to
+                indicate the TTYPE value that should be matched on the rcmd.
                 HTM Ttype Filter Control Register (1:7).
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
   <id>ATTR_HTMSC_TSIZEFILT_PAT</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: defines the TSIZE pattern to match in Fabric trace
-                mode.
+                mode. These bits are used with the tsize filter mask to indicate
+                the TSIZE value that should be matched on the rcmd
                 HTM Ttype Filter Control Register (8:15).
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
+
 <attribute>
   <id>ATTR_HTMSC_TTYPEFILT_MASK</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: TTYPE pattern mask.
-                HTM Ttype Filter Control Register (17:23).
-                If set to 1, do not need to match w/ the pattern.
-                If all mask bits are set, no TTYPE pattern/masking is done
-                - Platform is to default to 0x7F
-                - User can change the value using Attribute Override.
+                If mask bit is clear to 0, then do not need to match w/ the pattern.
+                If all mask bits are clear, no TTYPE pattern/masking is done.
+                The inversion of this attribute value will be programmed into
+                bits 17:23 of HTM Ttype Filter Control Register.
   </description>
   <valueType>uint8</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
   <id>ATTR_HTMSC_TSIZEFILT_MASK</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: TSIZE pattern mask.
-                HTM Ttype Filter Control Register (24:31).
-                If set to 1, do not need to match w/ the Pattern.
-                If all mask bits are set, no TSIZE pattern/masking is done
-                - Platform is to default to 0xFF
-                - User can change the value using Attribute Override.
+                If mask bit is clear to 0, then do not need to match w/ the pattern.
+                If all mask bits are clear, no TSIZE pattern/masking is done.
+                The inversion of this attribute value will be programmed into
+                bits 24:31 of HTM Ttype Filter Control Register.
   </description>
   <valueType>uint8</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
+
 <attribute>
   <id>ATTR_HTMSC_TTYPEFILT_INVERT</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: TTYPE/TSIZE Capture Invert.
                 HTM Ttype Filter Control Register (32).
+                This bit controls the inversion of the ttype/tsize filter.
                 0 : Capture record based on ttype/tsize pattern matching
                 1 : Capture record based on ttype/tsize pattern NOT matching
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> MATCH = 0x0, NOT_MATCH = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -138,16 +129,15 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: CRESP Filter Capture Invert.
                 HTM Ttype Filter Control Register (33).
-                0 : Capture record based on cresp filter pattern matching
-                1 : Capture record based on cresp filter pattern NOT matching
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
+                This bit controls the inversion of the cresp filter.
+                0: Capture record based on cresp filter pattern/mask match
+                1: Capture record based on cresp filter pattern/mask NOT matching.
   </description>
   <valueType>uint8</valueType>
   <enum> MATCH = 0x0, NOT_MATCH = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <!-- **************************************************
@@ -173,13 +163,11 @@
                  In OCC trace mode, defines the occ_trace_data(0:22) pattern
                  to match:
                     0:22  occ_trace_data(0:22) pattern.
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint32</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -187,13 +175,11 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: defines the CRESP Filter pattern in FABRIC trace mode.
                 HTM Filter Control Register (27:31).
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -201,16 +187,27 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM FABRIC: Pattern mask.
                 HTM Filter Control Register (32:54).
-                Bits set to 1 in this mask do not need to match w/ the Filter
-                pattern.
-                If all mask bits are set, No pattern matching is done.
-                - Platform is to default to 0x3FFFFF
-                - User can change the value using Attribute Override.
+                Bits clear to 0 in this mask do not need to match with the
+                Filter Pattern.
+                If all bits are clear, no pattern/masking is done and all
+                Cresp/rcmd are captured in Fabric trace mode and all
+                OCC commands are captured in OCC mode.
+                The inversion of this attribute value will be programmed into
+                bits 32:54 of HTM Ttype Filter Control Register.
+                In Fabric Trace Mode:
+                 32:35: rcmd_ttag(0:3) Group ID Mask
+                 36:38: rcmd_ttag(4:6) Chip ID Mask
+                 39:48: rcmd_ttag(7:16) Unit ID Pattern
+                 49:51: rcmd_scope(0:2) Mask
+                 52:53: rcmd_source(0:1) Mask
+                 54in the : PowerBus PORT MASK (for rcmd and cresp filtering0
+                 In OCC Trace Mode
+                 32:54 occ_trace_data(0:22) Mask
   </description>
   <valueType>uint32</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -218,123 +215,244 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM FABRIC: CRESP Filter Mask.
                 HTM Filter Control Register (59:63).
-                Bits set to 1 in this mask do not need to match w/ the CRESP
+                If mask bit is clear to 0, then do not need to match w/ the CRESP
                 Filter pattern.
-                If all mask bits are set, no pattern matching is done
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
+                If all mask bits are clear, no pattern matching is done.
+                The inversion of this attribute value will be programmed into
+                bits 59:63 of HTM Ttype Filter Control Register.
   </description>
   <valueType>uint8</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <!-- **************************************************
         Attributes for HTM Collection Mode Register
      ************************************************** -->
+
+<!-- **** NHTM attributes only *** 
+-->
 <attribute>
-  <id>ATTR_HTMSC_MODE_CONTENT_SEL</id>
+  <id>ATTR_NHTM_HTMSC_MODE_CONTENT_SEL</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Nest HTM: defines the NHTM trace mode.
                 HTM Collection Mode Register (1:2).
-                - Platform is to default to 0x0 (FABRIC)
-                - User can change the value using Attribute Override.
+                Only FABRIC is supported at this time.
   </description>
   <valueType>uint8</valueType>
   <enum> FABRIC = 0x0, EVENT = 0x1, OCC = 0x2 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Nest HTM: defines if the generated data writes are captured.
+                HTM Collection Mode Register (4).
+                0 - Ignore HTM generated data writes
+                1 - Capture even HTM generated writes if they meet the filtering
+                    criteria.
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Nest HTM: defines if the filtering will apply to ttype=PMISC
+                and ttype=Report Hang commands when filtering is enabled.
+                HTM Collection Mode Register (5).
+                0 - filtering ignored on PMISC
+                1 - Apply filtering to PMISC also
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Nest HTM: defines if Precise cresp mode is enabled.
+                0 - Enable precisce cresp mode
+                1 - Disable precisce cresp mode
+  </description>
+  <valueType>uint8</valueType>
+  <enum> ENABLE = 0x0, DISABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Nest HTM: defines Limit Memory Allocation mode.
+                 0 - Pre-allocate maximum memory buffers (NHTM=8)
+                 1 - Pre-allocate only one half maximum memory buffers
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Nest HTM: defines PMISC only Command trace mode.
+                 0 rCmd amd cResp port 0 only goes to NHTM0
+                 1 rCmd and Cresp port 0 is stored alternately to NHTM0 and
+                   NHTM1, switching based for each valid
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
-</attribute>
-
-<attribute>
-  <id>ATTR_HTMSC_MODE_CAPTURE</id>
-  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> Nest HTM: defines capture mode according to trace mode.
-                HTM Collection Mode Register (4:12).
-                When htm_mode_q(1 TO 2) == 00, i.e. FABRIC
-                  456789012
-                  0xxxx0000 : Ignore HTM generated data writes
-                  1xxxx0000 : Capture htm generated data writes
-                  x0xxx0000 : Filtering ignored on PMISC (always trace PMISC and Report Hang)
-                  x1xxx0000 : Filtering applied on ttype = PMISC and ttype = report hang
-                  xx00x0000 : CRESP Mode: Flush CRESP Queue to avoid overrun (default)
-                  xx01x0000 : CRESP Mode: Reserved
-                  xx10x0000 : CRESP Mode: Enable Precise CRESP Mode
-                  xx11x0000 : CRESP Mode: Ignore CRESP
-                  xxxx00000 : Pre-Allocate maximum memory buffers (8)
-                  xxxx10000 : Pre-Allocate fewer memory buffers (4)
-                When htm_mode_q(1 TO 2) == 01, i.e. OTHER
-                  00000xxxx : Pre-Allocate maximum memory buffers (8)
-                  00001xxxx : Pre-Allocate fewer memory buffers (4)
-                  0000xmmmx : mmm for optional external mux control
-                  0000xxxx0 : Both -other- trace buses to NHTM0
-                  0000xxxx1 : Other trace bus0 to nhtm0, trace bus1 to nhtm1. High BW
-                When htm_mode_q(1 TO 2) == 10, i.e. OCC
-                  00000xxx0 : Pre-Allocate maximum memory buffers (8)
-                  00001xxx0 : Pre-Allocate fewer memory buffers (4)
-                  0000xmmm0 : mmm for optional external mux control
-                - Platform is to default to 0x040 (Precise CRESP, 0b001000000)
-                - User can change the value using Attribute Override.
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_SYNC_STAMP_FORCE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Control the number of cycles to wait to force a synchronization
+                stamp or reset the timer.  For NHTM only.
+                HTM Collection Mode Register (19:21).
+  </description>
+  <valueType>uint8</valueType>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_HTMSC_MODE_WRITETOIO</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Use space option. For NHTM only.
+                HTM Collection Mode Register (22).
+                0 = Use HTM_CL_Write op to target system memory.
+                    Do pre-allocation sequence. (default)
+                1 = Use ci_pr_st op to target anywhere else.
+                    Dont do pre-allocate sequence.
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<!-- **** CHTM attributes only ***
+-->
+<attribute>
+  <id>ATTR_CHTM_HTMSC_MODE_CONTENT_SEL</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Core HTM: defines the CHTM trace mode.
+                HTM Collection Mode Register (1:2).
+                Only Direct Memory Write mode (IMA) is supported at this time.
+  </description>
+  <valueType>uint8</valueType>
+  <enum> CI = 0x0, LLAT = 0x1, PPE = 0x2, DMW = 0x3 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_CHTM_HTMSC_MODE_CAPTURE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Core HTM: defines capture mode according to trace mode.
+                HTM Collection Mode Register (4:9).
+                When htm_mode_q(1 TO 2) == 00, i.e. Core Instruction Trace
+                  00xxxx : tc_pc_trace_active asserted when HTM_STAT[Tracing]=1 to purge the ERAT when entering and exitting trace
+                  01xxxx : tc_pc_trace_active asserted when HTM_MODE[HTM_Trace_enable]=1 to purge the ERAT only at the beginning
+                When htm_mode_q(1 TO 2) == 01, i.e. LLAT Trace
+                  0xxxxx : capture on assertion of l2_htm_llat_disp_req, i.e. any dispatch request
+                  1xxxxx : capture on assertion of l2_htm_llat_disp_req AND l2_llat_htm_rcdisp_occurred, i.e. only on passed dispatch
+                  x0xxxx : capture on assertion of l2_htm_llat_disp_req, i.e. loads or stores
+                  x1xxxx : capture on assertion of l2_htm_llat_disp_req AND l2_llat_htm_rcdisp_ld_not_st, i.e. only loads
+                  xx0xxx : capture on assertion of l2_llat_htm_pbl3hit_dval
+                  xx1xxx : no capture on assertion of l2_llat_htm_pbl3hit_dval - enable embedded timestamp
+                When htm_mode_q(1 TO 2) == 11, i.e. Direct Memory Write
+                  1xxxxx : Enable HPMC-IMA Mode
   </description>
   <valueType>uint32</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
+  <id>ATTR_CHTM_HTMSC_MODE_CORE_INSTR_STALL</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> For CHTM only.
+                 0: Core execution is stalled whenever the data buffers are almost full to prevent losing records.
+                 1: Core execution is never stalled and entries may be discarded when buffer is full
+  </description>
+  <valueType>uint8</valueType>
+  <enum> ENABLE = 0x0, DISABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<!-- **** Common attributes for both NHTM & CHTM ***
+-->
+<attribute>
   <id>ATTR_HTMSC_MODE_WRAP</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> Nest HTM: Trace Wrap mode.
+  <description> Trace Wrap mode, used for both NHTM and CHTM
                 HTM Collection Mode Register (13).
-                0 = Stop trace when top of Trace Memory is reached
-                1 = Wrap trace to beginning of Trace Memory
-                - Platform is to default to 0x1
-                - User can change the value using Attribute Override.
+                0 = Wrap trace to beginning of Trace Memory
+                1 = Stop trace when top of Trace Memory is reached
   </description>
   <valueType>uint8</valueType>
-  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <enum> ENABLE = 0x0, DISABLE = 0x1</enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
   <id>ATTR_HTMSC_MODE_DIS_TSTAMP</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> Nest HTM: TimeStamp Writes option.
+  <description> TimeStamp Writes option, used for both NHTM and CHTM
                 HTM Collection Mode Register (14).
                 0 = Write of timestamps enabled to indicate elapsed time
                     between records.
                 1 = Timestamps written only to indicate record loss
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> ENABLE = 0x0, DISABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
   <id>ATTR_HTMSC_MODE_SINGLE_TSTAMP</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> Nest HTM: Overflow Timestamps option.
+  <description> Overflow Timestamps option, used for both NHTM and CHTM.
                 HTM Collection Mode Register (15).
                 0 = Timestamp written to indicate elapsed time overflow.
                 1 = Only one timestamp is written between entries, overflow
                     indication is lost
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -345,14 +463,12 @@
                 0 = Normal trace
                 1 = Ignore incoming trace data and save only markers caused
                     by HTM_TRIG writes,
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -364,48 +480,12 @@
                 0 = htm write ops sent with group scope
                 1 = htm write ops sent with Vg scope using programmed
                     target bits.
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
-  </description>
-  <valueType>uint8</valueType>
-  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
-  <writeable/>
-  <persistRuntime/>
-  <platInit/>
-</attribute>
-
-<attribute>
-  <id>ATTR_HTMSC_MODE_SYNC_STAMP_FORCE</id>
-  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> Nest HTM: Control the number of cycles to wait to force a
-                synchronization stamp or reset the timer.
-                HTM Collection Mode Register (19:21).
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
-  </description>
-  <valueType>uint8</valueType>
-  <writeable/>
-  <persistRuntime/>
-  <platInit/>
-</attribute>
-
-<attribute>
-  <id>ATTR_HTMSC_MODE_WRITETOIO</id>
-  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> Nest HTM: Use space option.
-                HTM Collection Mode Register (22).
-                0 = Use HTM_CL_Write op to target system memory.
-                    Do pre-allocation sequence. (default)
-                1 = Use ci_pr_st op to target anywhere else.
-                    Dont do pre-allocate sequence.
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -415,13 +495,11 @@
                 HTM Collection Mode Register (24:39).
                 Vg Target bits should be configured if HTM_MEM[scope] is Vg
                 or if Disable Group Scope=1
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint32</valueType>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <!-- ********************************************************
@@ -432,14 +510,12 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Setting of memory scope for HTM collection.
                 HTM Memory Configuration Register (1:3)
-                - Platform is to default to 0x0 (LOCAL).
-                - User can change HTM scope using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> LOCAL = 0x0, NEARNODE = 0x1, GROUP = 0x3, REMOTE = 0x4, VECTORED = 0x5 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -447,21 +523,63 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Setting of memory priority for HTM collection.
                 HTM Memory Configuration Register (4)
-                - Platform is to default to LOW.
-                - User can change MEM_PRIORITY using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> LOW = 0x0, HIGH = 0x1</enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <!-- ********************************************************
         Attributes for HTM Trigger Control Register
      ******************************************************** -->
 <attribute>
-  <id>ATTR_HTMSC_CTRL_TRIG</id>
+  <id>ATTR_NHTM_CTRL_TRIG</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Setting of Trigger control for NHTM.
+                HTM Trigger Control Register (0:1)
+                  00 local triggers are not forwarded to the PowerBus, it is
+                     inserted into the trace when tracing.  Both local and
+                     global triggers control the HTM
+                  01 local triggers are not forwarded to the PowerBus, it is
+                     inserted into the traCe when tracing.  Only local triggers
+                     control the HTM
+                  1x local triggers are forwarded to the PowerBus, it is not
+                     inserted into the trace when tracing.  Only global
+                     triggers control the HTM
+  </description>
+  <valueType>uint8</valueType>
+  <enum> LOCAL_GLOBAL = 0x0, LOCAL = 0x1, GLOBAL = 0x2 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NHTM_CTRL_MARK</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Setting of Mark control for NHTM.
+                HTM Trigger Control Register (4:5)
+                00 local markers are not forwarded to the PowerBus.  Both
+                   local and global markers are inserted into the trace
+                01 local markers are not forwarded to the PowerBus.  Only
+                   local markers are inserted into the trace
+                10 local markers are forwarded to the PowerBus.  Only global
+                   markers are inserted into the trace
+                11 local markers are forwarded to the PowerBus.  Markers
+                   are not inserted into the trace (Fabric Trace Mode)
+  </description>
+  <valueType>uint8</valueType>
+  <enum> LOCAL_GLOBAL = 0x0, LOCAL_MARK = 0x1, GLOBAL_MARK = 0x2,
+         NO_MARK = 0x3 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_CHTM_CTRL_TRIG</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Setting of Trigger control.
                 HTM Trigger Control Register (0:1)
@@ -474,18 +592,16 @@
                   1x local triggers are forwarded to the PowerBus, it is not
                      inserted into the trace when tracing.  Only global
                      triggers control the HTM
-                - Platform is to default to 0x1.
-                - User can change MEM_PRIORITY using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> LOCAL_GLOBAL = 0x0, LOCAL = 0x1, GLOBAL = 0x2 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
-  <id>ATTR_HTMSC_CTRL_MARK</id>
+  <id>ATTR_CHTM_CTRL_MARK</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Setting of Mark control.
                 HTM Trigger Control Register (4:5)
@@ -497,16 +613,13 @@
                    markers are inserted into the trace
                 11 local markers are forwarded to the PowerBus.  Markers
                    are not inserted into the trace (Fabric Trace Mode)
-
-                - Platform is to default to 1.
-                - User can change MEM_PRIORITY using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> LOCAL_GLOBAL = 0x0, LOCAL_MARK = 0x1, GLOBAL_MARK = 0x2,
          NO_MARK = 0x3 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -514,14 +627,12 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Enable Stop on PB Chiplet Debug Trigger 0.
                 HTM Trigger Control Register (6)
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -529,14 +640,12 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Enable Stop on PB Chiplet Debug Trigger 1.
                 HTM Trigger Control Register (7)
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -544,14 +653,12 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Enable trace stop on falling edge of PB chiplet trace run.
                 HTM Trigger Control Register (8)
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -559,14 +666,12 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Enable Stop using OCC Control.
                 HTM Trigger Control Register (9)
-                - Platform is to default to 0x0
-                - User can change the value using Attribute Override.
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 <attribute>
@@ -574,14 +679,96 @@
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> Enable Stop on chiplet XSTOP.
                 HTM Trigger Control Register (13)
-                - Platform is to default to 0x1
-                - User can change the value using Attribute Override.
+                Platform to default to 0x1
+  </description>
+  <valueType>uint8</valueType>
+  <enum> ENABLE = 0x0, DISABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_HTMSC_CTRL_CHIP0_STOP</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Stop on PC_TC_DBG_Trigger0
+                1 = stop trigger Core Debug Trigger 0
+                0 = ignore Core Debug Trigger  0
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_HTMSC_CTRL_CHIP1_STOP</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> Stop on PC_TC_DBG_Trigger1
+                1 = stop trigger Core Debug Trigger 1
+                0 = ignore Core Debug Trigger  1
   </description>
   <valueType>uint8</valueType>
   <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_HTMSC_IMA_PDBAR_SPLIT_CORE_MODE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> This bit controls the indexing of the PDBAR address for the
+                starting address of the write to the PDBAR space.
+                For CHTM only.
+                0 'Big Core' mode.
+                1 'Split Core' mode.
+  </description>
+  <valueType>uint8</valueType>
+  <enum> DISABLE = 0x0, ENABLE = 0x1 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_HTMSC_IMA_PDBAR_SCOPE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>  This register defines the starting Scope of the PowerBus
+                 operation. The Scope will be increased if necessary however
+                 it is more efficient to have the request issued according to
+                 where the target memory is located.
+                     000 LOCAL scope
+                     001 Reserved
+                     010 NEAR NODE scope (Nn)
+                     011 GROUP scope (G).
+                     100 REMOTE scope (Rn).
+                     101 VECTORED group scope (Vg).
+                     110 Reserved
+                     111 Reserved
+                 Note 1: Since P9 uses a Group Class MCD, the HTM will always
+                 force a 'Nodal' scope to 'Group' scope.  If the scope is
+                 initialized to 'Vectored Group Scope', the HTM_MODE[Vg_Target]
+                 bits must also be initialized.
+  </description>
+  <valueType>uint8</valueType>
+  <enum> LOCAL = 0x0, NEARNODE = 0x2, GROUP = 0x3, REMOTE = 0x4, VECTORED = 0x5 </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_HTMSC_IMA_PDBAR_ADDR</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>  IMA Write Physical Base Address
+  </description>
+  <valueType>uint64</valueType>
+  <initToZero/>
+  <initToZero/>
   <writeable/>
   <persistRuntime/>
-  <platInit/>
 </attribute>
 
 </attributes>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_htm_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_htm_setup_errors.xml
index 73f5a420a..ee6fadfae 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_htm_setup_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_htm_setup_errors.xml
@@ -7,7 +7,7 @@
 <!--                                                                        -->
 <!-- EKB Project                                                            -->
 <!--                                                                        -->
-<!-- COPYRIGHT 2015                                                         -->
+<!-- COPYRIGHT 2015,2016                                                    -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -35,17 +35,45 @@
 </hwpError>
 
 <hwpError>
-    <rc>RC_PROC_HTM_CTRL_BAD_STATE</rc>
+    <rc>RC_P9_NHTM_CTRL_BAD_STATE</rc>
     <description>
-        HTM is not at the expected state for current operation.
+        NHTM is not at the expected state for current operation.
     </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>HTM_STATUS_REG_NHTM0</ffdc>
+    <ffdc>HTM_STATUS_REG_NHTM1</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
+</hwpError>
+
+<hwpError>
+    <rc>RC_P9_CHTM_CTRL_BAD_STATE</rc>
+    <description>
+        CHTM is not at the expected state for current operation.
+    </description>
+    <ffdc>TARGET</ffdc>
     <ffdc>HTM_STATUS_REG</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
+</hwpError>
+
+<hwpError>
+    <rc>RC_P9_NHTM_CTRL_TIMEOUT</rc>
+    <description>
+        NHTM state machine change did not complete in allotted time.
+    </description>
     <ffdc>TARGET</ffdc>
+    <ffdc>DELAY_COUNT</ffdc>
+    <ffdc>HTM_STATUS_REG_NHTM0</ffdc>
+    <ffdc>HTM_STATUS_REG_NHTM1</ffdc>
     <callout>
       <procedure>CODE</procedure>
       <priority>LOW</priority>
     </callout>
-    <!-- TODO: Add deconfigure/HW callout -->
 </hwpError>
 
 <hwpError>
@@ -65,6 +93,7 @@
     <description>
         The selected Core HTM trace type is not yet supported.
     </description>
+    <ffdc>CORE_POS</ffdc>
     <ffdc>CHTM_TRACE_TYPE</ffdc>
     <callout>
       <procedure>CODE</procedure>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml
index cf56f37d7..0eb8a4e08 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml
@@ -75,8 +75,8 @@
         Sandbox bar sizes.
     </description>
     <ffdc>TOTAL_SIZE</ffdc>
-    <ffdc>HTM_BAR_SIZE_1</ffdc>
-    <ffdc>HTM_BAR_SIZE_2</ffdc>
+    <ffdc>NHTM_TOTAL_BAR_SIZE</ffdc>
+    <ffdc>CHTM_TOTAL_BAR_SIZE</ffdc>
     <ffdc>OCC_SANDBOX_BAR_SIZE</ffdc>
     <ffdc>MIRROR_PLACEMENT_POLICY</ffdc>
     <callout>
@@ -91,8 +91,8 @@
         HTM and OCC Sandbox bars are not possible.
     </description>
     <ffdc>TOTAL_SIZE</ffdc>
-    <ffdc>HTM_BAR_SIZE_1</ffdc>
-    <ffdc>HTM_BAR_SIZE_2</ffdc>
+    <ffdc>NHTM_TOTAL_BAR_SIZE</ffdc>
+    <ffdc>CHTM_TOTAL_BAR_SIZE</ffdc>
     <ffdc>OCC_SANDBOX_BAR_SIZE</ffdc>
     <ffdc>MIRROR_PLACEMENT_POLICY</ffdc>
     <callout>
diff --git a/src/usr/targeting/attrsync.C b/src/usr/targeting/attrsync.C
index 2cb260881..6b39cbe32 100644
--- a/src/usr/targeting/attrsync.C
+++ b/src/usr/targeting/attrsync.C
@@ -665,7 +665,7 @@ namespace TARGETING
                 (*proc)->setAttr<ATTR_PROC_MEM_BASES>(memBases);
                 uint64_t memSizes[] = {0x800000000,0x0,0x0,0x0,0x0,0x0,0x0,0x0};
                 (*proc)->setAttr<ATTR_PROC_MEM_SIZES>(memSizes);
-                (*proc)->setAttr<ATTR_PROC_HTM_BAR_BASE_ADDR>(0);
+                (*proc)->setAttr<ATTR_PROC_NHTM_BAR_BASE_ADDR>(0);
                 //(*proc)->setAttr<ATTR_PROC_PCIE_LANE_EQUALIZATION>(pcieLane); //defaulted in attribute_types.xml
                 uint8_t mssMem[] = {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0};
                 (*proc)->setAttr<ATTR_MSS_MEM_MC_IN_GROUP>(mssMem);
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 88d3a47d3..140a010ae 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -13780,58 +13780,20 @@ Measured in GB</description>
 </attribute>
 
 <attribute>
-    <id>PROC_HTM_BAR_SIZE</id>
-    <description>Desired HTM trace memory size value
-      creator: platform
-      firmware notes:
-        set by platform to request size of per-chip area reserved
-        for HTM trace memory
-    </description>
-    <simpleType>
-        <uint64_t>
-            <default>0</default>
-        </uint64_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_PROC_HTM_BAR_SIZE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
     <id>PROC_OCC_SANDBOX_SIZE</id>
-    <description>Desired size of OCC sandbox memory region
-      creator: platform
-      firmware notes:
-        set by platform to request size of per-chip area reserved
-        for OCC sandbox function
+    <description> The amount of memory a user can reserve to store OCC sandbox
+                  functions.
+                  Used by p9_mss_eff_grouping.
     </description>
     <simpleType>
         <uint64_t>
-            <default>0</default>
         </uint64_t>
     </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_PROC_OCC_SANDBOX_SIZE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>PROC_HTM_BAR_BASE_ADDR</id>
-    <description>HTM trace memory base address allocated
-    </description>
-    <simpleType><uint64_t></uint64_t></simpleType>
     <persistency>volatile-zeroed</persistency>
     <readable/>
     <writeable/>
     <hwpfToHbAttrMap>
-        <id>ATTR_PROC_HTM_BAR_BASE_ADDR</id>
+        <id>ATTR_PROC_OCC_SANDBOX_SIZE</id>
         <macro>DIRECT</macro>
     </hwpfToHbAttrMap>
 </attribute>
@@ -22106,47 +22068,6 @@ DEPRECATED!!!!
     <macro>DIRECT</macro>
   </hwpfToHbAttrMap>
 </attribute>
-<attribute>
-  <id>PROC_HTM_BAR_SIZES</id>
-  <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> -->
-  <description> The amount of memory a user can reserve to store HTM traces.
-                There are two different HTM trace areas, thus two different
-                sizes (For example, one to store NHTM0 and one for NHTM1).
-                Platform is to initialize this attribute to 0 (default).
-                Set by user via attribute override.
-                Used by p9_mss_eff_grouping.
-                256_GB = 0x0000004000000000,
-                128_GB = 0x0000002000000000,
-                 64_GB = 0x0000001000000000,
-                 32_GB = 0x0000000800000000,
-                 16_GB = 0x0000000400000000,
-                  8_GB = 0x0000000200000000,
-                  4_GB = 0x0000000100000000,
-                  2_GB = 0x0000000080000000,
-                  1_GB = 0x0000000040000000,
-                512_MB = 0x0000000020000000,
-                256_MB = 0x0000000010000000,
-                128_MB = 0x0000000008000000,
-                 64_MB = 0x0000000004000000,
-                 32_MB = 0x0000000002000000,
-                 16_MB = 0x0000000001000000,
-                  ZERO = 0x0000000000000000
-  </description>
-  <simpleType>
-    <uint64_t>
-      <default>0,0</default>
-    </uint64_t>
-    <array>2</array>
-  </simpleType>
-  <writeable/>
-  <persistency>volatile-zeroed</persistency>
-  <readable/>
-  <hwpfToHbAttrMap>
-    <id>ATTR_PROC_HTM_BAR_SIZES</id>
-    <macro>DIRECT</macro>
-  </hwpfToHbAttrMap>
-</attribute>
-
 
 <attribute>
     <id>PROC_PCIE_IOVALID_ENABLE</id>
@@ -23460,790 +23381,6 @@ DEPRECATED!!!!
 </attribute>
 
 <attribute>
-    <id>NHTM_TRACE_TYPE</id>
-    <description>
-      The Nest HTM trace type desired to be collected.
-      - Platform is to default to DISABLE (0x0).
-      - User can change NHTM trace type (i.e. enable NHTM trace
-      collection) using Attribute Override.
-      DISABLE = 0x0, FABRIC = 0x1, EVENT = 0x2, OCC = 0x3
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_NHTM_TRACE_TYPE</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>CHTM_TRACE_TYPE</id>
-    <description>
-      The Core HTM trace type desired to be collected.
-      - Platform is to default to DISABLE (0x0)
-      - User can change CHTM trace type (i.e. enable CHTM trace
-        collection) using Attribute Override.
-        DISABLE = 0x0, CORE = 0x1, LLAT = 0x2, PPE = 0x3, DMW = 0x4
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_CHTM_TRACE_TYPE</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_TTYPEFILT_PAT</id>
-    <description>
-      Nest HTM: defines the TTYPE pattern to match in Fabric trace mode.
-      HTM Ttype Filter Control Register (1:7).
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_TTYPEFILT_PAT</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_TSIZEFILT_PAT</id>
-    <description>
-      Nest HTM: defines the TSIZE pattern to match in Fabric trace mode.
-      HTM Ttype Filter Control Register (8:15).
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_TSIZEFILT_PAT</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_TTYPEFILT_MASK</id>
-    <description>
-      Nest HTM: TTYPE pattern mask.
-      HTM Ttype Filter Control Register (17:23).
-      If set to 1, do not need to match w/ the pattern.
-      If all mask bits are set, no TTYPE pattern/masking is done
-      - Platform is to default to 0x7F
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_TTYPEFILT_MASK</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_TSIZEFILT_MASK</id>
-    <description>
-      Nest HTM: TSIZE pattern mask.
-      HTM Ttype Filter Control Register (24:31).
-      If set to 1, do not need to match w/ the Pattern.
-      If all mask bits are set, no TSIZE pattern/masking is done
-      - Platform is to default to 0xFF
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_TSIZEFILT_MASK</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_TTYPEFILT_INVERT</id>
-    <description>
-      Nest HTM: TTYPE/TSIZE Capture Invert.
-      HTM Ttype Filter Control Register (32).
-      0 : Capture record based on ttype/tsize pattern matching
-      1 : Capture record based on ttype/tsize pattern NOT matching
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_TTYPEFILT_INVERT</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_CRESPFILT_INVERT</id>
-    <description>
-      Nest HTM: CRESP Filter Capture Invert.
-      HTM Ttype Filter Control Register (33).
-      0 : Capture record based on cresp filter pattern matching
-      1 : Capture record based on cresp filter pattern NOT matching
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_CRESPFILT_INVERT</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_FILT_PAT</id>
-    <description>
-      HTM Filter Control Register (0:22).
-      In Fabric trace mode, defines the TTAG/Scope/Source pattern to
-      match in the RCMD and CRESP:
-          0:3   rcmd_ttag(0:2) Group ID Pattern for rcmd and cresp
-                filtering.
-          4:6   rcmd_ttag(3:5) Chip ID Pattern for rcmd and cresp
-                filtering.
-          7:16  rcmd_ttag(6:13) Unit ID Pattern for rcmd and cresp
-                (if from this chip) filtering.
-          17:19 rcmd_scope(0:2) Scope Pattern for rcmd and cresp
-                filtering.
-          20:21 rcmd_source(0:1) Source Pattern for rcmd filtering.
-          22    Powerbus PORT pattern for rcmd and cresp filtering.
-        In OCC trace mode, defines the occ_trace_data(0:22) pattern
-        to match:
-          0:22  occ_trace_data(0:22) pattern.
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint32_t>
-        <default>0</default>
-      </uint32_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_FILT_PAT</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_FILT_CRESP_PAT</id>
-    <description>
-      Nest HTM: defines the CRESP Filter pattern in FABRIC trace mode.
-      HTM Filter Control Register (27:31).
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_FILT_CRESP_PAT</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_FILT_MASK</id>
-    <description>
-      Nest HTM FABRIC: Pattern mask.
-      HTM Filter Control Register (32:54).
-      Bits set to 1 in this mask do not need to match w/ the Filter
-      pattern.
-      If all mask bits are set, No pattern matching is done.
-      - Platform is to default to 0x3FFFFF
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint32_t>
-        <default>0x3FFFFF</default>
-      </uint32_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_FILT_MASK</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_FILT_CRESP_MASK</id>
-    <description>
-      Nest HTM FABRIC: CRESP Filter Mask.
-      HTM Filter Control Register (59:63).
-      Bits set to 1 in this mask do not need to match w/ the CRESP
-      Filter pattern.
-      If all mask bits are set, no pattern matching is done
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_FILT_CRESP_MASK</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_MODE_CONTENT_SEL</id>
-    <description>
-      Nest HTM: defines the NHTM trace mode.
-      HTM Collection Mode Register (1:2).
-      - Platform is to default to 0x0 (FABRIC)
-      - User can change the value using Attribute Override.
-      FABRIC = 0x0, EVENT = 0x1, OCC = 0x2
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_MODE_CONTENT_SEL</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_MODE_CAPTURE</id>
-    <description>
-      Nest HTM: defines capture mode according to trace mode.
-      HTM Collection Mode Register (4:12).
-      When htm_mode_q(1 TO 2) == 00, i.e. FABRIC
-        456789012
-        0xxxx0000 : Ignore HTM generated data writes
-        1xxxx0000 : Capture htm generated data writes
-        x0xxx0000 : Filtering ignored on PMISC (always trace PMISC and Report Hang)
-        x1xxx0000 : Filtering applied on ttype = PMISC and ttype = report hang
-        xx00x0000 : CRESP Mode: Flush CRESP Queue to avoid overrun (default)
-        xx01x0000 : CRESP Mode: Reserved
-        xx10x0000 : CRESP Mode: Enable Precise CRESP Mode
-        xx11x0000 : CRESP Mode: Ignore CRESP
-        xxxx00000 : Pre-Allocate maximum memory buffers (8)
-        xxxx10000 : Pre-Allocate fewer memory buffers (4)
-      When htm_mode_q(1 TO 2) == 01, i.e. OTHER
-        00000xxxx : Pre-Allocate maximum memory buffers (8)
-        00001xxxx : Pre-Allocate fewer memory buffers (4)
-        0000xmmmx : mmm for optional external mux control
-        0000xxxx0 : Both -other- trace buses to NHTM0
-        0000xxxx1 : Other trace bus0 to nhtm0, trace bus1 to nhtm1. High BW
-      When htm_mode_q(1 TO 2) == 10, i.e. OCC
-        00000xxx0 : Pre-Allocate maximum memory buffers (8)
-        00001xxx0 : Pre-Allocate fewer memory buffers (4)
-        0000xmmm0 : mmm for optional external mux control
-      - Platform is to default to 0x040 (Precise CRESP, 0b001000000)
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint32_t>
-        <default>0x040</default>
-      </uint32_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_MODE_CAPTURE</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_MODE_WRAP</id>
-    <description>
-      Nest HTM: Trace Wrap mode.
-      HTM Collection Mode Register (13).
-      0 = Stop trace when top of Trace Memory is reached
-      1 = Wrap trace to beginning of Trace Memory
-      - Platform is to default to 0x1
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint32_t>
-        <default>1</default>
-      </uint32_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_MODE_WRAP</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>ATTR_HTMSC_MODE_DIS_TSTAMP</id>
-    <description>
-      Nest HTM: TimeStamp Writes option.
-      HTM Collection Mode Register (14).
-      0 = Write of timestamps enabled to indicate elapsed time
-          between records.
-      1 = Timestamps written only to indicate record loss
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_MODE_DIS_TSTAMP</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_MODE_SINGLE_TSTAMP</id>
-    <description>
-      Nest HTM: Overflow Timestamps option.
-      HTM Collection Mode Register (15).
-      0 = Timestamp written to indicate elapsed time overflow.
-      1 = Only one timestamp is written between entries, overflow
-          indication is lost
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_MODE_SINGLE_TSTAMP</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_MODE_MARKERS_ONLY</id>
-    <description>
-      Nest HTM: Stamp/Marker only mode.
-      HTM Collection Mode Register (17).
-      0 = Normal trace
-      1 = Ignore incoming trace data and save only markers caused
-          by HTM_TRIG writes,
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_MODE_MARKERS_ONLY</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_MODE_DIS_FORCE_GROUP_SCOPE</id>
-    <description>
-      Nest HTM: Group scope option.
-      HTM Collection Mode Register (18).
-      This is a powerbus debug bit
-      0 = htm write ops sent with group scope
-      1 = htm write ops sent with Vg scope using programmed
-          target bits.
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override..
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_MODE_SYNC_STAMP_FORCE</id>
-    <description>
-      Nest HTM: Control the number of cycles to wait to force a
-      synchronization stamp or reset the timer.
-      HTM Collection Mode Register (19:21).
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_MODE_SYNC_STAMP_FORCE</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_MODE_WRITETOIO</id>
-    <description>
-      Nest HTM: Use space option.
-      HTM Collection Mode Register (22).
-      0 = Use HTM_CL_Write op to target system memory.
-          Do pre-allocation sequence. (default)
-      1 = Use ci_pr_st op to target anywhere else.
-          Dont do pre-allocate sequence.
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_MODE_WRITETOIO</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_MODE_VGTARGET</id>
-    <description>
-      Nest HTM: VG target mode.
-      HTM Collection Mode Register (24:39).
-      Vg Target bits should be configured if HTM_MEM[scope] is Vg
-      or if Disable Group Scope=1
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-    </description>
-    <simpleType>
-      <uint32_t>
-        <default>0</default>
-      </uint32_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_MODE_VGTARGET</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_MEM_SCOPE</id>
-    <description>
-      Setting of memory scope for HTM collection.
-      HTM Memory Configuration Register (1:3)
-      - Platform is to default to 0x0 (LOCAL).
-      - User can change HTM scope using Attribute Override.
-      LOCAL = 0x0, NEARNODE = 0x1, GROUP = 0x3, REMOTE = 0x4, VECTORED = 0x5
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_MEM_SCOPE</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_MEM_PRIORITY</id>
-    <description>
-      Setting of memory priority for HTM collection.
-      HTM Memory Configuration Register (4)
-      - Platform is to default to LOW.
-      - User can change MEM_PRIORITY using Attribute Override.
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_MEM_PRIORITY</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_CTRL_TRIG</id>
-    <description>
-      Setting of Trigger control.
-      HTM Trigger Control Register (0:1)
-        00 local triggers are not forwarded to the PowerBus, it is
-            inserted into the trace when tracing.  Both local and
-            global triggers control the HTM
-        01 local triggers are not forwarded to the PowerBus, it is
-            inserted into the traCe when tracing.  Only local triggers
-            control the HTM
-        1x local triggers are forwarded to the PowerBus, it is not
-            inserted into the trace when tracing.  Only global
-            triggers control the HTM
-      - Platform is to default to 0x1.
-      - User can change MEM_PRIORITY using Attribute Override.
-      LOCAL_GLOBAL = 0x0, LOCAL = 0x1, GLOBAL = 0x2
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>1</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_CTRL_TRIG</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_CTRL_MARK</id>
-    <description>
-      Setting of Mark control.
-      HTM Trigger Control Register (4:5)
-      00 local markers are not forwarded to the PowerBus.  Both
-          local and global markers are inserted into the trace
-      01 local markers are not forwarded to the PowerBus.  Only
-          local markers are inserted into the trace
-      10 local markers are forwarded to the PowerBus.  Only global
-          markers are inserted into the trace
-      11 local markers are forwarded to the PowerBus.  Markers
-          are not inserted into the trace (Fabric Trace Mode)
-
-      - Platform is to default to 1.
-      - User can change MEM_PRIORITY using Attribute Override.
-      LOCAL_GLOBAL = 0x0, LOCAL_MARK = 0x1, GLOBAL_MARK = 0x2,
-      NO_MARK = 0x3
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>1</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_CTRL_MARK</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_CTRL_DBG0_STOP</id>
-    <description>
-      Enable Stop on PB Chiplet Debug Trigger 0.
-      HTM Trigger Control Register (6)
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-      DISABLE = 0x0, ENABLE = 0x1
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_CTRL_DBG0_STOP</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_CTRL_DBG1_STOP</id>
-    <description>
-      Enable Stop on PB Chiplet Debug Trigger 1.
-      HTM Trigger Control Register (7)
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-      DISABLE = 0x0, ENABLE = 0x1
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_CTRL_DBG1_STOP</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_CTRL_RUN_STOP</id>
-    <description>
-      Enable trace stop on falling edge of PB chiplet trace run.
-      HTM Trigger Control Register (8)
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-      DISABLE = 0x0, ENABLE = 0x1
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_CTRL_RUN_STOP</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>ATTR_HTMSC_CTRL_OTHER_DBG0_STOP</id>
-    <description>
-      Enable Stop using OCC Control.
-      HTM Trigger Control Register (9)
-      - Platform is to default to 0x0
-      - User can change the value using Attribute Override.
-      DISABLE = 0x0, ENABLE = 0x1
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>0</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_CTRL_OTHER_DBG0_STOP</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>HTMSC_CTRL_XSTOP_STOP</id>
-    <description>
-      Enable Stop on chiplet XSTOP.
-      HTM Trigger Control Register (13)
-      - Platform is to default to 0x1
-      - User can change the value using Attribute Override.
-      DISABLE = 0x0, ENABLE = 0x1
-    </description>
-    <simpleType>
-      <uint8_t>
-        <default>1</default>
-      </uint8_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_HTMSC_CTRL_XSTOP_STOP</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
     <id>EFF_DRAM_GEN</id>
     <description>
       DRAM Device Type.
@@ -29353,6 +28490,1138 @@ DEPRECATED!!!!
 <!--- TODO: End RTC 155880 workaround -->
 
 <attribute>
+    <id>PROC_NHTM_BAR_BASE_ADDR</id>
+    <description> The base address where the NHTM traces start.  They are
+                  calculated based on the NHTM trace size requested by user.
+                  This address in memory will be the location where NHTM0/1
+                  traces are output.
+                  Set by p9_mss_eff_grouping.
+                  Used by p9_setup_bars and p9_htm_setup.
+    </description>
+    <simpleType><uint64_t></uint64_t></simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_NHTM_BAR_BASE_ADDR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_NHTM_BAR_SIZE</id>
+  <description> The amount of memory a user can reserve to store NHTM traces.
+                This amount will be used to store both NHTM0 and NHTM1 traces.
+                Used by p9_mss_eff_grouping.
+  </description>
+    <simpleType>
+        <uint64_t>
+        </uint64_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_NHTM_BAR_SIZE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_CHTM_BAR_BASE_ADDR</id>
+    <description> The base addresses where the CHTM traces start.  They are
+                  calculated based on the CHTM trace sizes requested by users.
+                  There are 24 different CHTM regions, thus 24 different sizes.
+                  Each region is to store HTM trace for a core.
+                  Set by p9_mss_eff_grouping.
+                  Used by p9_setup_bars.
+    </description>
+    <simpleType>
+      <uint64_t></uint64_t>
+      <array>24</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_CHTM_BAR_BASE_ADDR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_CHTM_BAR_SIZES</id>
+    <description> The amount of memory a user can reserve to store CHTM traces.
+                  There are 24 cores, thus 24 different sizes.
+                  Used by p9_mss_eff_grouping.
+    </description>
+    <simpleType>
+      <uint64_t>
+      </uint64_t>
+      <array>24</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_CHTM_BAR_SIZES</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>NHTM_TRACE_TYPE</id>
+    <description> The Nest HTM trace type desired to be collected.  This setting
+                  is applied to both NHTM0 and NHTM1.
+                  DISABLE = 0x0, FABRIC = 0x1, EVENT = 0x2, OCC = 0x3
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_NHTM_TRACE_TYPE</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>CHTM_TRACE_TYPE</id>
+    <description> The Core HTM trace type desired to be collected.
+                  DISABLE = 0x0, CORE = 0x1, LLAT = 0x2, PPE = 0x3, DMW = 0x4
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+      <array>24</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_CHTM_TRACE_TYPE</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_TTYPEFILT_PAT</id>
+    <description> Nest HTM: defines the TTYPE pattern to match in Fabric trace
+                  mode.  These bits are used with the ttype Filter Mask to
+                  indicate the TTYPE value that should be matched on the rcmd.
+                  HTM Ttype Filter Control Register (1:7).
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_TTYPEFILT_PAT</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_TSIZEFILT_PAT</id>
+    <description> Nest HTM: defines the TSIZE pattern to match in Fabric trace
+                  mode. These bits are used with the tsize filter mask to indicate
+                  the TSIZE value that should be matched on the rcmd
+                  HTM Ttype Filter Control Register (8:15).
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_TSIZEFILT_PAT</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_TTYPEFILT_MASK</id>
+    <description> Nest HTM: TTYPE pattern mask.
+                  If mask bit is clear to 0, then do not need to match w/ the pattern.
+                  If all mask bits are clear, no TTYPE pattern/masking is done.
+                  The inversion of this attribute value will be programmed into
+                  bits 17:23 of HTM Ttype Filter Control Register.
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_TTYPEFILT_MASK</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_TSIZEFILT_MASK</id>
+    <description> Nest HTM: TSIZE pattern mask.
+                  If mask bit is clear to 0, then do not need to match w/ the pattern.
+                  If all mask bits are clear, no TSIZE pattern/masking is done.
+                  The inversion of this attribute value will be programmed into
+                  bits 24:31 of HTM Ttype Filter Control Register.
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_TSIZEFILT_MASK</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_TTYPEFILT_INVERT</id>
+    <description> Nest HTM: TTYPE/TSIZE Capture Invert.
+                  HTM Ttype Filter Control Register (32).
+                  This bit controls the inversion of the ttype/tsize filter.
+                  0 : Capture record based on ttype/tsize pattern matching
+                  1 : Capture record based on ttype/tsize pattern NOT matching
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_TTYPEFILT_INVERT</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_CRESPFILT_INVERT</id>
+    <description> Nest HTM: CRESP Filter Capture Invert.
+                  HTM Ttype Filter Control Register (33).
+                  This bit controls the inversion of the cresp filter.
+                  0: Capture record based on cresp filter pattern/mask match
+                  1: Capture record based on cresp filter pattern/mask NOT matching.
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_CRESPFILT_INVERT</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_FILT_PAT</id>
+    <description> Nest HTM: Filter Pattern.
+                  HTM Filter Control Register (0:22).
+                  In Fabric trace mode, defines the TTAG/Scope/Source pattern to
+                  match in the RCMD and CRESP:
+                      0:3   rcmd_ttag(0:2) Group ID Pattern for rcmd and cresp
+                            filtering.
+                      4:6   rcmd_ttag(3:5) Chip ID Pattern for rcmd and cresp
+                            filtering.
+                      7:16  rcmd_ttag(6:13) Unit ID Pattern for rcmd and cresp
+                            (if from this chip) filtering.
+                      17:19 rcmd_scope(0:2) Scope Pattern for rcmd and cresp
+                            filtering.
+                      20:21 rcmd_source(0:1) Source Pattern for rcmd filtering.
+                      22    Powerbus PORT pattern for rcmd and cresp filtering.
+                   In OCC trace mode, defines the occ_trace_data(0:22) pattern
+                   to match:
+                      0:22  occ_trace_data(0:22) pattern.
+    </description>
+    <simpleType>
+      <uint32_t>
+      </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_FILT_PAT</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_FILT_CRESP_PAT</id>
+    <description> Nest HTM: defines the CRESP Filter pattern in FABRIC trace mode.
+                  HTM Filter Control Register (27:31).
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_FILT_CRESP_PAT</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_FILT_MASK</id>
+    <description> Nest HTM FABRIC: Pattern mask.
+                  HTM Filter Control Register (32:54).
+                  Bits clear to 0 in this mask do not need to match with the
+                  Filter Pattern.
+                  If all bits are clear, no pattern/masking is done and all
+                  Cresp/rcmd are captured in Fabric trace mode and all
+                  OCC commands are captured in OCC mode.
+                  The inversion of this attribute value will be programmed into
+                  bits 32:54 of HTM Ttype Filter Control Register.
+                  In Fabric Trace Mode:
+                   32:35: rcmd_ttag(0:3) Group ID Mask
+                   36:38: rcmd_ttag(4:6) Chip ID Mask
+                   39:48: rcmd_ttag(7:16) Unit ID Pattern
+                   49:51: rcmd_scope(0:2) Mask
+                   52:53: rcmd_source(0:1) Mask
+                   54in the : PowerBus PORT MASK (for rcmd and cresp filtering0
+                   In OCC Trace Mode
+                   32:54 occ_trace_data(0:22) Mask
+    </description>
+    <simpleType>
+      <uint32_t>
+      </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_FILT_MASK</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_FILT_CRESP_MASK</id>
+    <description> Nest HTM FABRIC: CRESP Filter Mask.
+                  HTM Filter Control Register (59:63).
+                  If mask bit is clear to 0, then do not need to match w/ the CRESP
+                  Filter pattern.
+                  If all mask bits are clear, no pattern matching is done.
+                  The inversion of this attribute value will be programmed into
+                  bits 59:63 of HTM Ttype Filter Control Register.
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_FILT_CRESP_MASK</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>NHTM_HTMSC_MODE_CONTENT_SEL</id>
+    <description> Nest HTM: defines the NHTM trace mode.
+                  HTM Collection Mode Register (1:2).
+                  Only FABRIC is supported at this time.
+                  FABRIC = 0x0, EVENT = 0x1, OCC = 0x2
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_NHTM_HTMSC_MODE_CONTENT_SEL</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES</id>
+    <description> Nest HTM: defines if the generated data writes are captured.
+                  HTM Collection Mode Register (4).
+                  0 - Ignore HTM generated data writes
+                  1 - Capture even HTM generated writes if they meet the filtering
+                      criteria.
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL</id>
+    <description> Nest HTM: defines if the filtering will apply to ttype=PMISC
+                  and ttype=Report Hang commands when filtering is enabled.
+                  HTM Collection Mode Register (5).
+                  0 - filtering ignored on PMISC
+                  1 - Apply filtering to PMISC also
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE</id>
+    <description> Nest HTM: defines if Precise cresp mode is disabled.
+                  0 - Disable precisce cresp mode
+                  1 - Enable precisce cresp mode
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION</id>
+    <description> Nest HTM: defines Limit Memory Allocation mode.
+                   0 - Pre-allocate maximum memory buffers (NHTM=8)
+                   1 - Pre-allocate only one half maximum memory buffers
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD</id>
+    <description> Nest HTM: defines PMISC only Command trace mode.
+                   0 rCmd amd cResp port 0 only goes to NHTM0
+                   1 rCmd and Cresp port 0 is stored alternately to NHTM0 and
+                     NHTM1, switching based for each valid
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>NHTM_HTMSC_MODE_SYNC_STAMP_FORCE</id>
+    <description> Control the number of cycles to wait to force a synchronization
+                  stamp or reset the timer.  For NHTM only.
+                  HTM Collection Mode Register (19:21).
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_NHTM_HTMSC_MODE_SYNC_STAMP_FORCE</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>NHTM_HTMSC_MODE_WRITETOIO</id>
+    <description> Use space option. For NHTM only.
+                  HTM Collection Mode Register (22).
+                  0 = Use HTM_CL_Write op to target system memory.
+                      Do pre-allocation sequence. (default)
+                  1 = Use ci_pr_st op to target anywhere else.
+                      Dont do pre-allocate sequence.
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_NHTM_HTMSC_MODE_WRITETOIO</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>CHTM_HTMSC_MODE_CONTENT_SEL</id>
+    <description> Core HTM: defines the CHTM trace mode.
+                  HTM Collection Mode Register (1:2).
+                  Only Direct Memory Write mode (IMA) is supported at this time.
+                  CI = 0x0, LLAT = 0x1, PPE = 0x2, DMW = 0x3
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_CHTM_HTMSC_MODE_CONTENT_SEL</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>CHTM_HTMSC_MODE_CAPTURE</id>
+    <description> Core HTM: defines capture mode according to trace mode.
+                  HTM Collection Mode Register (4:9).
+                  When htm_mode_q(1 TO 2) == 00, i.e. Core Instruction Trace
+                    00xxxx : tc_pc_trace_active asserted when HTM_STAT[Tracing]=1 to purge the ERAT when entering and exitting trace
+                    01xxxx : tc_pc_trace_active asserted when HTM_MODE[HTM_Trace_enable]=1 to purge the ERAT only at the beginning
+                  When htm_mode_q(1 TO 2) == 01, i.e. LLAT Trace
+                    0xxxxx : capture on assertion of l2_htm_llat_disp_req, i.e. any dispatch request
+                    1xxxxx : capture on assertion of l2_htm_llat_disp_req AND l2_llat_htm_rcdisp_occurred, i.e. only on passed dispatch
+                    x0xxxx : capture on assertion of l2_htm_llat_disp_req, i.e. loads or stores
+                    x1xxxx : capture on assertion of l2_htm_llat_disp_req AND l2_llat_htm_rcdisp_ld_not_st, i.e. only loads
+                    xx0xxx : capture on assertion of l2_llat_htm_pbl3hit_dval
+                    xx1xxx : no capture on assertion of l2_llat_htm_pbl3hit_dval - enable embedded timestamp 
+                  When htm_mode_q(1 TO 2) == 11, i.e. Direct Memory Write
+                    1xxxxx : Enable HPMC-IMA Mode         
+    </description>
+    <simpleType>
+      <uint32_t>
+      </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_CHTM_HTMSC_MODE_CAPTURE</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>CHTM_HTMSC_MODE_CORE_INSTR_STALL</id>
+    <description> For CHTM only.
+                   0: Core execution is stalled whenever the data buffers are almost full to prevent losing records.
+                   1: Core execution is never stalled and entries may be discarded when buffer is full
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_CHTM_HTMSC_MODE_CORE_INSTR_STALL</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_MODE_WRAP</id>
+    <description> Trace Wrap mode, used for both NHTM and CHTM
+                  HTM Collection Mode Register (13).
+                  0 = Wrap trace to beginning of Trace Memory
+                  1 = Stop trace when top of Trace Memory is reached
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_MODE_WRAP</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_MODE_DIS_TSTAMP</id>
+    <description> TimeStamp Writes option, used for both NHTM and CHTM
+                  HTM Collection Mode Register (14).
+                  0 = Write of timestamps enabled to indicate elapsed time
+                      between records.
+                  1 = Timestamps written only to indicate record loss
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_MODE_DIS_TSTAMP</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_MODE_SINGLE_TSTAMP</id>
+    <description> Overflow Timestamps option, used for both NHTM and CHTM.
+                  HTM Collection Mode Register (15).
+                  0 = Timestamp written to indicate elapsed time overflow.
+                  1 = Only one timestamp is written between entries, overflow
+                      indication is lost
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_MODE_SINGLE_TSTAMP</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_MODE_MARKERS_ONLY</id>
+    <description> Nest HTM: Stamp/Marker only mode.
+                  HTM Collection Mode Register (17).
+                  0 = Normal trace
+                  1 = Ignore incoming trace data and save only markers caused
+                      by HTM_TRIG writes,
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_MODE_MARKERS_ONLY</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_MODE_DIS_FORCE_GROUP_SCOPE</id>
+    <description> Nest HTM: Group scope option.
+                  HTM Collection Mode Register (18).
+                  This is a powerbus debug bit
+                  0 = htm write ops sent with group scope
+                  1 = htm write ops sent with Vg scope using programmed
+                      target bits.
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_MODE_VGTARGET</id>
+    <description> Nest HTM: VG target mode.
+                  HTM Collection Mode Register (24:39).
+                  Vg Target bits should be configured if HTM_MEM[scope] is Vg
+                  or if Disable Group Scope=1
+    </description>
+    <simpleType>
+      <uint32_t>
+      </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_MODE_VGTARGET</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_MEM_SCOPE</id>
+    <description> Setting of memory scope for HTM collection.
+                  HTM Memory Configuration Register (1:3)
+                  LOCAL = 0x0, NEARNODE = 0x1, GROUP = 0x3, REMOTE = 0x4, VECTORED = 0x5
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_MEM_SCOPE</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_MEM_PRIORITY</id>
+    <description> Setting of memory priority for HTM collection.
+                  HTM Memory Configuration Register (4)
+                  LOW = 0x0, HIGH = 0x1
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_MEM_PRIORITY</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>NHTM_CTRL_TRIG</id>
+    <description> Setting of Trigger control for NHTM.
+                  HTM Trigger Control Register (0:1)
+                    00 local triggers are not forwarded to the PowerBus, it is
+                       inserted into the trace when tracing.  Both local and
+                       global triggers control the HTM
+                    01 local triggers are not forwarded to the PowerBus, it is
+                       inserted into the traCe when tracing.  Only local triggers
+                       control the HTM
+                    1x local triggers are forwarded to the PowerBus, it is not
+                       inserted into the trace when tracing.  Only global
+                       triggers control the HTM
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <writeable/>
+    <readable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_NHTM_CTRL_TRIG</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>NHTM_CTRL_MARK</id>
+    <description> Setting of Mark control for NHTM.
+                  HTM Trigger Control Register (4:5)
+                  00 local markers are not forwarded to the PowerBus.  Both
+                     local and global markers are inserted into the trace
+                  01 local markers are not forwarded to the PowerBus.  Only
+                     local markers are inserted into the trace
+                  10 local markers are forwarded to the PowerBus.  Only global
+                     markers are inserted into the trace
+                  11 local markers are forwarded to the PowerBus.  Markers
+                     are not inserted into the trace (Fabric Trace Mode)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_NHTM_CTRL_MARK</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>CHTM_CTRL_TRIG</id>
+    <description> Setting of Trigger control.
+                  HTM Trigger Control Register (0:1)
+                    00 local triggers are not forwarded to the PowerBus, it is
+                       inserted into the trace when tracing.  Both local and
+                       global triggers control the HTM
+                    01 local triggers are not forwarded to the PowerBus, it is
+                       inserted into the traCe when tracing.  Only local triggers
+                       control the HTM
+                    1x local triggers are forwarded to the PowerBus, it is not
+                       inserted into the trace when tracing.  Only global
+                       triggers control the HTM
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <writeable/>
+    <readable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_CHTM_CTRL_TRIG</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>CHTM_CTRL_MARK</id>
+    <description> Setting of Mark control.
+                  HTM Trigger Control Register (4:5)
+                  00 local markers are not forwarded to the PowerBus.  Both
+                     local and global markers are inserted into the trace
+                  01 local markers are not forwarded to the PowerBus.  Only
+                     local markers are inserted into the trace
+                  10 local markers are forwarded to the PowerBus.  Only global
+                     markers are inserted into the trace
+                  11 local markers are forwarded to the PowerBus.  Markers
+                     are not inserted into the trace (Fabric Trace Mode)
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_CHTM_CTRL_MARK</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_CTRL_DBG0_STOP</id>
+    <description> Enable Stop on PB Chiplet Debug Trigger 0.
+                  HTM Trigger Control Register (6)
+                  DISABLE = 0x0, ENABLE = 0x1
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_CTRL_DBG0_STOP</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_CTRL_DBG1_STOP</id>
+    <description> Enable Stop on PB Chiplet Debug Trigger 1.
+                  HTM Trigger Control Register (7)
+                  DISABLE = 0x0, ENABLE = 0x1
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_CTRL_DBG1_STOP</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_CTRL_RUN_STOP</id>
+    <description> Enable trace stop on falling edge of PB chiplet trace run.
+                  HTM Trigger Control Register (8)
+                  DISABLE = 0x0, ENABLE = 0x1
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_CTRL_RUN_STOP</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_CTRL_OTHER_DBG0_STOP</id>
+    <description> Enable Stop using OCC Control.
+                  HTM Trigger Control Register (9)
+                  DISABLE = 0x0, ENABLE = 0x1
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_CTRL_OTHER_DBG0_STOP</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_CTRL_XSTOP_STOP</id>
+    <description> Enable Stop on chiplet XSTOP.
+                  HTM Trigger Control Register (13)
+                  ENABLE = 0x0, DISABLE = 0x1
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_CTRL_XSTOP_STOP</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_CTRL_CHIP0_STOP</id>
+    <description> Stop on PC_TC_DBG_Trigger0
+                  1 = stop trigger Core Debug Trigger 0
+                  0 = ignore Core Debug Trigger  0
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_CTRL_CHIP0_STOP</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_CTRL_CHIP1_STOP</id>
+    <description> Stop on PC_TC_DBG_Trigger1
+                  1 = stop trigger Core Debug Trigger 1
+                  0 = ignore Core Debug Trigger  1
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_CTRL_CHIP1_STOP</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_IMA_PDBAR_SPLIT_CORE_MODE</id>
+    <description> This bit controls the indexing of the PDBAR address for the
+                  starting address of the write to the PDBAR space.
+                  For CHTM only.
+                  0 'Big Core' mode.
+                  1 'Split Core' mode.
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_IMA_PDBAR_SPLIT_CORE_MODE</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_IMA_PDBAR_SCOPE</id>
+    <description>  This register defines the starting Scope of the PowerBus
+                   operation. The Scope will be increased if necessary however
+                   it is more efficient to have the request issued according to
+                   where the target memory is located.
+                       000 LOCAL scope
+                       001 Reserved
+                       010 NEAR NODE scope (Nn)
+                       011 GROUP scope (G).
+                       100 REMOTE scope (Rn).
+                       101 VECTORED group scope (Vg).
+                       110 Reserved
+                       111 Reserved
+                   Note 1: Since P9 uses a Group Class MCD, the HTM will always
+                   force a 'Nodal' scope to 'Group' scope.  If the scope is
+                   initialized to 'Vectored Group Scope', the HTM_MODE[Vg_Target]
+                   bits must also be initialized.
+    </description>
+    <simpleType>
+      <uint8_t>
+      </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_IMA_PDBAR_SCOPE</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>HTMSC_IMA_PDBAR_ADDR</id>
+    <description>  IMA Write Physical Base Address  
+    </description>
+    <simpleType>
+      <uint64_t>
+      </uint64_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+      <id>ATTR_HTMSC_IMA_PDBAR_ADDR</id>
+      <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<!-- TODO: RTC 156244 - To be removed -->
+
+<attribute>
+    <id>PROC_HTM_BAR_SIZE</id>
+    <description>Desired HTM trace memory size value
+      creator: platform
+      firmware notes:
+        set by platform to request size of per-chip area reserved
+        for HTM trace memory
+    </description>
+    <simpleType>
+        <uint64_t>
+            <default>0</default>
+        </uint64_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_HTM_BAR_SIZE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_HTM_BAR_BASE_ADDR</id>
+    <description>HTM trace memory base address allocated
+    </description>
+    <simpleType><uint64_t></uint64_t></simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_HTM_BAR_BASE_ADDR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_HTM_BAR_SIZES</id>
+  <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> -->
+  <description> The amount of memory a user can reserve to store HTM traces.
+                There are two different HTM trace areas, thus two different
+                sizes (For example, one to store NHTM0 and one for NHTM1).
+                Platform is to initialize this attribute to 0 (default).
+                Set by user via attribute override.
+                Used by p9_mss_eff_grouping.
+                256_GB = 0x0000004000000000,
+                128_GB = 0x0000002000000000,
+                 64_GB = 0x0000001000000000,
+                 32_GB = 0x0000000800000000,
+                 16_GB = 0x0000000400000000,
+                  8_GB = 0x0000000200000000,
+                  4_GB = 0x0000000100000000,
+                  2_GB = 0x0000000080000000,
+                  1_GB = 0x0000000040000000,
+                512_MB = 0x0000000020000000,
+                256_MB = 0x0000000010000000,
+                128_MB = 0x0000000008000000,
+                 64_MB = 0x0000000004000000,
+                 32_MB = 0x0000000002000000,
+                 16_MB = 0x0000000001000000,
+                  ZERO = 0x0000000000000000
+  </description>
+  <simpleType>
+    <uint64_t>
+      <default>0,0</default>
+    </uint64_t>
+    <array>2</array>
+  </simpleType>
+  <writeable/>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+    <id>ATTR_PROC_HTM_BAR_SIZES</id>
+    <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<!-- End TODO: RTC 156244 -->
+
+<attribute>
   <id>MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP</id>
   <description>
     Selects the number of enabled pullup branches during READ mode.
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index a24ea7710..9afb0cb31 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -149,7 +149,6 @@
     <attribute><id>PROC_L3_BAR_GROUP_MASK_REG</id></attribute>
     <!--   proc_fab_smp_fabric_attributes.xml  -->
     <attribute><id>PROC_PCIE_NOT_F_LINK</id></attribute>
-    <attribute><id>MSS_INTERLEAVE_ENABLE</id></attribute>
     <attribute><id>MSS_MCS_GROUP_32</id></attribute>
     <attribute><id>MSS_MEM_IPL_COMPLETE</id></attribute>
     <!-- Start pm_plat_attributes.xml -->
@@ -278,7 +277,6 @@
     <attribute><id>PROC_R_LOADLINE_VCS</id></attribute>
     <attribute><id>PROC_R_DISTLOSS_VCS</id></attribute>
     <attribute><id>PROC_VRM_VOFFSET_VCS</id></attribute>
-    <attribute><id>PROC_HTM_BAR_BASE_ADDR</id></attribute>
     <attribute><id>ICACHE_LINE_SIZE</id></attribute>
     <attribute><id>ICACHE_ASSOC_SETS</id></attribute>
     <attribute><id>ICACHE_SIZE</id></attribute>
@@ -309,10 +307,6 @@
     <attribute><id>PROC_FABRIC_X_ATTACHED_CHIP_ID</id></attribute>
     <attribute><id>PROC_FABRIC_A_ADDR_DIS</id></attribute>
     <attribute><id>PROC_FABRIC_X_ADDR_DIS</id></attribute>
-    <attribute><id>PROC_FABRIC_SYSTEM_ID</id></attribute>
-    <attribute><id>PROC_OCC_SANDBOX_BASE_ADDR</id></attribute>
-    <attribute><id>PROC_HTM_BAR_SIZES</id></attribute>
-
     <attribute><id>PROC_PCIE_HOTPLUG_I2C_DEVICE_ADDRESS</id></attribute>
     <attribute><id>PROC_PCIE_HOTPLUG_ENABLE_ACTIONS</id></attribute>
     <attribute><id>PROC_PCIE_HOTPLUG_NUM_ENABLE_ACTIONS</id></attribute>
@@ -931,7 +925,6 @@
     <attribute><id>PROC_PCIE_IOP_TX_FFE_GEN1</id></attribute>
     <attribute><id>PROC_PCIE_IOP_TX_FFE_GEN2</id></attribute>
     <attribute><id>PROC_PCIE_PHB_ACTIVE</id></attribute>
-    <attribute><id>PROC_HTM_BAR_SIZE</id></attribute>
     <attribute><id>XSCOM_BASE_ADDRESS</id></attribute>
     <attribute><id>PSTATEGPE_BOOT_COPIER_IVPR_OFFSET</id></attribute>
     <attribute><id>STOPGPE_BOOT_COPIER_IVPR_OFFSET</id></attribute>
@@ -948,8 +941,6 @@
     <attribute><id>BOOT_FREQ_MULT</id></attribute>
     <attribute><id>PFET_OFF_CONTROLS</id></attribute>
     <attribute><id>MC_SYNC_MODE</id></attribute>
-    <attribute><id>NHTM_TRACE_TYPE</id></attribute>
-    <attribute><id>CHTM_TRACE_TYPE</id></attribute>
     <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute>
     <!-- proc_fbc_eff_config_links -->
     <attribute><id>PROC_FABRIC_X_ATTACHED_LINK_ID</id></attribute>
@@ -965,6 +956,64 @@
     <!-- End proc_fbc_eff_config_links -->
     <attribute><id>FSI_GP_SHADOWS_OVERWRITE</id></attribute>
     <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute>
+    <attribute><id>PROC_NHTM_BAR_BASE_ADDR</id></attribute>
+    <attribute><id>PROC_NHTM_BAR_SIZE</id></attribute>
+    <attribute><id>PROC_CHTM_BAR_BASE_ADDR</id></attribute>
+    <attribute><id>PROC_CHTM_BAR_SIZES</id></attribute>
+    <attribute><id>NHTM_TRACE_TYPE</id></attribute>
+    <attribute><id>CHTM_TRACE_TYPE</id></attribute>
+    <attribute><id>HTMSC_TTYPEFILT_PAT</id></attribute>
+    <attribute><id>HTMSC_TSIZEFILT_PAT</id></attribute>
+    <attribute><id>HTMSC_TTYPEFILT_MASK</id></attribute>
+    <attribute><id>HTMSC_TSIZEFILT_MASK</id></attribute>
+    <attribute><id>HTMSC_TTYPEFILT_INVERT</id></attribute>
+    <attribute><id>HTMSC_CRESPFILT_INVERT</id></attribute>
+    <attribute><id>HTMSC_FILT_PAT</id></attribute>
+    <attribute><id>HTMSC_FILT_CRESP_PAT</id></attribute>
+    <attribute><id>HTMSC_FILT_MASK</id></attribute>
+    <attribute><id>HTMSC_FILT_CRESP_MASK</id></attribute>
+    <attribute><id>NHTM_HTMSC_MODE_CONTENT_SEL</id></attribute>
+    <attribute><id>NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES</id></attribute>
+    <attribute><id>NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL</id></attribute>
+    <attribute><id>NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE</id></attribute>
+    <attribute><id>NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION</id></attribute>
+    <attribute><id>NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD</id></attribute>
+    <attribute><id>NHTM_HTMSC_MODE_SYNC_STAMP_FORCE</id></attribute>
+    <attribute><id>NHTM_HTMSC_MODE_WRITETOIO</id></attribute>
+    <attribute><id>CHTM_HTMSC_MODE_CONTENT_SEL</id></attribute>
+    <attribute><id>CHTM_HTMSC_MODE_CAPTURE</id></attribute>
+    <attribute><id>CHTM_HTMSC_MODE_CORE_INSTR_STALL</id></attribute>
+    <attribute><id>HTMSC_MODE_WRAP</id></attribute>
+    <attribute><id>HTMSC_MODE_DIS_TSTAMP</id></attribute>
+    <attribute><id>HTMSC_MODE_SINGLE_TSTAMP</id></attribute>
+    <attribute><id>HTMSC_MODE_MARKERS_ONLY</id></attribute>
+    <attribute><id>HTMSC_MODE_DIS_FORCE_GROUP_SCOPE</id></attribute>
+    <attribute><id>HTMSC_MODE_VGTARGET</id></attribute>
+    <attribute><id>HTMSC_MEM_SCOPE</id></attribute>
+    <attribute><id>HTMSC_MEM_PRIORITY</id></attribute>
+    <attribute><id>NHTM_CTRL_TRIG</id></attribute>
+    <attribute><id>NHTM_CTRL_MARK</id></attribute>
+    <attribute><id>CHTM_CTRL_TRIG</id></attribute>
+    <attribute><id>CHTM_CTRL_MARK</id></attribute>
+    <attribute><id>HTMSC_CTRL_DBG0_STOP</id></attribute>
+    <attribute><id>HTMSC_CTRL_DBG1_STOP</id></attribute>
+    <attribute><id>HTMSC_CTRL_RUN_STOP</id></attribute>
+    <attribute><id>HTMSC_CTRL_OTHER_DBG0_STOP</id></attribute>
+    <attribute><id>HTMSC_CTRL_XSTOP_STOP</id></attribute>
+    <attribute><id>HTMSC_CTRL_CHIP0_STOP</id></attribute>
+    <attribute><id>HTMSC_CTRL_CHIP1_STOP</id></attribute>
+    <attribute><id>HTMSC_IMA_PDBAR_SPLIT_CORE_MODE</id></attribute>
+    <attribute><id>HTMSC_IMA_PDBAR_SCOPE</id></attribute>
+    <attribute><id>HTMSC_IMA_PDBAR_ADDR</id></attribute>
+    <attribute><id>PROC_FABRIC_SYSTEM_ID</id></attribute>
+    <attribute><id>PROC_OCC_SANDBOX_BASE_ADDR</id></attribute>
+
+<!-- TODO: RTC 156244 - To be removed -->
+    <attribute><id>PROC_HTM_BAR_SIZE</id></attribute>
+    <attribute><id>PROC_HTM_BAR_BASE_ADDR</id></attribute>
+    <attribute><id>PROC_HTM_BAR_SIZES</id></attribute>
+<!-- End TODO: RTC 156244 -->
+
 </targetType>
 
 <!-- chip-processor-nimbus -->