diff options
| author | Thi Tran <thi@us.ibm.com> | 2016-09-23 14:56:59 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-09-26 11:31:43 -0400 |
| commit | aa07e5cb4b5cb7020c946e24f28e225e5feda5a0 (patch) | |
| tree | de10a157ba8f086a2441a9ad6b423022af94d7ad /src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml | |
| parent | 76bc23a4040926fc0038811dfaa93af18cad18ec (diff) | |
| download | talos-hostboot-aa07e5cb4b5cb7020c946e24f28e225e5feda5a0.tar.gz talos-hostboot-aa07e5cb4b5cb7020c946e24f28e225e5feda5a0.zip | |
Fix MCFGP table look up when MCA is garded out
Also fix incorrect description of ATTR_MSS_MEM_MC_IN_GROUP
Change-Id: I7c793373b5c124c56ab9caa30dcc7e5cfe7253ca
CQ:SW366015
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30193
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30195
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 6d03bc85a..68d655d8c 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -878,14 +878,14 @@ <id>ATTR_MSS_MEM_MC_IN_GROUP</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - An 8 bit vector that would be a designation of which MC (Nimbus MCS or + An 8 bit vector that would be a designation of which MC (Nimbus MCA or Cumulus MI) are involved in the group. So the bits would represent Nimbus Cumulus - Bit 0 MCS0 MI0 - Bit 1 MCS1 MI1 + Bit 0 MCA0 MI0 + Bit 1 MCA1 MI1 ..... - Bit 7 MCS7 MI7 + Bit 7 MCA7 MI7 Set by p9_mss_eff_grouping </description> <valueType>uint8</valueType> |
