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authorThi Tran <thi@us.ibm.com>2016-09-23 14:56:59 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-09-26 11:31:43 -0400
commitaa07e5cb4b5cb7020c946e24f28e225e5feda5a0 (patch)
treede10a157ba8f086a2441a9ad6b423022af94d7ad /src/import
parent76bc23a4040926fc0038811dfaa93af18cad18ec (diff)
downloadtalos-hostboot-aa07e5cb4b5cb7020c946e24f28e225e5feda5a0.tar.gz
talos-hostboot-aa07e5cb4b5cb7020c946e24f28e225e5feda5a0.zip
Fix MCFGP table look up when MCA is garded out
Also fix incorrect description of ATTR_MSS_MEM_MC_IN_GROUP Change-Id: I7c793373b5c124c56ab9caa30dcc7e5cfe7253ca CQ:SW366015 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30193 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30195 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import')
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C77
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml8
2 files changed, 48 insertions, 37 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C
index cfb2772bc..81617f278 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C
@@ -71,17 +71,13 @@ static const struct channelPerGroupTable_t
} CHANNEL_PER_GROUP_TABLE[] =
{
// Port 0 Port 1 Channel/group value
- { 1, 0, 0b0000 }, // 1 MC port/group for port0, port1 is not populated.
{ 1, 1, 0b0000 }, // 1 MC port/group for both port0 and port1
{ 1, 3, 0b0001 }, // 1 MC port/group for port0, 3 MC port/group for port1
- { 0, 1, 0b0000 }, // 1 MC port/group for port1, port0 is not populated.
{ 2, 1, 0b0100 }, // 2 MC port/group different MC port pairs
{ 3, 1, 0b0010 }, // 3 MC port/group for port0, 1 MC port/group for port1
{ 3, 3, 0b0011 }, // 3 MC port/group for port0, 3 MC port/group for port1
- { 2, 0, 0b0100 }, // 2 MC port/group different MC port pairs
{ 2, 2, 0b0101 }, // 2 MC port/group in the same MC port pairs (Need additional verification in code below)
{ 2, 3, 0b0100 }, // 2 MC port/group different MC port pairs
- { 0, 2, 0b0100 }, // 2 MC port/group different MC port pairs
{ 1, 2, 0b0100 }, // 2 MC port/group different MC port pairs
{ 3, 2, 0b0100 }, // 2 MC port/group different MC port pairs
{ 4, 4, 0b0110 }, // 4 MC ports/group, two ports in the same MC pairs
@@ -460,8 +456,24 @@ fapi2::ReturnCode getBarData(const mcsPortGroupInfo_t i_portInfo[],
ii < (sizeof(CHANNEL_PER_GROUP_TABLE) / sizeof(channelPerGroupTable_t));
ii++)
{
- if ( (i_portInfo[0].numPortsInGroup == CHANNEL_PER_GROUP_TABLE[ii].port0_ports_in_group) &&
- (i_portInfo[1].numPortsInGroup == CHANNEL_PER_GROUP_TABLE[ii].port1_ports_in_group) )
+ uint8_t l_port0_lookup_val = i_portInfo[0].numPortsInGroup;
+ uint8_t l_port1_lookup_val = i_portInfo[1].numPortsInGroup;
+
+ // If port is disabled, treat as single port. However, this
+ // port will be set invalid in MCFGP reg further below
+ //
+ if (l_port0_lookup_val == 0)
+ {
+ l_port0_lookup_val = 1;
+ }
+
+ if (l_port1_lookup_val == 0)
+ {
+ l_port1_lookup_val = 1;
+ }
+
+ if ( (l_port0_lookup_val == CHANNEL_PER_GROUP_TABLE[ii].port0_ports_in_group) &&
+ (l_port1_lookup_val == CHANNEL_PER_GROUP_TABLE[ii].port1_ports_in_group) )
{
o_mcsBarData.MCFGP_chan_per_group = CHANNEL_PER_GROUP_TABLE[ii].channel_per_group;
}
@@ -475,8 +487,7 @@ fapi2::ReturnCode getBarData(const mcsPortGroupInfo_t i_portInfo[],
.set_PORT_1_PORTS_IN_GROUP(i_portInfo[1].numPortsInGroup)
.set_PORT_1_GROUP(i_portInfo[1].myGroup),
"Error: ports 0/1 config doesn't match any entry in Channel/group table. "
- "Port_0: group %u, ports in group %u",
- "Port_1: group %u, ports in group %u",
+ "Port_0: group %u, ports in group %u, Port_1: group %u, ports in group %u",
i_portInfo[0].myGroup, i_portInfo[0].numPortsInGroup,
i_portInfo[1].myGroup, i_portInfo[1].numPortsInGroup);
@@ -621,18 +632,18 @@ void displayMCPortInfoData(const fapi2::Target<fapi2::TARGET_TYPE_MCS> i_mcTarge
{
for (uint8_t ii = 0; ii < MAX_MC_PORTS_PER_MCS; ii++)
{
- FAPI_DBG(" Port %u:", ii);
- FAPI_DBG(" myGroup %u", i_portInfo[ii].myGroup);
- FAPI_DBG(" numPortsInGroup %u", i_portInfo[ii].numPortsInGroup);
- FAPI_DBG(" groupSize %u", i_portInfo[ii].groupSize);
- FAPI_DBG(" groupBaseAddr %u", i_portInfo[ii].groupBaseAddr);
- FAPI_DBG(" channelId %u", i_portInfo[ii].channelId);
+ FAPI_INF(" Port %u:", ii);
+ FAPI_INF(" myGroup %u", i_portInfo[ii].myGroup);
+ FAPI_INF(" numPortsInGroup %u", i_portInfo[ii].numPortsInGroup);
+ FAPI_INF(" groupSize %u", i_portInfo[ii].groupSize);
+ FAPI_INF(" groupBaseAddr %u", i_portInfo[ii].groupBaseAddr);
+ FAPI_INF(" channelId %u", i_portInfo[ii].channelId);
for (uint8_t jj = 0; jj < MAX_ALT_MEM_REGIONS; jj++)
{
- FAPI_DBG(" altMemValid[%u] %u", jj, i_portInfo[ii].altMemValid[jj]);
- FAPI_DBG(" altMemSize[%u] %u", jj, i_portInfo[ii].altMemSize[jj]);
- FAPI_DBG(" altBaseAddr[%u] %u", jj, i_portInfo[ii].altBaseAddr[jj]);
+ FAPI_INF(" altMemValid[%u] %u", jj, i_portInfo[ii].altMemValid[jj]);
+ FAPI_INF(" altMemSize[%u] %u", jj, i_portInfo[ii].altMemSize[jj]);
+ FAPI_INF(" altBaseAddr[%u] %u", jj, i_portInfo[ii].altBaseAddr[jj]);
}
}
@@ -666,26 +677,26 @@ template<> // TARGET_TYPE_MCS
void displayMCBarData(const fapi2::Target<fapi2::TARGET_TYPE_MCS> i_mcTarget,
const mcsBarData_t i_mcBarData)
{
- FAPI_DBG(" BAR data:");
- FAPI_DBG(" MCS_MCFGP_VALID %u", i_mcBarData.MCS_MCFGP_VALID);
- FAPI_DBG(" MCFGP_chan_per_group %u", i_mcBarData.MCFGP_chan_per_group);
- FAPI_DBG(" MCFGP_chan0_group_member_id %u", i_mcBarData.MCFGP_chan0_group_member_id);
- FAPI_DBG(" MCFGP_chan1_group_member_id %u", i_mcBarData.MCFGP_chan1_group_member_id);
- FAPI_DBG(" MCFGP_group_size %u", i_mcBarData.MCFGP_group_size);
- FAPI_DBG(" MCFGP_groupBaseAddr %u", i_mcBarData.MCFGP_groupBaseAddr);
- FAPI_DBG(" MCS_MCFGPM_VALID %u", i_mcBarData.MCS_MCFGPM_VALID);
- FAPI_DBG(" MCFGPM_group_size %u", i_mcBarData.MCFGPM_group_size);
- FAPI_DBG(" MCFGPM_groupBaseAddr %u", i_mcBarData.MCFGPM_groupBaseAddr);
+ FAPI_INF(" BAR data:");
+ FAPI_INF(" MCS_MCFGP_VALID %u", i_mcBarData.MCS_MCFGP_VALID);
+ FAPI_INF(" MCFGP_chan_per_group %u", i_mcBarData.MCFGP_chan_per_group);
+ FAPI_INF(" MCFGP_chan0_group_member_id %u", i_mcBarData.MCFGP_chan0_group_member_id);
+ FAPI_INF(" MCFGP_chan1_group_member_id %u", i_mcBarData.MCFGP_chan1_group_member_id);
+ FAPI_INF(" MCFGP_group_size %u", i_mcBarData.MCFGP_group_size);
+ FAPI_INF(" MCFGP_groupBaseAddr %u", i_mcBarData.MCFGP_groupBaseAddr);
+ FAPI_INF(" MCS_MCFGPM_VALID %u", i_mcBarData.MCS_MCFGPM_VALID);
+ FAPI_INF(" MCFGPM_group_size %u", i_mcBarData.MCFGPM_group_size);
+ FAPI_INF(" MCFGPM_groupBaseAddr %u", i_mcBarData.MCFGPM_groupBaseAddr);
for (uint8_t jj = 0; jj < MAX_ALT_MEM_REGIONS; jj++)
{
- FAPI_DBG(" MCFGPA_HOLE_valid[%u] %u", jj, i_mcBarData.MCFGPA_HOLE_valid[jj]);
- FAPI_DBG(" MCFGPA_HOLE_LOWER_addr[%u] %u", jj, i_mcBarData.MCFGPA_HOLE_LOWER_addr[jj]);
- FAPI_DBG(" MCFGPA_HOLE_UPPER_addr[%u] %u", jj, i_mcBarData.MCFGPA_HOLE_UPPER_addr[jj]);
+ FAPI_INF(" MCFGPA_HOLE_valid[%u] %u", jj, i_mcBarData.MCFGPA_HOLE_valid[jj]);
+ FAPI_INF(" MCFGPA_HOLE_LOWER_addr[%u] %u", jj, i_mcBarData.MCFGPA_HOLE_LOWER_addr[jj]);
+ FAPI_INF(" MCFGPA_HOLE_UPPER_addr[%u] %u", jj, i_mcBarData.MCFGPA_HOLE_UPPER_addr[jj]);
- FAPI_DBG(" MCFGPMA_HOLE_valid[%u] %u", jj, i_mcBarData.MCFGPMA_HOLE_valid[jj]);
- FAPI_DBG(" MCFGPMA_HOLE_LOWER_addr[%u] %u", jj, i_mcBarData.MCFGPMA_HOLE_LOWER_addr[jj]);
- FAPI_DBG(" MCFGPMA_HOLE_UPPER_addr[%u] %u", jj, i_mcBarData.MCFGPMA_HOLE_UPPER_addr[jj]);
+ FAPI_INF(" MCFGPMA_HOLE_valid[%u] %u", jj, i_mcBarData.MCFGPMA_HOLE_valid[jj]);
+ FAPI_INF(" MCFGPMA_HOLE_LOWER_addr[%u] %u", jj, i_mcBarData.MCFGPMA_HOLE_LOWER_addr[jj]);
+ FAPI_INF(" MCFGPMA_HOLE_UPPER_addr[%u] %u", jj, i_mcBarData.MCFGPMA_HOLE_UPPER_addr[jj]);
}
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
index 6d03bc85a..68d655d8c 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
@@ -878,14 +878,14 @@
<id>ATTR_MSS_MEM_MC_IN_GROUP</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
- An 8 bit vector that would be a designation of which MC (Nimbus MCS or
+ An 8 bit vector that would be a designation of which MC (Nimbus MCA or
Cumulus MI) are involved in the group.
So the bits would represent
Nimbus Cumulus
- Bit 0 MCS0 MI0
- Bit 1 MCS1 MI1
+ Bit 0 MCA0 MI0
+ Bit 1 MCA1 MI1
.....
- Bit 7 MCS7 MI7
+ Bit 7 MCA7 MI7
Set by p9_mss_eff_grouping
</description>
<valueType>uint8</valueType>
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