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authorGreg Still <stillgs@us.ibm.com>2017-03-05 13:45:30 -0600
committerChristian R. Geddes <crgeddes@us.ibm.com>2017-03-14 22:41:37 -0400
commit51b073913916d5afced7242f9bacfad486a6b28b (patch)
treeeac5e9b8c169ee45893bc007042bef39a8760b95 /src/import/chips/p9/procedures/hwp
parent519fbef6dcba4ed662366d7dd9f8c8ae43ba8e02 (diff)
downloadtalos-hostboot-51b073913916d5afced7242f9bacfad486a6b28b.tar.gz
talos-hostboot-51b073913916d5afced7242f9bacfad486a6b28b.zip
PM: Add CME_INSTRUCTION_TRACE_ENABLE attribute support for debug control
Change-Id: Id93fb6773616ccce77408f72a9ad1245e7a555d8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37521 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37523 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H1
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C19
2 files changed, 16 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index d9ce7dbe5..0f959069c 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -214,6 +214,7 @@ HCD_CONST(SGPE_STOP_4_TO_2_BIT_POS, 0x80000000)
HCD_CONST(SGPE_STOP_5_TO_4_BIT_POS, 0x40000000)
HCD_CONST(SGPE_STOP_8_TO_5_BIT_POS, 0x20000000)
HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS, 0x10000000)
+HCD_CONST(SGPE_CME_INSTRUCTION_TRACE_BIT_POS, 0x08000000)
HCD_CONST(SGPE_PROC_FAB_ADDR_BAR_MODE_POS, 0x00008000)
/// SGPE Hcode
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index dd468116e..79a0909c5 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -655,7 +655,7 @@ extern "C"
* @param i_pChipHomer points to HOMER image.
* @return fapi2 return code.
*/
- fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer )
+ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt )
{
uint8_t attrVal = 0;
uint32_t cmeFlag = 0;
@@ -666,7 +666,6 @@ extern "C"
cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE];
sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE];
PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)& i_pChipHomer->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR_SIZE];
-
//Handling flags common to CME and SGPE
FAPI_DBG(" ==================== CME/SGPE Flags =================");
@@ -720,7 +719,19 @@ extern "C"
sgpeFlag |= SGPE_STOP_11_TO_8_BIT_POS;
}
- FAPI_DBG("STOP_11_to_8 : %s", attrVal ? "TRUE" : "FALSE" );
+ FAPI_DBG("STOP_11_to_8 : %s", attrVal ? "TRUE" : "FALSE" );
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CME_INSTRUCTION_TRACE_ENABLE,
+ i_procTgt,
+ attrVal),
+ "Error from FAPI_ATTR_GET for attribute ATTR_CME_INSTRUCTION_TRACE_ENABLE");
+
+ if( attrVal )
+ {
+ sgpeFlag |= SGPE_CME_INSTRUCTION_TRACE_BIT_POS;
+ }
+
+ FAPI_DBG("CME Instruction Trace Enabled : %s", attrVal ? "TRUE" : "FALSE" );
// Set PGPE Header Flags from Attributes
FAPI_DBG(" -------------------- PGPE Flags -----------------");
@@ -3450,7 +3461,7 @@ extern "C"
"Final SRAM Image Size Check Failed" );
//Update CME/SGPE Flags in respective image header.
- FAPI_TRY( updateImageFlags( pChipHomer ),
+ FAPI_TRY( updateImageFlags( pChipHomer, i_procTgt ),
"updateImageFlags Failed" );
//Set the Fabric IDs
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