PM: Add CME_INSTRUCTION_TRACE_ENABLE attribute support for debug control

Change-Id: Id93fb6773616ccce77408f72a9ad1245e7a555d8
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37521
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37523
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

6 files changed, 79 insertions, 16 deletions

diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index d9ce7dbe5..0f959069c 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -214,6 +214,7 @@ HCD_CONST(SGPE_STOP_4_TO_2_BIT_POS,             0x80000000)
 HCD_CONST(SGPE_STOP_5_TO_4_BIT_POS,             0x40000000)
 HCD_CONST(SGPE_STOP_8_TO_5_BIT_POS,             0x20000000)
 HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS,            0x10000000)
+HCD_CONST(SGPE_CME_INSTRUCTION_TRACE_BIT_POS,   0x08000000)
 HCD_CONST(SGPE_PROC_FAB_ADDR_BAR_MODE_POS,      0x00008000)
 
 /// SGPE Hcode
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index dd468116e..79a0909c5 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -655,7 +655,7 @@ extern "C"
      * @param   i_pChipHomer    points to HOMER image.
      * @return  fapi2 return code.
      */
-    fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer )
+    fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt )
     {
         uint8_t attrVal = 0;
         uint32_t cmeFlag = 0;
@@ -666,7 +666,6 @@ extern "C"
         cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE];
         sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE];
         PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)& i_pChipHomer->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR_SIZE];
-
         //Handling flags common to CME and SGPE
 
         FAPI_DBG(" ==================== CME/SGPE Flags =================");
@@ -720,7 +719,19 @@ extern "C"
             sgpeFlag |= SGPE_STOP_11_TO_8_BIT_POS;
         }
 
-        FAPI_DBG("STOP_11_to_8          :   %s", attrVal ? "TRUE" : "FALSE" );
+        FAPI_DBG("STOP_11_to_8                  :   %s", attrVal ? "TRUE" : "FALSE" );
+
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CME_INSTRUCTION_TRACE_ENABLE,
+                               i_procTgt,
+                               attrVal),
+                 "Error from FAPI_ATTR_GET for attribute ATTR_CME_INSTRUCTION_TRACE_ENABLE");
+
+        if( attrVal )
+        {
+            sgpeFlag |= SGPE_CME_INSTRUCTION_TRACE_BIT_POS;
+        }
+
+        FAPI_DBG("CME Instruction Trace Enabled :   %s", attrVal ? "TRUE" : "FALSE" );
 
         // Set PGPE Header Flags from Attributes
         FAPI_DBG(" -------------------- PGPE Flags -----------------");
@@ -3450,7 +3461,7 @@ extern "C"
                       "Final SRAM Image Size Check Failed" );
 
             //Update CME/SGPE Flags in respective image header.
-            FAPI_TRY( updateImageFlags( pChipHomer ),
+            FAPI_TRY( updateImageFlags( pChipHomer, i_procTgt ),
                       "updateImageFlags Failed" );
 
             //Set the Fabric IDs
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
index 3509ac6c1..86c509eab 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
@@ -841,8 +841,8 @@
       This is matched to pbax_groupid of the PMISC Address phase.
 
       Provided by the Machine Readable Workbook.
-      
-      Platform default:  Nimbus systems = 0     
+
+      Platform default:  Nimbus systems = 0
     </description>
     <valueType>uint8</valueType>
     <platInit/>
@@ -858,8 +858,8 @@
       pbax_type=unicast.
 
       Provided by the Machine Readable Workbook.
-      
-      Platform default:  Nimbus systems - set so value in ATTR_FABRIC_GROUP_ID 
+
+      Platform default:  Nimbus systems - set so value in ATTR_FABRIC_GROUP_ID
     </description>
     <valueType>uint8</valueType>
     <platInit/>
@@ -875,12 +875,12 @@
     bit in this vector at the decoded bit location is a 1, then this receive
     engine will participate in the broadcast operation.
 
-    Override attribute.  Platform value of 0 indiates the OCC firmware will 
+    Override attribute.  Platform value of 0 indiates the OCC firmware will
     perform this function.
     </description>
     <valueType>uint8</valueType>
     <platInit/>
-    <initToZero/> 
+    <initToZero/>
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
@@ -1567,6 +1567,27 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
+     <id>ATTR_CME_INSTRUCTION_TRACE_ENABLE</id>
+     <description>
+     Enables the SGPE Hcode to enable the CME instruction traces into the L3
+     Trace array for debug.  Note:  all configured CMEs will be put into this
+     mode if this attribute is ON.
+
+     Consumer: p9_hcode_image_build.c ->
+                  SGPE Header field
+
+     Platform default:  OFF
+     </description>
+     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+     <valueType>uint8</valueType>
+     <enum>
+        OFF = 0x00, ON = 0x01
+    </enum>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
      <id>ATTR_PGPE_HCODE_FUNCTION_ENABLE</id>
      <description>
      Enables the PGPE Hcode to physically perform frequency and voltage operations
diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
index 9a4c0ab13..69739e658 100644
--- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
+++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
@@ -100,6 +100,10 @@
        <default>0x0</default>
      </attribute>
      <attribute>
+       <id>ATTR_CME_INSTRUCTION_TRACE_ENABLE</id>
+       <default>0x0</default>
+     </attribute>
+     <attribute>
          <id>ATTR_IO_OBUS_DCCAL_FLAGS</id>
          <default>0x0</default>
      </attribute>
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 3be640af9..370210c6e 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -32425,6 +32425,31 @@ Measured in GB</description>
 </attribute>
 
 <attribute>
+    <id>CME_INSTRUCTION_TRACE_ENABLE</id>
+    <description>
+     Enables the SGPE Hcode to enable the CME instruction traces into the L3
+     Trace array for debug.  Note:  all configured CMEs will be put into this
+     mode if this attribute is ON.
+
+     Consumer: p9_hcode_image_build.c ->
+                  SGPE Header field
+
+     Platform default:  OFF
+    </description>
+    <simpleType>
+        <uint8_t>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_CME_INSTRUCTION_TRACE_ENABLE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
     <id>CP_REFCLOCK_RCVR_TERM</id>
     <description>
         Defines system specific value of processor refclock receiver termination
@@ -32995,9 +33020,9 @@ Measured in GB</description>
 <attribute>
     <id>SKIP_HW_VREF_CAL</id>
     <description>
-        
+
       In sub DD1.02 Nimbus the HW VREF calibrations should not be run
-    
+
     </description>
     <simpleType>
         <uint8_t>
@@ -33015,9 +33040,9 @@ Measured in GB</description>
 <attribute>
     <id>SKIP_RD_VREF_VREFSENSE_OVERRIDE</id>
     <description>
-        
+
       In sub DD1.03 Nimbus the HW VREF calibrations should not be run
-    
+
     </description>
     <simpleType>
         <uint8_t>
@@ -33155,13 +33180,13 @@ Measured in GB</description>
 <attribute>
     <id>EFF_RANK_GROUP_OVERRIDE</id>
     <description>
-        
+
           Override PHY RANK_PAIR settings. First uint16 value is for RANK_PAIR0
           register value, and second is for RANK_PAIR1. Note that DIMM1 ranks in
           a dual-drop config will be converted from Centaur canonical number
           (4,5) to correct PHY settings (2,3). Set this attribute to zero
           to use default settings.
-        
+
     </description>
     <simpleType>
         <uint16_t>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 86a9608f0..92666f300 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1305,6 +1305,7 @@
     <attribute><id>TOD_CPU_DATA</id></attribute>
     <attribute><id>PM_SPWUP_IGNORE_XSTOP_FLAG</id></attribute>
     <attribute><id>SECUREBOOT_PROTECT_DECONFIGURED_TPM</id></attribute>
+    <attribute><id>CME_INSTRUCTION_TRACE_ENABLE</id></attribute>
     <!-- START memory workaround for DD1.02 -->
     <attribute><id>DO_MSS_WR_VREF</id></attribute>
     <attribute><id>DO_MSS_VREF_DAC</id></attribute>