diff options
author | Greg Still <stillgs@us.ibm.com> | 2018-03-09 16:43:33 -0600 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-15 15:14:14 -0400 |
commit | cbcd27d3a6292e709ab4b22811364b1abc47441a (patch) | |
tree | a1d2dc80a16d24d465383a3ff38e740b625adb75 /src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.H | |
parent | b1e597ec9bdb0df07fc3e492d208fdc8f46fed64 (diff) | |
download | talos-hostboot-cbcd27d3a6292e709ab4b22811364b1abc47441a.tar.gz talos-hostboot-cbcd27d3a6292e709ab4b22811364b1abc47441a.zip |
PM: p9_setup_evid steps voltage to avoid Fleetwood VRM limitations
- use the present value of ATTR_EXT_VRM_STEPSIZE (used by PGPE for Pstate
movement) to step the the boot voltage setup during istep 8. This attribute
defaults to 50mV.
- Done only for rails attached via AVSBus
Key_Cronus_Test=PM_REGRESS
Change-Id: I63feb361323246c8b92f1e96dc41f8fc19bd0912
CQ: SW420343
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55386
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55395
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.H')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.H | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.H b/src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.H index a73f44aab..838783a23 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -47,7 +47,7 @@ enum P9_SETUP_EVID_CONSTANTS BRIDGE_NUMBER = 1, // Default voltages if mailbox -> attributes are not setup - AVSBUS_VOLTAGE_WRITE_RETRY_COUNT = 5, + AVSBUS_RETRY_COUNT = 5, VDD_SETUP = 6, VDN_SETUP = 7, VCS_SETUP = 8, @@ -114,6 +114,7 @@ extern "C" /// @param [in] i_rail_select AVS bus rail select /// @param [in] i_voltage_mv voltage value in mv /// @param [in] i_evid_value EVID setup mode +/// @param [in] i_ext_vrm_step_size_mv Maximum VRM step size in mv //@return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. fapi2::ReturnCode p9_setup_evid_voltageWrite( @@ -121,9 +122,9 @@ extern "C" const uint8_t i_bus_num, const uint8_t i_rail_select, const uint32_t i_voltage_mv, + const uint32_t i_ext_vrm_step_size_mv, const P9_SETUP_EVID_CONSTANTS i_evid_value); - } // extern C #endif // __P9_SETUP_EVID_H__ |