Extend PM Reset flow to collect PM FFDC to HOMER

- extend the base flow to ensure ffdc gets collected to homer
- revise error xmls
- misc changes to handle pm recovery flow triggered via Malf Alert

Key_Cronus_Test=PM_REGRESS

Change-Id: I12148ed227efe4613332ae76ff142c1d82855f20
RTC: 153979
CQ: SW416537
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53522
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53533
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>

1 files changed, 267 insertions, 12 deletions

diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C
index 30b5d8342..95c8d9767 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C
@@ -58,6 +58,16 @@
 #include <p9_setup_evid.H>
 #include <p9_quad_scom_addresses.H>
 #include <p9_quad_scom_addresses_fld.H>
+#include <p9n2_misc_scom_addresses.H>
+#include <p9_pm_occ_firinit.H>
+
+#include <p9_pm_recovery_ffdc_base.H>
+#include <p9_pm_recovery_ffdc_cme.H>
+#include <p9_pm_recovery_ffdc_sgpe.H>
+#include <p9_pm_recovery_ffdc_pgpe.H>
+#include <p9_pm_recovery_ffdc_occ.H>
+#include <p9_pm_recovery_ffdc_cppm.H>
+#include <p9_pm_recovery_ffdc_qppm.H>
 
 // -----------------------------------------------------------------------------
 // Constant definitions
@@ -80,20 +90,64 @@ enum PPM_MASK
 // -----------------------------------------------------------------------------
 // Function definitions
 // -----------------------------------------------------------------------------
-
 fapi2::ReturnCode p9_pm_reset(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
     void* i_pHomerImage = NULL)
 {
+    using namespace p9_stop_recov_ffdc;
     FAPI_IMP(">> p9_pm_reset");
 
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    bool l_malfAlert = false;
+    fapi2::ATTR_PM_MALF_ALERT_ENABLE_Type l_malfEnabled =
+        fapi2::ENUM_ATTR_PM_MALF_ALERT_ENABLE_FALSE;
+
+    fapi2::ATTR_PM_RESET_PHASE_Type l_phase = PM_RESET_INIT;
+
+    fapi2::ATTR_INITIATED_PM_RESET_Type l_pmResetActive =
+        fapi2::ENUM_ATTR_INITIATED_PM_RESET_ACTIVE;
+
     fapi2::buffer<uint64_t> l_data64;
     fapi2::ReturnCode l_rc;
 
     //  ************************************************************************
+    //  Put a mark on the wall that we are in the Reset Flow
+    //  ************************************************************************
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_INITIATED_PM_RESET, i_target, l_pmResetActive));
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
+
+    //  ************************************************************************
+    //  Check if the PM Complex Reset came in due to a Malf Alert
+    //  ************************************************************************
+    FAPI_TRY (FAPI_ATTR_GET (fapi2::ATTR_PM_MALF_ALERT_ENABLE, FAPI_SYSTEM, l_malfEnabled));
+
+    if (l_malfEnabled == fapi2::ENUM_ATTR_PM_MALF_ALERT_ENABLE_TRUE)
+    {
+        FAPI_TRY(fapi2::getScom(i_target, P9N2_PU_OCB_OCI_OCCFLG2_SCOM, l_data64),
+                 "Error reading P9N2_PU_OCB_OCI_OCCFLG2_SCOM to check for Malf Alert");
+
+        if (l_data64.getBit<p9hcd::PM_CALLOUT_ACTIVE>())
+        {
+            l_malfAlert = true;
+            FAPI_IMP("OCC FLAG2 Bit 28 [PM_CALLOUT_ACTIVE] Set: In Malf Path");
+        }
+    }
+
+    //  ************************************************************************
+    //  Initialize the PM FFDC section headers in HOMER, record the PPE halt
+    //  states and FIR data before resetting the subsystem
+    //  ************************************************************************
+    FAPI_DBG("Init PM FFDC section in HOMER & collect PPE Halt and FIR states");
+    FAPI_TRY ( p9_pm_collect_ffdc(i_target, i_pHomerImage, PLAT_INIT),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_INIT );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After PM FFDC Init & Read PPE Halt, FIR states"));
+
+    //  ************************************************************************
     //  Mask the OCC FIRs as errors can occur in what follows
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_occ_firinit for masking errors in reset operation.");
+    l_phase = PM_RESET_FIR_OCC;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_occ_firinit, i_target, p9pm::PM_RESET);
     FAPI_TRY(l_rc, "ERROR: Failed to mask OCC FIRs.");
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After masking FIRs"));
@@ -102,6 +156,8 @@ fapi2::ReturnCode p9_pm_reset(
     //  Halt the OCC PPC405 and reset it safely
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_occ_control to put OCC PPC405 into reset safely.");
+    l_phase = PM_RESET_OCC_CTRL;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_occ_control,
                   i_target,
                   p9occ_ctrl::PPC405_RESET_SEQUENCE, //Operation on PPC405
@@ -110,18 +166,30 @@ fapi2::ReturnCode p9_pm_reset(
     FAPI_TRY(l_rc, "ERROR: Failed to reset OCC PPC405");
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After safe reset of OCC PPC405"));
 
-    //  ************************************************************************
-    //  Put all EX chiplets in special wakeup
-    //  ************************************************************************
-    FAPI_DBG("Enable special wakeup for all functional  EX targets.");
-    FAPI_TRY(special_wakeup_all(i_target,
-                                true),//Enable splwkup
-             "ERROR: Failed to remove EX chiplets from special wakeup");
-    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After EX in special wakeup"));
+    if (l_malfAlert == false)
+    {
+        //  ************************************************************************
+        //  Put all EX chiplets in special wakeup
+        //  ************************************************************************
+        FAPI_DBG("Enable special wakeup for all functional  EX targets.");
+        l_phase = PM_RESET_SPL_WKUP_EX_ALL;
+        FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
+        FAPI_TRY(special_wakeup_all(i_target,
+                                    true),//Enable splwkup
+                 "ERROR: Failed to remove EX chiplets from special wakeup");
+        FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After EX in special wakeup"));
+    }
+    else
+    {
+        FAPI_TRY(p9_pm_glob_fir_trace(i_target, "Skip special wakeup in malf alert path"));
+    }
 
     //  ************************************************************************
-    //  Enable the Auto Special Wake-up Function on all EXs
+    //  Set Auto Special Wake-up Mode to all EXs ECs if spl. wkup done is asserted
     //  ************************************************************************
+    FAPI_DBG("Set auto special wakeup for all functional  EX targets.");
+    l_phase = PM_RESET_SET_AUTO_SPL_WKUP;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_TRY(p9_pm_set_auto_spwkup(i_target));
 
     //  ************************************************************************
@@ -136,6 +204,8 @@ fapi2::ReturnCode p9_pm_reset(
     //  Issue reset to OCC GPEs ( GPE0 and GPE1) (Bring them to HALT)
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_occ_gpe_init to reset OCC GPE");
+    l_phase = PM_RESET_OCC_GPE;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_occ_gpe_init,
                   i_target,
                   p9pm::PM_RESET,
@@ -145,21 +215,48 @@ fapi2::ReturnCode p9_pm_reset(
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of OCC GPEs"));
 
     //  ************************************************************************
+    //  Collect OCC FFDC into FFDC section in HOMER
+    //  ************************************************************************
+    FAPI_DBG("Collect FFDC from 405, GPE0 and GPE1 to HOMER");
+    FAPI_TRY ( p9_pm_collect_ffdc (i_target, i_pHomerImage, PLAT_OCC),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_OCC );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After OCC, GPE0 and GPE1 FFDC"));
+
+    //  ************************************************************************
     //  Reset the PSTATE GPE (Bring it to HALT)
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_pstate_gpe_init to reset PGPE");
+    l_phase = PM_RESET_PGPE;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_pstate_gpe_init, i_target, p9pm::PM_RESET);
     FAPI_TRY(l_rc, "ERROR: Failed to reset the PGPE");
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of PGPE"));
 
     //  ************************************************************************
+    //  Collect PGPE FFDC into FFDC section in HOMER
+    //  ************************************************************************
+    FAPI_DBG("Collect FFDC from PGPE to HOMER");
+    FAPI_TRY ( p9_pm_collect_ffdc (i_target, i_pHomerImage, PLAT_PGPE),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_PGPE );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After PGPE FFDC"));
+
+    //  ************************************************************************
     //  Reset the STOP GPE (Bring it to HALT)
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_stop_gpe_init to reset SGPE");
+    l_phase = PM_RESET_SGPE;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_stop_gpe_init, i_target, p9pm::PM_RESET);
     FAPI_TRY(l_rc, "ERROR: Failed to reset SGPE");
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of SGPE"));
 
+    //  ************************************************************************
+    //  Collect SGPE FFDC into FFDC section in HOMER
+    //  ************************************************************************
+    FAPI_DBG("Collect FFDC from SGPE to HOMER");
+    FAPI_TRY ( p9_pm_collect_ffdc ( i_target, i_pHomerImage, PLAT_SGPE),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_SGPE );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After SGPE FFDC"));
 
     //  ************************************************************************
     // Clear the OCC Flag and Scratch2 registers
@@ -171,11 +268,28 @@ fapi2::ReturnCode p9_pm_reset(
     FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCS2_SCOM, l_data64),
              "ERROR: Failed to write to OCC Scratch2 Register");
 
+    //  ************************************************************************
+    //  Collect FFDC from CPPMs into FFDC section in HOMER
+    //  ************************************************************************
+    FAPI_DBG("Collect FFDC from CPPMs to HOMER");
+    FAPI_TRY ( p9_pm_collect_ffdc (i_target, i_pHomerImage, PLAT_CPPM),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_CPPM );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After CPPMs FFDC"));
+
+    //  ************************************************************************
+    //  Collect FFDC from QPPMs into FFDC section in HOMER
+    //  ************************************************************************
+    FAPI_DBG("Collect FFDC from QPPMs to HOMER");
+    FAPI_TRY ( p9_pm_collect_ffdc (i_target, i_pHomerImage, PLAT_QPPM),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_QPPM );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After QPPMs FFDC"));
 
     //  ************************************************************************
     //  Reset Cores and Quads
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_corequad_init to reset cores & quads");
+    l_phase = PM_RESET_EC_EQ;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_corequad_init,
                   i_target,
                   p9pm::PM_RESET,
@@ -187,16 +301,27 @@ fapi2::ReturnCode p9_pm_reset(
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of core quad"));
 
     //  ************************************************************************
+    //  Collect FFDC from CMEs into FFDC section in HOMER
+    //  ************************************************************************
+    FAPI_DBG("Collect FFDC from CMEs to HOMER");
+    FAPI_TRY ( p9_pm_collect_ffdc (i_target, i_pHomerImage, PLAT_CME),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_CME );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After CME FFDC"));
+
+    //  ************************************************************************
     //  Move PSAFE values to DPLL and Ext Voltage
     //  ************************************************************************
+    l_phase = PM_RESET_PSAFE_UPDATE;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_TRY(p9_pm_reset_psafe_update(i_target),
              "Error from p9_pm_reset_psafe_update");
 
-
     //  ************************************************************************
     //  Issue reset to OCC-SRAM
     //  ************************************************************************
     FAPI_DBG("Executing p8_occ_sram_init to reset OCC-SRAM");
+    l_phase = PM_RESET_OCC_SRAM;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_occ_sram_init, i_target, p9pm::PM_RESET);
     FAPI_TRY(l_rc, "ERROR: Failed to reset OCC SRAM");
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of OCC SRAM"));
@@ -205,6 +330,8 @@ fapi2::ReturnCode p9_pm_reset(
     //  Issue reset to OCB
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_ocb_init to reset OCB");
+    l_phase = PM_RESET_OCB;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_ocb_init,
                   i_target,
                   p9pm::PM_RESET,
@@ -222,12 +349,58 @@ fapi2::ReturnCode p9_pm_reset(
     //  Resets P2S and HWC logic
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_pss_init to reset P2S and HWC logic");
+    l_phase = PM_RESET_PSS;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_pss_init, i_target, p9pm::PM_RESET);
     FAPI_TRY(l_rc, "ERROR: Failed to reset PSS & HWC");
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of PSS"));
 
+    //  ************************************************************************
+    //  Trigger OCC LFIR so that bad ec/ex/eq are updated for pm_init and prd
+    //  gets a chance to deconfig cores and callout hw and grab ffdc to logs
+    //  This should be the last phase in pm reset
+    //  ************************************************************************
+    if (l_malfAlert == true)
+    {
+        const uint32_t l_OCC_LFIR_BIT_STOP_RCV_NOTIFY_PRD = 3;
+        l_phase = PM_RESET_NOTIFY_PRD;
+        FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
+
+        p9pmFIR::PMFir <p9pmFIR::FIRTYPE_OCC_LFIR> l_occFir(i_target);
+        FAPI_TRY(l_occFir.get(p9pmFIR::REG_ALL),
+                 "ERROR: Failed to get the OCC FIR values");
+        FAPI_TRY(l_occFir.setRecvAttn(l_OCC_LFIR_BIT_STOP_RCV_NOTIFY_PRD),
+                 FIR_REC_ATTN_ERROR);
+        // Not doing the restoreSavedMask, as this is a special case between reset->init
+        // and pm init handles it
+        FAPI_TRY(l_occFir.put(),
+                 "ERROR: Failed to write OCC LFIR setting for STOP_RCV_NOTIFY_PRD");
+
+        l_data64.flush<0>();
+        l_data64.setBit(l_OCC_LFIR_BIT_STOP_RCV_NOTIFY_PRD);
+
+        FAPI_IMP ("p9_pm_reset: Signalling PRD via OCCLFIR Bit 3 [STOP_RCV_NOTIFY_PRD]!");
+        FAPI_TRY(fapi2::putScom(i_target, PERV_TP_OCC_SCOM_OCCLFIR_OR, l_data64),
+                 "ERROR: Failed to write to OCC Flag Register");
+    }
+
+    l_phase = PM_RESET_DONE;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
+
 fapi_try_exit:
-    FAPI_IMP("<< p9_pm_reset");
+    //  Update PM FFDC Section Header with Miscellaneous Info
+    l_rc = p9_pm_collect_ffdc (i_target, i_pHomerImage, PLAT_MISC);
+
+    if (l_rc != fapi2::FAPI2_RC_SUCCESS)
+    {
+        FAPI_ERR ("Failed updating Miscellaneous FFDC to PM FFDC section!", PLAT_MISC );
+    }
+
+    l_pmResetActive = fapi2::ENUM_ATTR_INITIATED_PM_RESET_INACTIVE;
+    FAPI_ATTR_SET (fapi2::ATTR_INITIATED_PM_RESET, i_target, l_pmResetActive);
+
+    FAPI_ATTR_GET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase);
+    FAPI_IMP("<< p9_pm_reset: Phase 0x%02X", l_phase);
     return fapi2::current_err;
 }
 
@@ -442,3 +615,85 @@ fapi_try_exit:
     FAPI_INF("<< p9_set_auto_spwkup");
     return fapi2::current_err;
 }
+
+fapi2::ReturnCode p9_pm_collect_ffdc (
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    void* i_pHomerImage,
+    const uint8_t i_plat )
+{
+    using namespace p9_stop_recov_ffdc;
+    FAPI_DBG (">>  p9_pm_collect_ffdc: Plat %d", i_plat);
+
+    fapi2::ReturnCode l_rc;
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    fapi2::ATTR_PM_RESET_FFDC_ENABLE_Type l_ffdcEnable =
+        fapi2::ENUM_ATTR_PM_RESET_FFDC_ENABLE_FALSE;
+    fapi2::ATTR_PM_RESET_PHASE_Type l_phase = PM_RESET_UNKNOWN;
+
+    FAPI_TRY (FAPI_ATTR_GET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
+    FAPI_TRY (FAPI_ATTR_GET (fapi2::ATTR_PM_RESET_FFDC_ENABLE, FAPI_SYSTEM, l_ffdcEnable));
+
+    if (l_ffdcEnable == fapi2::ENUM_ATTR_PM_RESET_FFDC_ENABLE_TRUE)
+    {
+        switch (i_plat)
+        {
+            case PLAT_INIT:
+                FAPI_INF ("Init PM FFDC sections, collect PPE and FIR states to HOMER");
+                FAPI_EXEC_HWP (l_rc, p9_pm_recovery_ffdc_base, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_CME:
+                FAPI_DBG("Collecting CME(s) FFDC to HOMER");
+                FAPI_EXEC_HWP(l_rc, p9_pm_recovery_ffdc_cme, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_SGPE:
+                FAPI_DBG("Collecting SGPE FFDC to HOMER");
+                FAPI_EXEC_HWP(l_rc, p9_pm_recovery_ffdc_sgpe, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_PGPE:
+                FAPI_DBG("Collecting PGPE FFDC to HOMER");
+                FAPI_EXEC_HWP(l_rc, p9_pm_recovery_ffdc_pgpe, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_OCC:
+                FAPI_DBG("Collecting OCC 405, GPE0 and GPE1 FFDC to HOMER");
+                FAPI_EXEC_HWP(l_rc, p9_pm_recovery_ffdc_occ, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_CPPM:
+                FAPI_DBG("Collecting CPPM(s) FFDC to HOMER");
+                FAPI_EXEC_HWP(l_rc, p9_pm_recovery_ffdc_cppm, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_QPPM:
+                FAPI_DBG("Collecting QPPM(s) FFDC to HOMER");
+                FAPI_EXEC_HWP(l_rc, p9_pm_recovery_ffdc_qppm, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_MISC:
+                FAPI_DBG("Collecting Miscellaneous FFDC to HOMER");
+                l_rc = p9_pm_recovery_ffdc_misc (i_target, i_pHomerImage);
+                break;
+
+            default:
+                FAPI_ERR ("Bad Input Platform: 0x%02X .. Ignored!", i_plat);
+                l_rc = fapi2::RC_PM_RESET_FFDC_ERROR;
+                break;
+        }
+
+        FAPI_ASSERT_NOEXIT (l_rc == fapi2::FAPI2_RC_SUCCESS,
+                            fapi2::PM_RESET_FFDC_ERROR(fapi2::FAPI2_ERRL_SEV_RECOVERED)
+                            .set_CHIP_TARGET(i_target)
+                            .set_PM_RESET_PHASE(l_phase)
+                            .set_PM_FFDC_PLAT(i_plat),
+                            "Failed PM FFDC collection: Plat: 0x%02X Phase: 0x%02X",
+                            i_plat, l_phase);
+    }
+
+fapi_try_exit:
+    FAPI_DBG ( "<< p9_pm_collect_ffdc: Plat: 0x%02X Phase: 0x%02X Enabled: %d",
+               i_plat, l_phase, l_ffdcEnable );
+    return fapi2::current_err;
+}