Extend PM Reset flow to collect PM FFDC to HOMER

- extend the base flow to ensure ffdc gets collected to homer
- revise error xmls
- misc changes to handle pm recovery flow triggered via Malf Alert

Key_Cronus_Test=PM_REGRESS

Change-Id: I12148ed227efe4613332ae76ff142c1d82855f20
RTC: 153979
CQ: SW416537
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53522
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53533
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>

17 files changed, 463 insertions, 33 deletions

diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.C
index bd6d30061..c308feb57 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.C
@@ -335,6 +335,23 @@ namespace p9_stop_recov_ffdc
 
 //------------------------------------------------------------------------------
 
+    void PlatPmComplex::logPmResetPhase (const void* i_pHomerBuf)
+    {
+        FAPI_DBG ( ">> PlatPmComplex::logPmResetPhase" );
+        HomerFfdcRegion* l_pHomerFfdc = ( HomerFfdcRegion* )
+             ((uint8_t*) i_pHomerBuf + FFDC_REGION_HOMER_BASE_OFFSET );
+        uint8_t* l_pResetPhase = &l_pHomerFfdc->iv_pmFfdcHdrRegion.iv_pmFfdcHdr.iv_phase;
+
+        fapi2::ATTR_PM_RESET_PHASE_Type l_phase;
+        FAPI_ATTR_GET (fapi2::ATTR_PM_RESET_PHASE, iv_procChip, l_phase);
+        *l_pResetPhase = l_phase;
+
+        FAPI_DBG ( "<<  PlatPmComplex::logPmResetPhase PM Reset Phase: %d",
+                   l_phase );
+    }
+
+//------------------------------------------------------------------------------
+
     fapi2::ReturnCode PlatPmComplex::readPpeHaltState (
                       const uint64_t  i_xirBaseAddress,
                        const uint8_t* i_pHomerOffset )
@@ -665,8 +682,12 @@ extern "C"
     {
         FAPI_IMP(">> p9_pm_recovery_ffdc_base" );
         std::vector<PlatPmComplex*> l_pPlatList;
+        fapi2::ATTR_PM_RESET_PHASE_Type l_phase = PM_RESET_FFDC_SEC_INIT;
 
         // init all the platform FFDC headers
+        FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_procChipTarget,
+                       l_phase);
+
         l_pPlatList.push_back (new PlatPmComplex(i_procChipTarget));
         l_pPlatList.push_back (new PlatCme(i_procChipTarget));
         l_pPlatList.push_back (new PlatSgpe(i_procChipTarget));
@@ -684,11 +705,16 @@ extern "C"
         }
 
         // Grab FIRs and PPE Halt State in FFDC, before entering Reset Flow
+        // PPE_HALT_STATE and FIRS are collected together, mark step as FIRS
+        l_phase = PM_RESET_FFDC_GET_FIRS;
+        FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_procChipTarget,
+                                 l_phase);
         FAPI_INF ("p9_pm_recovery_ffdc_base: Collecting FIR & PPE Halt States");
+
         for ( auto& it : l_pPlatList )
         {
             FAPI_TRY ( it->collectFfdc (i_pHomerImage, (PPE_HALT_STATE | FIR_STATE)),
-            "p9_pm_recovery_ffdc_base: Failed to collect FOR & PPE Halt State. Plat %d",
+            "p9_pm_recovery_ffdc_base: Failed to collect FIR & PPE Halt State. Plat %d",
             it->getPlatId () );
         }
 
@@ -697,7 +723,20 @@ extern "C"
             delete it;
 
         FAPI_IMP("<< p9_pm_recovery_ffdc_base" );
-        return  fapi2::FAPI2_RC_SUCCESS;
+        return  fapi2::current_err;
+    }
+
+    fapi2::ReturnCode p9_pm_recovery_ffdc_misc (
+                      const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_procChipTarget,
+                      void* i_pHomerImage )
+    {
+        FAPI_DBG (">> p9_pm_recovery_ffdc_misc" );
+        PlatPmComplex l_pmFfdc (i_procChipTarget, PLAT_MISC);
+
+        l_pmFfdc.logPmResetPhase (i_pHomerImage);
+
+        FAPI_DBG ("<< p9_pm_recovery_ffdc_misc" );
+        return fapi2::FAPI2_RC_SUCCESS;
     }
 }
 
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.H
index 4f1769728..cb4370f41 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_base.H
@@ -59,7 +59,7 @@ namespace p9_stop_recov_ffdc
             /// @param[in]  i_globalBaseAddr        sram address of start of global variables
             PlatPmComplex( const fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP >
                                     i_procChipTgt,
-                           PmComplexPlatId i_plat = PLAT_NONE,
+                           PmComplexPlatId i_plat = PLAT_INIT,
                            uint32_t i_imageHdrBaseAddr = 0,
                            uint32_t i_traceBufBaseAddress = 0,
                            uint32_t i_globalBaseAddr = 0 );
@@ -122,6 +122,11 @@ namespace p9_stop_recov_ffdc
             ///@brief initializes a list of register for generation of FFDC summary.
             void initRegList();
 
+           ///@brief logs the current PM Reset Phase in the PmFfdcHeader
+           ///@param[in]  i_pHomerBuf Base address of PM FFDC in HOMER
+           ///@return     N.A.
+           void logPmResetPhase ( const void*    i_pHomerBuf );
+
         protected:
 
             /// @brief  parses a region of HOMER to extract PPE registers
@@ -292,7 +297,7 @@ namespace p9_stop_recov_ffdc
     // function pointer typedef definition for HWP call support
     typedef fapi2::ReturnCode (*p9_pm_recovery_ffdc_base_FP_t)
             ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
-              const void* );
+              void* );
 
     extern "C"
     {
@@ -311,6 +316,18 @@ namespace p9_stop_recov_ffdc
         fapi2::ReturnCode p9_pm_recovery_ffdc_base
         ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_procChipTarget,
           void* i_pHomerImage );
+
+    /// @brief Updates the PM FFDC section in HOMER with miscellaneous, platform
+    ///        agnostic FFDC
+    ///
+    /// @param[in] i_procChipTarget Proc Chip target
+    /// @param[in] i_pHomerImage    Pointer to the base of the chip HOMER region
+    ///
+    /// @return FAPI2_RC_SUCCESS on success or error return code
+    ///
+        fapi2::ReturnCode p9_pm_recovery_ffdc_misc
+        ( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_procChipTarget,
+          void* i_pHomerImage );
     }
 
 } //namespace p9_stop_recov_ffdc ends
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.C
index cd9fea11a..9a73d5f24 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cme.C
@@ -230,6 +230,7 @@
         }
 
     fapi_try_exit:
+        logPmResetPhase (i_pHomerBuf);
         FAPI_DBG("<< PlatCme::collectFfdc");
         return fapi2::current_err;
     }
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cppm.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cppm.C
index d63366c36..0d50b2e73 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cppm.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_cppm.C
@@ -154,6 +154,7 @@
         }
 
     fapi_try_exit:
+        logPmResetPhase (i_pHomerBuf);
         FAPI_DBG("<< CppmRegs::collectFfdc");
         return fapi2::current_err;
     }
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_defines.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_defines.H
index bd62e0605..c518e8d38 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_defines.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_defines.H
@@ -43,13 +43,15 @@ namespace p9_stop_recov_ffdc
  */
 enum PmResetStep
 {
-    PM_RESET_UNKNOWN = 0,
+    PM_RESET_UNKNOWN = 0x00,
+    PM_RESET_INIT,
     PM_RESET_FFDC_SEC_INIT,
     PM_RESET_FFDC_CHK_PPE_HALT,
     PM_RESET_FFDC_GET_FIRS,
     PM_RESET_FIR_OCC,
     PM_RESET_OCC_CTRL,
     PM_RESET_SPL_WKUP_EX_ALL,
+    PM_RESET_SET_AUTO_SPL_WKUP,
     PM_RESET_FIR_PBA,
     PM_RESET_FIR_PPM,
     PM_RESET_FIR_CME,
@@ -57,11 +59,12 @@ enum PmResetStep
     PM_RESET_PGPE,
     PM_RESET_SGPE,
     PM_RESET_EC_EQ,
-    PM_RESET_DISABLE_RES_CLKS,
+    PM_RESET_PSAFE_UPDATE,
     PM_RESET_OCC_SRAM,
     PM_RESET_OCB,
     PM_RESET_PSS,
-    PM_RESET_MAX
+    PM_RESET_NOTIFY_PRD,
+    PM_RESET_DONE = 0xFF  // Always the last
 };
 
 /**
@@ -69,13 +72,14 @@ enum PmResetStep
  */
 enum PmComplexPlatId
 {
-    PLAT_NONE   =   0x00,
+    PLAT_INIT   =   0x00,
     PLAT_CME    =   0x01,
     PLAT_SGPE   =   0x02,
     PLAT_PGPE   =   0x03,
     PLAT_OCC    =   0x04,
     PLAT_CPPM   =   0x05,
     PLAT_QPPM   =   0x06,
+    PLAT_MISC   =   0x07,
 };
 
 /**
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.C
index fb7f17b51..ba5c4000d 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.C
@@ -76,10 +76,10 @@ namespace p9_stop_recov_ffdc
     {
         FAPI_DBG (">> PlatOcc::initRegList" );
         std::vector < uint32_t> l_scomRegList;
-        iv_occSummaryReg.push_back( PU_OCB_OCI_CCSR_SCOM );
-        iv_occSummaryReg.push_back( PU_OCB_OCI_QSSR_SCOM );
-        iv_occSummaryReg.push_back( P9N2_PU_OCB_OCI_OCCFLG_SCOM );
-        iv_occSummaryReg.push_back( P9N2_PU_OCB_OCI_OCCFLG2_SCOM );
+        l_scomRegList.push_back( PU_OCB_OCI_CCSR_SCOM );
+        l_scomRegList.push_back( PU_OCB_OCI_QSSR_SCOM );
+        l_scomRegList.push_back( P9N2_PU_OCB_OCI_OCCFLG_SCOM );
+        l_scomRegList.push_back( P9N2_PU_OCB_OCI_OCCFLG2_SCOM );
         PlatPmComplex::updateSummaryList( l_scomRegList );
         FAPI_DBG ("<< PlatOcc::initRegList" );
     }
@@ -221,6 +221,7 @@ namespace p9_stop_recov_ffdc
         }
 
     fapi_try_exit:
+        logPmResetPhase (i_pHomerBuf);
         FAPI_DBG("<< PlatOcc::collectFfdc");
         return fapi2::current_err;
     }
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.H
index 2d80f4904..e85e52afa 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_occ.H
@@ -107,8 +107,6 @@ namespace p9_stop_recov_ffdc
 
             ///@brief initializes a list of register for generation of FFDC summary.
             void initRegList();
-        private:
-            std::vector<uint32_t> iv_occSummaryReg;
     };
 
     //---------------------------------------------------------------------------------------------
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.C
index 5db2ff0c8..894f35f85 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_pgpe.C
@@ -167,6 +167,7 @@
         }
 
     fapi_try_exit:
+        logPmResetPhase (i_pHomerBuf);
         FAPI_DBG("<< PlatPgpe::collectFfdc");
         return fapi2::current_err;
     }
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_qppm.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_qppm.C
index 3288b92db..44543ed58 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_qppm.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_qppm.C
@@ -135,6 +135,7 @@
         }
 
     fapi_try_exit:
+        logPmResetPhase (i_pHomerBuf);
         FAPI_DBG("<< QppmRegs::collectFfdc");
         return fapi2::current_err;
     }
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.C
index 478c1049f..cbc1f8c6f 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_recovery_ffdc_sgpe.C
@@ -165,6 +165,7 @@
         }
 
     fapi_try_exit:
+        logPmResetPhase (i_pHomerBuf);
         FAPI_DBG("<< PlatSgpe::collectFfdc: 0x%02X", l_ffdcValdityVect);
         return fapi2::current_err;
     }
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C
index 30b5d8342..95c8d9767 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C
@@ -58,6 +58,16 @@
 #include <p9_setup_evid.H>
 #include <p9_quad_scom_addresses.H>
 #include <p9_quad_scom_addresses_fld.H>
+#include <p9n2_misc_scom_addresses.H>
+#include <p9_pm_occ_firinit.H>
+
+#include <p9_pm_recovery_ffdc_base.H>
+#include <p9_pm_recovery_ffdc_cme.H>
+#include <p9_pm_recovery_ffdc_sgpe.H>
+#include <p9_pm_recovery_ffdc_pgpe.H>
+#include <p9_pm_recovery_ffdc_occ.H>
+#include <p9_pm_recovery_ffdc_cppm.H>
+#include <p9_pm_recovery_ffdc_qppm.H>
 
 // -----------------------------------------------------------------------------
 // Constant definitions
@@ -80,20 +90,64 @@ enum PPM_MASK
 // -----------------------------------------------------------------------------
 // Function definitions
 // -----------------------------------------------------------------------------
-
 fapi2::ReturnCode p9_pm_reset(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
     void* i_pHomerImage = NULL)
 {
+    using namespace p9_stop_recov_ffdc;
     FAPI_IMP(">> p9_pm_reset");
 
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    bool l_malfAlert = false;
+    fapi2::ATTR_PM_MALF_ALERT_ENABLE_Type l_malfEnabled =
+        fapi2::ENUM_ATTR_PM_MALF_ALERT_ENABLE_FALSE;
+
+    fapi2::ATTR_PM_RESET_PHASE_Type l_phase = PM_RESET_INIT;
+
+    fapi2::ATTR_INITIATED_PM_RESET_Type l_pmResetActive =
+        fapi2::ENUM_ATTR_INITIATED_PM_RESET_ACTIVE;
+
     fapi2::buffer<uint64_t> l_data64;
     fapi2::ReturnCode l_rc;
 
     //  ************************************************************************
+    //  Put a mark on the wall that we are in the Reset Flow
+    //  ************************************************************************
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_INITIATED_PM_RESET, i_target, l_pmResetActive));
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
+
+    //  ************************************************************************
+    //  Check if the PM Complex Reset came in due to a Malf Alert
+    //  ************************************************************************
+    FAPI_TRY (FAPI_ATTR_GET (fapi2::ATTR_PM_MALF_ALERT_ENABLE, FAPI_SYSTEM, l_malfEnabled));
+
+    if (l_malfEnabled == fapi2::ENUM_ATTR_PM_MALF_ALERT_ENABLE_TRUE)
+    {
+        FAPI_TRY(fapi2::getScom(i_target, P9N2_PU_OCB_OCI_OCCFLG2_SCOM, l_data64),
+                 "Error reading P9N2_PU_OCB_OCI_OCCFLG2_SCOM to check for Malf Alert");
+
+        if (l_data64.getBit<p9hcd::PM_CALLOUT_ACTIVE>())
+        {
+            l_malfAlert = true;
+            FAPI_IMP("OCC FLAG2 Bit 28 [PM_CALLOUT_ACTIVE] Set: In Malf Path");
+        }
+    }
+
+    //  ************************************************************************
+    //  Initialize the PM FFDC section headers in HOMER, record the PPE halt
+    //  states and FIR data before resetting the subsystem
+    //  ************************************************************************
+    FAPI_DBG("Init PM FFDC section in HOMER & collect PPE Halt and FIR states");
+    FAPI_TRY ( p9_pm_collect_ffdc(i_target, i_pHomerImage, PLAT_INIT),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_INIT );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After PM FFDC Init & Read PPE Halt, FIR states"));
+
+    //  ************************************************************************
     //  Mask the OCC FIRs as errors can occur in what follows
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_occ_firinit for masking errors in reset operation.");
+    l_phase = PM_RESET_FIR_OCC;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_occ_firinit, i_target, p9pm::PM_RESET);
     FAPI_TRY(l_rc, "ERROR: Failed to mask OCC FIRs.");
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After masking FIRs"));
@@ -102,6 +156,8 @@ fapi2::ReturnCode p9_pm_reset(
     //  Halt the OCC PPC405 and reset it safely
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_occ_control to put OCC PPC405 into reset safely.");
+    l_phase = PM_RESET_OCC_CTRL;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_occ_control,
                   i_target,
                   p9occ_ctrl::PPC405_RESET_SEQUENCE, //Operation on PPC405
@@ -110,18 +166,30 @@ fapi2::ReturnCode p9_pm_reset(
     FAPI_TRY(l_rc, "ERROR: Failed to reset OCC PPC405");
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After safe reset of OCC PPC405"));
 
-    //  ************************************************************************
-    //  Put all EX chiplets in special wakeup
-    //  ************************************************************************
-    FAPI_DBG("Enable special wakeup for all functional  EX targets.");
-    FAPI_TRY(special_wakeup_all(i_target,
-                                true),//Enable splwkup
-             "ERROR: Failed to remove EX chiplets from special wakeup");
-    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After EX in special wakeup"));
+    if (l_malfAlert == false)
+    {
+        //  ************************************************************************
+        //  Put all EX chiplets in special wakeup
+        //  ************************************************************************
+        FAPI_DBG("Enable special wakeup for all functional  EX targets.");
+        l_phase = PM_RESET_SPL_WKUP_EX_ALL;
+        FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
+        FAPI_TRY(special_wakeup_all(i_target,
+                                    true),//Enable splwkup
+                 "ERROR: Failed to remove EX chiplets from special wakeup");
+        FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After EX in special wakeup"));
+    }
+    else
+    {
+        FAPI_TRY(p9_pm_glob_fir_trace(i_target, "Skip special wakeup in malf alert path"));
+    }
 
     //  ************************************************************************
-    //  Enable the Auto Special Wake-up Function on all EXs
+    //  Set Auto Special Wake-up Mode to all EXs ECs if spl. wkup done is asserted
     //  ************************************************************************
+    FAPI_DBG("Set auto special wakeup for all functional  EX targets.");
+    l_phase = PM_RESET_SET_AUTO_SPL_WKUP;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_TRY(p9_pm_set_auto_spwkup(i_target));
 
     //  ************************************************************************
@@ -136,6 +204,8 @@ fapi2::ReturnCode p9_pm_reset(
     //  Issue reset to OCC GPEs ( GPE0 and GPE1) (Bring them to HALT)
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_occ_gpe_init to reset OCC GPE");
+    l_phase = PM_RESET_OCC_GPE;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_occ_gpe_init,
                   i_target,
                   p9pm::PM_RESET,
@@ -145,21 +215,48 @@ fapi2::ReturnCode p9_pm_reset(
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of OCC GPEs"));
 
     //  ************************************************************************
+    //  Collect OCC FFDC into FFDC section in HOMER
+    //  ************************************************************************
+    FAPI_DBG("Collect FFDC from 405, GPE0 and GPE1 to HOMER");
+    FAPI_TRY ( p9_pm_collect_ffdc (i_target, i_pHomerImage, PLAT_OCC),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_OCC );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After OCC, GPE0 and GPE1 FFDC"));
+
+    //  ************************************************************************
     //  Reset the PSTATE GPE (Bring it to HALT)
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_pstate_gpe_init to reset PGPE");
+    l_phase = PM_RESET_PGPE;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_pstate_gpe_init, i_target, p9pm::PM_RESET);
     FAPI_TRY(l_rc, "ERROR: Failed to reset the PGPE");
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of PGPE"));
 
     //  ************************************************************************
+    //  Collect PGPE FFDC into FFDC section in HOMER
+    //  ************************************************************************
+    FAPI_DBG("Collect FFDC from PGPE to HOMER");
+    FAPI_TRY ( p9_pm_collect_ffdc (i_target, i_pHomerImage, PLAT_PGPE),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_PGPE );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After PGPE FFDC"));
+
+    //  ************************************************************************
     //  Reset the STOP GPE (Bring it to HALT)
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_stop_gpe_init to reset SGPE");
+    l_phase = PM_RESET_SGPE;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_stop_gpe_init, i_target, p9pm::PM_RESET);
     FAPI_TRY(l_rc, "ERROR: Failed to reset SGPE");
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of SGPE"));
 
+    //  ************************************************************************
+    //  Collect SGPE FFDC into FFDC section in HOMER
+    //  ************************************************************************
+    FAPI_DBG("Collect FFDC from SGPE to HOMER");
+    FAPI_TRY ( p9_pm_collect_ffdc ( i_target, i_pHomerImage, PLAT_SGPE),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_SGPE );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After SGPE FFDC"));
 
     //  ************************************************************************
     // Clear the OCC Flag and Scratch2 registers
@@ -171,11 +268,28 @@ fapi2::ReturnCode p9_pm_reset(
     FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCS2_SCOM, l_data64),
              "ERROR: Failed to write to OCC Scratch2 Register");
 
+    //  ************************************************************************
+    //  Collect FFDC from CPPMs into FFDC section in HOMER
+    //  ************************************************************************
+    FAPI_DBG("Collect FFDC from CPPMs to HOMER");
+    FAPI_TRY ( p9_pm_collect_ffdc (i_target, i_pHomerImage, PLAT_CPPM),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_CPPM );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After CPPMs FFDC"));
+
+    //  ************************************************************************
+    //  Collect FFDC from QPPMs into FFDC section in HOMER
+    //  ************************************************************************
+    FAPI_DBG("Collect FFDC from QPPMs to HOMER");
+    FAPI_TRY ( p9_pm_collect_ffdc (i_target, i_pHomerImage, PLAT_QPPM),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_QPPM );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After QPPMs FFDC"));
 
     //  ************************************************************************
     //  Reset Cores and Quads
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_corequad_init to reset cores & quads");
+    l_phase = PM_RESET_EC_EQ;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_corequad_init,
                   i_target,
                   p9pm::PM_RESET,
@@ -187,16 +301,27 @@ fapi2::ReturnCode p9_pm_reset(
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of core quad"));
 
     //  ************************************************************************
+    //  Collect FFDC from CMEs into FFDC section in HOMER
+    //  ************************************************************************
+    FAPI_DBG("Collect FFDC from CMEs to HOMER");
+    FAPI_TRY ( p9_pm_collect_ffdc (i_target, i_pHomerImage, PLAT_CME),
+               "PM FFDC Error, Plat: 0x%02X", PLAT_CME );
+    FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After CME FFDC"));
+
+    //  ************************************************************************
     //  Move PSAFE values to DPLL and Ext Voltage
     //  ************************************************************************
+    l_phase = PM_RESET_PSAFE_UPDATE;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_TRY(p9_pm_reset_psafe_update(i_target),
              "Error from p9_pm_reset_psafe_update");
 
-
     //  ************************************************************************
     //  Issue reset to OCC-SRAM
     //  ************************************************************************
     FAPI_DBG("Executing p8_occ_sram_init to reset OCC-SRAM");
+    l_phase = PM_RESET_OCC_SRAM;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_occ_sram_init, i_target, p9pm::PM_RESET);
     FAPI_TRY(l_rc, "ERROR: Failed to reset OCC SRAM");
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of OCC SRAM"));
@@ -205,6 +330,8 @@ fapi2::ReturnCode p9_pm_reset(
     //  Issue reset to OCB
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_ocb_init to reset OCB");
+    l_phase = PM_RESET_OCB;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_ocb_init,
                   i_target,
                   p9pm::PM_RESET,
@@ -222,12 +349,58 @@ fapi2::ReturnCode p9_pm_reset(
     //  Resets P2S and HWC logic
     //  ************************************************************************
     FAPI_DBG("Executing p9_pm_pss_init to reset P2S and HWC logic");
+    l_phase = PM_RESET_PSS;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
     FAPI_EXEC_HWP(l_rc, p9_pm_pss_init, i_target, p9pm::PM_RESET);
     FAPI_TRY(l_rc, "ERROR: Failed to reset PSS & HWC");
     FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of PSS"));
 
+    //  ************************************************************************
+    //  Trigger OCC LFIR so that bad ec/ex/eq are updated for pm_init and prd
+    //  gets a chance to deconfig cores and callout hw and grab ffdc to logs
+    //  This should be the last phase in pm reset
+    //  ************************************************************************
+    if (l_malfAlert == true)
+    {
+        const uint32_t l_OCC_LFIR_BIT_STOP_RCV_NOTIFY_PRD = 3;
+        l_phase = PM_RESET_NOTIFY_PRD;
+        FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
+
+        p9pmFIR::PMFir <p9pmFIR::FIRTYPE_OCC_LFIR> l_occFir(i_target);
+        FAPI_TRY(l_occFir.get(p9pmFIR::REG_ALL),
+                 "ERROR: Failed to get the OCC FIR values");
+        FAPI_TRY(l_occFir.setRecvAttn(l_OCC_LFIR_BIT_STOP_RCV_NOTIFY_PRD),
+                 FIR_REC_ATTN_ERROR);
+        // Not doing the restoreSavedMask, as this is a special case between reset->init
+        // and pm init handles it
+        FAPI_TRY(l_occFir.put(),
+                 "ERROR: Failed to write OCC LFIR setting for STOP_RCV_NOTIFY_PRD");
+
+        l_data64.flush<0>();
+        l_data64.setBit(l_OCC_LFIR_BIT_STOP_RCV_NOTIFY_PRD);
+
+        FAPI_IMP ("p9_pm_reset: Signalling PRD via OCCLFIR Bit 3 [STOP_RCV_NOTIFY_PRD]!");
+        FAPI_TRY(fapi2::putScom(i_target, PERV_TP_OCC_SCOM_OCCLFIR_OR, l_data64),
+                 "ERROR: Failed to write to OCC Flag Register");
+    }
+
+    l_phase = PM_RESET_DONE;
+    FAPI_TRY (FAPI_ATTR_SET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
+
 fapi_try_exit:
-    FAPI_IMP("<< p9_pm_reset");
+    //  Update PM FFDC Section Header with Miscellaneous Info
+    l_rc = p9_pm_collect_ffdc (i_target, i_pHomerImage, PLAT_MISC);
+
+    if (l_rc != fapi2::FAPI2_RC_SUCCESS)
+    {
+        FAPI_ERR ("Failed updating Miscellaneous FFDC to PM FFDC section!", PLAT_MISC );
+    }
+
+    l_pmResetActive = fapi2::ENUM_ATTR_INITIATED_PM_RESET_INACTIVE;
+    FAPI_ATTR_SET (fapi2::ATTR_INITIATED_PM_RESET, i_target, l_pmResetActive);
+
+    FAPI_ATTR_GET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase);
+    FAPI_IMP("<< p9_pm_reset: Phase 0x%02X", l_phase);
     return fapi2::current_err;
 }
 
@@ -442,3 +615,85 @@ fapi_try_exit:
     FAPI_INF("<< p9_set_auto_spwkup");
     return fapi2::current_err;
 }
+
+fapi2::ReturnCode p9_pm_collect_ffdc (
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    void* i_pHomerImage,
+    const uint8_t i_plat )
+{
+    using namespace p9_stop_recov_ffdc;
+    FAPI_DBG (">>  p9_pm_collect_ffdc: Plat %d", i_plat);
+
+    fapi2::ReturnCode l_rc;
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    fapi2::ATTR_PM_RESET_FFDC_ENABLE_Type l_ffdcEnable =
+        fapi2::ENUM_ATTR_PM_RESET_FFDC_ENABLE_FALSE;
+    fapi2::ATTR_PM_RESET_PHASE_Type l_phase = PM_RESET_UNKNOWN;
+
+    FAPI_TRY (FAPI_ATTR_GET (fapi2::ATTR_PM_RESET_PHASE, i_target, l_phase));
+    FAPI_TRY (FAPI_ATTR_GET (fapi2::ATTR_PM_RESET_FFDC_ENABLE, FAPI_SYSTEM, l_ffdcEnable));
+
+    if (l_ffdcEnable == fapi2::ENUM_ATTR_PM_RESET_FFDC_ENABLE_TRUE)
+    {
+        switch (i_plat)
+        {
+            case PLAT_INIT:
+                FAPI_INF ("Init PM FFDC sections, collect PPE and FIR states to HOMER");
+                FAPI_EXEC_HWP (l_rc, p9_pm_recovery_ffdc_base, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_CME:
+                FAPI_DBG("Collecting CME(s) FFDC to HOMER");
+                FAPI_EXEC_HWP(l_rc, p9_pm_recovery_ffdc_cme, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_SGPE:
+                FAPI_DBG("Collecting SGPE FFDC to HOMER");
+                FAPI_EXEC_HWP(l_rc, p9_pm_recovery_ffdc_sgpe, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_PGPE:
+                FAPI_DBG("Collecting PGPE FFDC to HOMER");
+                FAPI_EXEC_HWP(l_rc, p9_pm_recovery_ffdc_pgpe, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_OCC:
+                FAPI_DBG("Collecting OCC 405, GPE0 and GPE1 FFDC to HOMER");
+                FAPI_EXEC_HWP(l_rc, p9_pm_recovery_ffdc_occ, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_CPPM:
+                FAPI_DBG("Collecting CPPM(s) FFDC to HOMER");
+                FAPI_EXEC_HWP(l_rc, p9_pm_recovery_ffdc_cppm, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_QPPM:
+                FAPI_DBG("Collecting QPPM(s) FFDC to HOMER");
+                FAPI_EXEC_HWP(l_rc, p9_pm_recovery_ffdc_qppm, i_target, i_pHomerImage);
+                break;
+
+            case PLAT_MISC:
+                FAPI_DBG("Collecting Miscellaneous FFDC to HOMER");
+                l_rc = p9_pm_recovery_ffdc_misc (i_target, i_pHomerImage);
+                break;
+
+            default:
+                FAPI_ERR ("Bad Input Platform: 0x%02X .. Ignored!", i_plat);
+                l_rc = fapi2::RC_PM_RESET_FFDC_ERROR;
+                break;
+        }
+
+        FAPI_ASSERT_NOEXIT (l_rc == fapi2::FAPI2_RC_SUCCESS,
+                            fapi2::PM_RESET_FFDC_ERROR(fapi2::FAPI2_ERRL_SEV_RECOVERED)
+                            .set_CHIP_TARGET(i_target)
+                            .set_PM_RESET_PHASE(l_phase)
+                            .set_PM_FFDC_PLAT(i_plat),
+                            "Failed PM FFDC collection: Plat: 0x%02X Phase: 0x%02X",
+                            i_plat, l_phase);
+    }
+
+fapi_try_exit:
+    FAPI_DBG ( "<< p9_pm_collect_ffdc: Plat: 0x%02X Phase: 0x%02X Enabled: %d",
+               i_plat, l_phase, l_ffdcEnable );
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H
index f4e8ad6d0..af685127c 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.H
@@ -29,7 +29,7 @@
 ///
 // *HWP HWP Owner        : Greg Still <stillgs@us.ibm.com>
 // *HWP HWP Backup Owner : Prasad BG Ranganath <prasadbgr@in.ibm.com>
-// *HWP FW Owner         : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP FW Owner         : Prem S Jha <premjha2@in.ibm.com>
 // *HWP Team             : PM
 // *HWP Level            : 3
 // *HWP Consumed by      : HS
@@ -103,8 +103,21 @@ extern "C"
     fapi2::ReturnCode p9_pm_set_auto_spwkup(
         const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
 
-
-
+//------------------------------------------------------------------------------
+///
+/// @brief Call utilities to collect PM complex FFDC to FFDC section in HOMER
+///
+/// @param[in] i_target Proc Chip target
+/// @param[in] i_pHomerImage pointer to the beginning of the HOMER image buffer
+/// @param[in] i_plat Platform Id indicating which part of the PM Complex to collect.
+///                   See p9_stop_recov_ffdc::PmComplexPlatId for details
+///
+/// @return FAPI2_RC_SUCCESS on success, else error code.
+///
+    fapi2::ReturnCode p9_pm_collect_ffdc (
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        void* i_pHomerImage,
+        const uint8_t i_plat );
 }
 
 #endif // _P9_PM_RESET_H
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.mk
index c3bd7dcd6..993aeb9ad 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.mk
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.mk
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2015,2017
+# Contributors Listed Below - COPYRIGHT 2015,2018
 # [+] International Business Machines Corp.
 #
 #
@@ -25,6 +25,7 @@
 PROCEDURE=p9_pm_reset
 lib$(PROCEDURE)_DEPLIBS+=p9_pm_utils
 lib$(PROCEDURE)_DEPLIBS+=p9_setup_evid
+lib$(PROCEDURE)_DEPLIBS+=p9_pm_recovery_ffdc_base
 lib$(PROCEDURE)_EXTRALIBS+=p9_pm_occ_firinit
 lib$(PROCEDURE)_EXTRALIBS+=p9_pm_firinit
 lib$(PROCEDURE)_EXTRALIBS+=p9_pm_occ_control
@@ -35,6 +36,12 @@ lib$(PROCEDURE)_EXTRALIBS+=p9_pm_corequad_init
 lib$(PROCEDURE)_EXTRALIBS+=p9_pm_occ_sram_init
 lib$(PROCEDURE)_EXTRALIBS+=p9_pm_ocb_init
 lib$(PROCEDURE)_EXTRALIBS+=p9_pm_pss_init
+lib$(PROCEDURE)_EXTRALIBS+= p9_pm_recovery_ffdc_sgpe
+lib$(PROCEDURE)_EXTRALIBS+= p9_pm_recovery_ffdc_pgpe
+lib$(PROCEDURE)_EXTRALIBS+= p9_pm_recovery_ffdc_cme
+lib$(PROCEDURE)_EXTRALIBS+= p9_pm_recovery_ffdc_occ
+lib$(PROCEDURE)_EXTRALIBS+= p9_pm_recovery_ffdc_qppm
+lib$(PROCEDURE)_EXTRALIBS+= p9_pm_recovery_ffdc_cppm
 $(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/lib)
 $(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/common/pmlib/include/registers)
 $(call BUILD_PROCEDURE)
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
index a04a60720..88d94d847 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -70,6 +70,7 @@
 #include <p9_quad_scom_addresses_fld.H>
 #include <p9_misc_scom_addresses.H>
 #include <p9_misc_scom_addresses_fld.H>
+#include <p9n2_misc_scom_addresses.H>
 
 //#include <p9_ppe_state.H>  @todo RTC 147996 to incorporate PPE state removing strings.
 
@@ -130,6 +131,8 @@ fapi2::ReturnCode p9_pm_stop_gpe_init(
     const char* PM_MODE_NAME_VAR; //Defines storage for PM_MODE_NAME
     FAPI_INF("Executing p9_stop_gpe_init in mode %s", PM_MODE_NAME(i_mode));
 
+    fapi2::ATTR_PM_MALF_ALERT_ENABLE_Type malfAlertEnable =
+        fapi2::ENUM_ATTR_PM_MALF_ALERT_ENABLE_FALSE;
     uint8_t                 fusedModeState = 0;
     uint8_t                 coreQuiesceDis = 0;
     uint8_t                 l_core_number  = 0;
@@ -151,6 +154,12 @@ fapi2::ReturnCode p9_pm_stop_gpe_init(
                                coreQuiesceDis),
                  "Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE");
 
+        FAPI_IMP ("reading ATTR_PM_MALF_ALERT_ENABLE");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PM_MALF_ALERT_ENABLE,
+                               FAPI_SYSTEM,
+                               malfAlertEnable),
+                 "Error from FAPI_ATTR_GET for attribute ATTR_PM_MALF_ALERT_ENABLE");
+
         // Check each core has a functional EX and EQ
         auto l_functional_core_vector =
             i_target.getChildren<fapi2::TARGET_TYPE_CORE>
@@ -308,6 +317,26 @@ fapi2::ReturnCode p9_pm_stop_gpe_init(
         .insertFromRight<4, 4>(0xA);    // FIT
         FAPI_TRY(fapi2::putScom(i_target, PU_GPE3_GPETSEL_SCOM, l_data64));
 
+        // @TODO via CQ SW417195: Renable this once FW Simics support is in.
+        //       Writing OCC FLG2 breaks HB CIs
+#if 0
+        // Set the Malf Alert Enabled policy to OCCFLG2 reg bit 29
+        FAPI_IMP ("Malf Alert Policy Enabled: %d", malfAlertEnable);
+
+        l_data64.flush<0>().setBit<p9hcd::STOP_RECOVERY_TRIGGER_ENABLE>();
+
+        if (malfAlertEnable == fapi2::ENUM_ATTR_PM_MALF_ALERT_ENABLE_TRUE)
+        {
+            FAPI_TRY(fapi2::putScom(i_target, P9N2_PU_OCB_OCI_OCCFLG2_SCOM2, l_data64));
+        }
+        else
+        {
+            FAPI_TRY(fapi2::putScom(i_target, P9N2_PU_OCB_OCI_OCCFLG2_SCOM1, l_data64));
+        }
+
+        FAPI_IMP ("Malf Alert Policy Set to OCC FLAG2 .. now init SGPE");
+#endif
+
         // Boot the STOP GPE
         FAPI_TRY(stop_gpe_init(i_target), "ERROR: failed to initialize Stop GPE");
 
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml
index 9e5e2f7b6..0738ffbca 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2016,2017                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2018                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -522,7 +522,7 @@
     <id>ATTR_INITIATED_PM_RESET</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-    Attribute is set by platform before initiating PM reset.
+    Attribute is set at the start of PM reset and reset at the end.
     It act as a signal for FFDC collection utility to behave
     differently during PM reset flow.
     </description>
@@ -532,4 +532,18 @@
     <initToZero/>
   </attribute>
   <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PM_RESET_PHASE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    Attribute to indicate the progress in the PM Complex Reset flow.
+
+    Producer: p9_pm_reset.C
+    Consumers: p9_pm_reset.C p9_pm_recovery_ffdc_*.C
+    </description>
+    <valueType>uint8</valueType>
+    <initToZero/>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
 </attributes>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
index c47d19735..647a387e1 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
@@ -2229,4 +2229,39 @@
     <default>0</default>
   </attribute>
   <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PM_MALF_ALERT_ENABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+    Switch to enable or disable Power Management Malfunction Alert Handling
+    based on the platform support. e.g. True for PHYP based systems and False
+    for KVM based systems depending on support available.
+
+    Producer: Initialized by Hostboot firmware based on platform support
+    Consumers: Read by p9_pm_reset.C p9_pm_stop_gpe_init.C
+    </description>
+    <valueType>uint8</valueType>
+    <enum>FALSE = 0x00, TRUE = 0x01</enum>
+    <platInit/>
+    <default>FALSE</default>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PM_RESET_FFDC_ENABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+    Switch to enable or disable Power Management Complex FFDC collection to HOMER.
+    When set, the PM Complex Reset flow will collect PM Complex data to the chip
+    HOMER region to assist with failure analysis and recovery.
+
+    Producer: HB must set or reset this based on the platform use-case and state.
+    Consumer: p9_pm_reset.C, p9_pm_callout.C
+    </description>
+    <valueType>uint8</valueType>
+    <enum>FALSE = 0x00, TRUE = 0x01</enum>
+    <writeable/>
+    <platInit/>
+    <default>FALSE</default>
+  </attribute>
+  <!-- ********************************************************************* -->
 </attributes>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_init_errors.xml
index 97edba0e8..26d383896 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_init_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_init_errors.xml
@@ -104,4 +104,17 @@
     </callout>
   </hwpError>
   <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_PM_RESET_FFDC_ERROR</rc>
+    <description>Error collecting PM FFDC in one of the PM Reset Phase
+    </description>
+    <ffdc>CHIP_TARGET</ffdc>
+    <ffdc>PM_RESET_PHASE</ffdc>
+    <ffdc>PM_FFDC_PLAT</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ******************************************************************** -->
 </hwpErrors>