Secure memory allocation and setup

p9_mss_eff_grouping.C:
  - determines whether secure mem is requested, reserves smf space
  - always reserve smf at end of range because of end-of-range bit
  - set addr15 when reporting smf base address
  - mask off group_id(0) via chip address extension if smf is enabled
  - updated to set value of attr_smf_enabled
  - enhanced error reporting with smf config/supported values
  - made values reported to attr_mss_mcs_group_32 more clear

p9_mss_setup_bars.C:
  - set MCFGPA/MCFGPMA registers with SMF data
  - fixed scom registers for MCFGPA/MCFGPMA hole setup
  - added note to leave MCFIR_invalid_smf masked for HW451708/HW451711
  - added assert to check for HOLE1 and SMF enable overlaps

p9_query_mssinfo.C:
  - updated to print out SMF reservations
  - print out HTM/OCC/SMF reservations regardless of mirroring enable

p9_fbc_utils.C:
  - prevent group_id(0)=1 from affecting mappable memory ranges

p9_sbe_fabricinit.C:
  - mask off group_id(0) via chip address extension if smf is enabled

p9_setup_sbe_config.C, p9_sbe_attr_setup.C:
  - use scratch_reg6 bit(16) to pass smf_config value

initfiles:
  - removed setup to use other addr bits as secure bit; core only uses addr15
  - added setup for ncu addr15 value in hcode
  - always set addr15 config bit in bridge unit if smf is supported
  - set addr15 bit across all mcs if smf is enabled
  - added in settings to enable smf in nmmu unit
  - hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported

attributes:
  - ATTR_SMF_ENABLE is a system level attribute
  - changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported)

CQ:HW451708
CQ:HW451711
Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57348
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

16 files changed, 583 insertions, 45 deletions

diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C
index d9f2bdb58..58c7b19f4 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C
@@ -35,6 +35,7 @@ constexpr uint64_t literal_1 = 1;
 constexpr uint64_t literal_0x801B1F98D8717000 = 0x801B1F98D8717000;
 constexpr uint64_t literal_0x0000000000000 = 0x0000000000000;
 constexpr uint64_t literal_0b1 = 0b1;
+constexpr uint64_t literal_0b10 = 0b10;
 constexpr uint64_t literal_0b0000 = 0b0000;
 constexpr uint64_t literal_0b111 = 0b111;
 constexpr uint64_t literal_0b0010 = 0b0010;
@@ -56,6 +57,8 @@ fapi2::ReturnCode p9_cxa_scom(const fapi2::Target<fapi2::TARGET_TYPE_CAPP>& TGT0
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID));
         fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID));
+        fapi2::ATTR_SMF_CONFIG_Type l_TGT1_ATTR_SMF_CONFIG;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, TGT1, l_TGT1_ATTR_SMF_CONFIG));
         fapi2::buffer<uint64_t> l_scom_buffer;
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x2010803ull, l_scom_buffer ));
@@ -137,6 +140,15 @@ fapi2::ReturnCode p9_cxa_scom(const fapi2::Target<fapi2::TARGET_TYPE_CAPP>& TGT0
                 l_scom_buffer.insert<25, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID );
             }
 
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6)
+                    && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x13)) || ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
+            {
+                if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED))
+                {
+                    l_scom_buffer.insert<19, 2, 62, uint64_t>(literal_0b10 );
+                }
+            }
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
                     && (l_chip_ec == 0x23)) )
             {
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C
index 8fac28a73..1bf2efad1 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C
@@ -31,6 +31,7 @@ using namespace fapi2;
 
 constexpr uint64_t literal_0 = 0;
 constexpr uint64_t literal_1 = 1;
+constexpr uint64_t literal_0b10 = 0b10;
 constexpr uint64_t literal_0x0070000072040140 = 0x0070000072040140;
 constexpr uint64_t literal_0x2000004004028000 = 0x2000004004028000;
 constexpr uint64_t literal_0x20000040040281C3 = 0x20000040040281C3;
@@ -69,6 +70,8 @@ fapi2::ReturnCode p9_int_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID));
         fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID));
+        fapi2::ATTR_SMF_CONFIG_Type l_TGT1_ATTR_SMF_CONFIG;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, TGT1, l_TGT1_ATTR_SMF_CONFIG));
         fapi2::ATTR_CHIP_EC_FEATURE_HW426891_Type l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW426891, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891));
         fapi2::ATTR_CHIP_EC_FEATURE_HW411637_Type l_TGT0_ATTR_CHIP_EC_FEATURE_HW411637;
@@ -99,6 +102,15 @@ fapi2::ReturnCode p9_int_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
                 l_scom_buffer.insert<9, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID );
             }
 
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6)
+                    && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x13)) || ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
+            {
+                if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED))
+                {
+                    l_scom_buffer.insert<12, 2, 62, uint64_t>(literal_0b10 );
+                }
+            }
+
             FAPI_TRY(fapi2::putScom(TGT0, 0x501300aull, l_scom_buffer));
         }
         {
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
index b67ed43fc..58373c5cb 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
@@ -44,6 +44,7 @@ constexpr uint64_t literal_0x000000000000 = 0x000000000000;
 constexpr uint64_t literal_0x910000040F00 = 0x910000040F00;
 constexpr uint64_t literal_0x911100000F00 = 0x911100000F00;
 constexpr uint64_t literal_0x991100000F00 = 0x991100000F00;
+constexpr uint64_t literal_0b110 = 0b110;
 constexpr uint64_t literal_0b11111 = 0b11111;
 constexpr uint64_t literal_0x00E = 0x00E;
 constexpr uint64_t literal_0x000 = 0x000;
@@ -63,6 +64,8 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW414700, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_HW414700));
         fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE));
+        fapi2::ATTR_SMF_CONFIG_Type l_TGT1_ATTR_SMF_CONFIG;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, TGT1, l_TGT1_ATTR_SMF_CONFIG));
         fapi2::buffer<uint64_t> l_scom_buffer;
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5012c03ull, l_scom_buffer ));
@@ -206,6 +209,20 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             FAPI_TRY(fapi2::putScom(TGT0, 0x5012c47ull, l_scom_buffer));
         }
         {
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6)
+                    && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x13)) || ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
+            {
+                FAPI_TRY(fapi2::getScom( TGT0, 0x5012c4cull, l_scom_buffer ));
+
+                if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED))
+                {
+                    l_scom_buffer.insert<0, 3, 61, uint64_t>(literal_0b110 );
+                }
+
+                FAPI_TRY(fapi2::putScom(TGT0, 0x5012c4cull, l_scom_buffer));
+            }
+        }
+        {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5012c52ull, l_scom_buffer ));
 
             l_scom_buffer.insert<30, 1, 59, uint64_t>(literal_0b11111 );
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C
index 6736c2e69..0b0377b37 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C
@@ -71,6 +71,7 @@ constexpr uint64_t literal_0x000801A200000000 = 0x000801A200000000;
 constexpr uint64_t literal_0xFFFF0BFFF0000000 = 0xFFFF0BFFF0000000;
 constexpr uint64_t literal_0x009A48180F01FFFF = 0x009A48180F01FFFF;
 constexpr uint64_t literal_0x8005000200500000 = 0x8005000200500000;
+constexpr uint64_t literal_0b10 = 0b10;
 constexpr uint64_t literal_0x0000F40000000003 = 0x0000F40000000003;
 constexpr uint64_t literal_0xF000003FF00C0FFF = 0xF000003FF00C0FFF;
 constexpr uint64_t literal_0x0000100000024000 = 0x0000100000024000;
@@ -120,6 +121,8 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_DISABLE_NPU_FREEZE, TGT0,
                                l_TGT0_ATTR_CHIP_EC_FEATURE_DISABLE_NPU_FREEZE));
         uint64_t l_def_ENABLE_NPU_FREEZE = (l_TGT0_ATTR_CHIP_EC_FEATURE_DISABLE_NPU_FREEZE == literal_0);
+        fapi2::ATTR_SMF_CONFIG_Type l_TGT1_ATTR_SMF_CONFIG;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, TGT1, l_TGT1_ATTR_SMF_CONFIG));
         fapi2::buffer<uint64_t> l_scom_buffer;
         {
             if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
@@ -6528,6 +6531,32 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             }
         }
         {
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6)
+                    && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x13)) || ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
+            {
+                FAPI_TRY(fapi2::getScom( TGT0, 0x5013c0aull, l_scom_buffer ));
+
+                if (((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6)
+                        && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x13)) )
+                {
+                    if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED))
+                    {
+                        l_scom_buffer.insert<0, 2, 62, uint64_t>(literal_0b10 );
+                    }
+                }
+
+                if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
+                {
+                    if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED))
+                    {
+                        l_scom_buffer.insert<0, 2, 62, uint64_t>(literal_0b10 );
+                    }
+                }
+
+                FAPI_TRY(fapi2::putScom(TGT0, 0x5013c0aull, l_scom_buffer));
+            }
+        }
+        {
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
                     && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10))
                 || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6)
@@ -6801,6 +6830,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         {
             if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
             {
+                FAPI_TRY(fapi2::getScom( TGT0, 0x5013ccaull, l_scom_buffer ));
+
+                if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED))
+                {
+                    l_scom_buffer.insert<0, 2, 62, uint64_t>(literal_0b10 );
+                }
+
+                FAPI_TRY(fapi2::putScom(TGT0, 0x5013ccaull, l_scom_buffer));
+            }
+        }
+        {
+            if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
+            {
                 FAPI_TRY(fapi2::getScom( TGT0, 0x5013d03ull, l_scom_buffer ));
 
                 if (((l_def_NVLINK_ACTIVE == literal_1) && (l_def_ENABLE_NPU_FREEZE == literal_0)))
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C
index c563c6710..b08ba5471 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C
@@ -35,6 +35,7 @@ constexpr uint64_t literal_0b1 = 0b1;
 constexpr uint64_t literal_0b11 = 0b11;
 constexpr uint64_t literal_0b00 = 0b00;
 constexpr uint64_t literal_0 = 0;
+constexpr uint64_t literal_0b10 = 0b10;
 constexpr uint64_t literal_0xFC = 0xFC;
 constexpr uint64_t literal_8 = 8;
 constexpr uint64_t literal_2 = 2;
@@ -61,6 +62,8 @@ fapi2::ReturnCode p9_nx_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID));
         fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID));
+        fapi2::ATTR_SMF_CONFIG_Type l_TGT1_ATTR_SMF_CONFIG;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, TGT1, l_TGT1_ATTR_SMF_CONFIG));
         fapi2::buffer<uint64_t> l_scom_buffer;
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x2011041ull, l_scom_buffer ));
@@ -665,6 +668,15 @@ fapi2::ReturnCode p9_nx_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
                 l_scom_buffer.insert<60, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID );
             }
 
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6)
+                    && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x13)) || ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
+            {
+                if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED))
+                {
+                    l_scom_buffer.insert<34, 2, 62, uint64_t>(literal_0b10 );
+                }
+            }
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5)
                     && (l_chip_ec == 0x23)) )
             {
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C
index 801ba3aaf..fa2710824 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C
@@ -35,6 +35,7 @@ constexpr uint64_t literal_0 = 0;
 constexpr uint64_t literal_0x00DD0201C0000000 = 0x00DD0201C0000000;
 constexpr uint64_t literal_0x00DF0201C0000000 = 0x00DF0201C0000000;
 constexpr uint64_t literal_0x0080000000000000 = 0x0080000000000000;
+constexpr uint64_t literal_0b10 = 0b10;
 constexpr uint64_t literal_0x1 = 0x1;
 constexpr uint64_t literal_0xFC = 0xFC;
 
@@ -52,6 +53,8 @@ fapi2::ReturnCode p9_vas_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID));
         fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID));
+        fapi2::ATTR_SMF_CONFIG_Type l_TGT1_ATTR_SMF_CONFIG;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, TGT1, l_TGT1_ATTR_SMF_CONFIG));
         fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE));
         fapi2::buffer<uint64_t> l_scom_buffer;
@@ -118,29 +121,32 @@ fapi2::ReturnCode p9_vas_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             }
         }
         {
-            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5)
-                    && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23))
-                || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6)
-                        && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x13)) )
-            {
-                FAPI_TRY(fapi2::getScom( TGT0, 0x301184dull, l_scom_buffer ));
+            FAPI_TRY(fapi2::getScom( TGT0, 0x301184dull, l_scom_buffer ));
 
-                if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
-                        && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10))
-                    || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6)
-                            && (l_chip_ec == 0x13)) )
-                {
-                    l_scom_buffer.insert<0, 4, 60, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID );
-                    l_scom_buffer.insert<4, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID );
-                }
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10))
+                || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6)
+                        && (l_chip_ec == 0x13)) )
+            {
+                l_scom_buffer.insert<0, 4, 60, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID );
+                l_scom_buffer.insert<4, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID );
+            }
 
-                if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6)
+                    && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x13)) || ((l_chip_id == 0x7) && (l_chip_ec == 0x10)) )
+            {
+                if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED))
                 {
-                    l_scom_buffer.insert<19, 1, 63, uint64_t>(literal_0x1 );
+                    l_scom_buffer.insert<11, 2, 62, uint64_t>(literal_0b10 );
                 }
+            }
 
-                FAPI_TRY(fapi2::putScom(TGT0, 0x301184dull, l_scom_buffer));
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
+            {
+                l_scom_buffer.insert<19, 1, 63, uint64_t>(literal_0x1 );
             }
+
+            FAPI_TRY(fapi2::putScom(TGT0, 0x301184dull, l_scom_buffer));
         }
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x301184eull, l_scom_buffer ));
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C
index 24d504147..8b526c36e 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9c_mi_scom.C
@@ -44,6 +44,7 @@ constexpr uint64_t literal_1400 = 1400;
 constexpr uint64_t literal_1500 = 1500;
 constexpr uint64_t literal_0b0000000000001000000 = 0b0000000000001000000;
 constexpr uint64_t literal_0b0000000000001000 = 0b0000000000001000;
+constexpr uint64_t literal_0b10 = 0b10;
 constexpr uint64_t literal_0b01 = 0b01;
 constexpr uint64_t literal_5 = 5;
 
@@ -79,6 +80,8 @@ fapi2::ReturnCode p9c_mi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MI>& TGT0,
                                l_TGT2_ATTR_CHIP_EC_FEATURE_HW423533_P9UDD11_MDI));
         uint64_t l_def_ENABLE_AMO_CACHING = literal_1;
         uint64_t l_def_ENABLE_HWFM = literal_1;
+        fapi2::ATTR_SMF_CONFIG_Type l_TGT1_ATTR_SMF_CONFIG;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, TGT1, l_TGT1_ATTR_SMF_CONFIG));
         uint64_t l_def_ENABLE_MCU_TIMEOUTS = literal_1;
         fapi2::buffer<uint64_t> l_scom_buffer;
         {
@@ -272,6 +275,14 @@ fapi2::ReturnCode p9c_mi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MI>& TGT0,
                 l_scom_buffer.insert<46, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE2_MCHWFM_ENABLE_OFF );
             }
 
+            if (((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x13)) )
+            {
+                if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED))
+                {
+                    l_scom_buffer.insert<19, 2, 62, uint64_t>(literal_0b10 );
+                }
+            }
+
             FAPI_TRY(fapi2::putScom(TGT0, 0x5010813ull, l_scom_buffer));
         }
         {
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C
index 7c195fc9b..9b28a4810 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C
@@ -36,6 +36,7 @@ constexpr uint64_t literal_8 = 8;
 constexpr uint64_t literal_25 = 25;
 constexpr uint64_t literal_0b001111 = 0b001111;
 constexpr uint64_t literal_0b0000000000001000000 = 0b0000000000001000000;
+constexpr uint64_t literal_0b10 = 0b10;
 constexpr uint64_t literal_0b0001100000000 = 0b0001100000000;
 constexpr uint64_t literal_1350 = 1350;
 constexpr uint64_t literal_1000 = 1000;
@@ -56,6 +57,8 @@ fapi2::ReturnCode p9n_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW398139, TGT2, l_TGT2_ATTR_CHIP_EC_FEATURE_HW398139));
         fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM_Type l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM, TGT1, l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM));
+        fapi2::ATTR_SMF_CONFIG_Type l_TGT1_ATTR_SMF_CONFIG;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, TGT1, l_TGT1_ATTR_SMF_CONFIG));
         fapi2::ATTR_RISK_LEVEL_Type l_TGT1_ATTR_RISK_LEVEL;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, TGT1, l_TGT1_ATTR_RISK_LEVEL));
         fapi2::ATTR_FREQ_PB_MHZ_Type l_TGT1_ATTR_FREQ_PB_MHZ;
@@ -176,6 +179,14 @@ fapi2::ReturnCode p9n_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5010813ull, l_scom_buffer ));
 
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) )
+            {
+                if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED))
+                {
+                    l_scom_buffer.insert<19, 2, 62, uint64_t>(literal_0b10 );
+                }
+            }
+
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) )
             {
                 if ((l_TGT1_ATTR_RISK_LEVEL == literal_0))
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
index 7aef823f8..06b5a61d7 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H
@@ -237,6 +237,7 @@ HCD_CONST(SGPE_ENABLE_MEM_EARLY_DATA_SCOM_POS,    0x00008000)
 HCD_CONST(SGPE_PROC_FAB_PUMP_MODE_BIT_POS,        0x00004000)
 HCD_CONST(SGPE_CACHE_SKEWADJ_DISABLE_BIT_POS,     0x00002000)
 HCD_CONST(SGPE_CACHE_DCADJ_DISABLE_BIT_POS,       0x00001000)
+HCD_CONST(SGPE_PROC_SMF_CONFIG_BIT_POS,           0x00000800)
 
 ///24x7
 HCD_CONST(QPMR_AUX_OFFSET,                     (512 * ONE_KB))
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
index a01d20298..5cd11f3b3 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
@@ -266,6 +266,8 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
 
     fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE_Type l_extended_addressing_mode;
     fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2_Type l_hw423589_option2;
+    fapi2::ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED_Type l_smf_supported;
+    fapi2::ATTR_SMF_CONFIG_Type l_smf_config;
 
     FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_target,
              i_addr_mode,
@@ -294,6 +296,18 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
                                l_addr_extension_chip_id),
                  "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID");
 
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, FAPI_SYSTEM, l_smf_config),
+                 "Error from FAPI_ATTR_GET (ATTR_SMF_CONFIG)");
+
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED, i_target, l_smf_supported),
+                 "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED)");
+
+        // mask group_id(0) to prevent it from being exposed to callers if smf is enabled
+        if (l_smf_config && l_smf_supported)
+        {
+            l_addr_extension_group_id &= ~CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_SMF_ENABLE;
+        }
+
         // mask all but LSB, prevent regions above RA bit 21 from being exposed to callers
         l_addr_extension_chip_id &= 0x01;
 
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
index 423855624..588cf5b4a 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
@@ -72,6 +72,10 @@ const uint64_t FABRIC_CACHELINE_SIZE = 0x80;
 const uint8_t CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_HW423589_OPTION2 = 0x0;
 const uint8_t CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2 = 0x7;
 
+// chip address extension mask, for SMF_ENABLE
+// repurposes group ID(0) as secure memory indicator
+const uint8_t CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_SMF_ENABLE = 0x8;
+
 const uint64_t MAX_INTERLEAVE_GROUP_SIZE                  = 0x40000000000ULL; // 4_TB
 const uint64_t MAX_INTERLEAVE_GROUP_SIZE_HW423589_OPTION2 = 0x8000000000ULL;  // 512_GB
 
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
index 2552568a0..0149317da 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
@@ -112,6 +112,9 @@ struct EffGroupingSysAttrs
     uint8_t iv_selectiveMode = 0;        // ATTR_MEM_MIRROR_PLACEMENT_POLICY
     uint8_t iv_hwMirrorEnabled = 0;      // ATTR_MRW_HW_MIRRORING_ENABLE
     uint8_t iv_groupsAllowed = 0;        // ATTR_MSS_INTERLEAVE_ENABLE
+    uint8_t iv_smfSupported = 0;         // ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED
+    uint8_t iv_smfConfig = 0;            // ATTR_SMF_CONFIG
+    uint8_t iv_smfEnabled = 0;           // ATTR_SMF_ENABLED
 };
 
 // See doxygen in struct definition.
@@ -144,6 +147,14 @@ fapi2::ReturnCode EffGroupingSysAttrs::getAttrs()
         FAPI_DBG("Extended addressing supported: %d, HW423589 option2: %d",
                  l_extended_addressing_mode,
                  l_hw423589_option2);
+
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, FAPI_SYSTEM, iv_smfConfig),
+                 "Error from FAPI_ATTR_GET (ATTR_SMF_CONFIG)");
+
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED, l_targets.front(), iv_smfSupported),
+                 "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED)");
+
+        FAPI_DBG("SMF config: %d, supported: %d", iv_smfConfig, iv_smfSupported);
     }
 
     if (l_extended_addressing_mode)
@@ -154,6 +165,12 @@ fapi2::ReturnCode EffGroupingSysAttrs::getAttrs()
             l_addr_extension_chip_id = CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2;
         }
 
+        if (iv_smfConfig && iv_smfSupported)
+        {
+            l_addr_extension_group_id |= CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_SMF_ENABLE;
+            iv_smfEnabled = fapi2::ENUM_ATTR_SMF_ENABLED_TRUE;
+        }
+
         // enable extended addressing mode, seed attributes from defaults
         // should allow for testing alternate configurations via Cronus with const
         // attribute overrides
@@ -185,6 +202,11 @@ fapi2::ReturnCode EffGroupingSysAttrs::getAttrs()
                            l_max_interleave_group_size),
              "Error from FAPI_ATTR_SET (ATTR_MAX_INTERLEAVE_GROUP_SIZE)");
 
+    // Set smf enabled attribute
+    FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SMF_ENABLED,
+                           FAPI_SYSTEM, iv_smfEnabled),
+             "Error from FAPI_ATTR_SET (ATTR_SMF_ENABLED)");
+
     // Get mirror placement policy
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY,
                            FAPI_SYSTEM, iv_selectiveMode),
@@ -237,6 +259,7 @@ fapi2::ReturnCode EffGroupingSysAttrs::getAttrs()
     FAPI_INF("   ATTR_MEM_MIRROR_PLACEMENT_POLICY 0x%.8X", iv_selectiveMode);
     FAPI_INF("   ATTR_MRW_HW_MIRRORING_ENABLE 0x%.8X", iv_hwMirrorEnabled);
     FAPI_INF("   ATTR_MSS_INTERLEAVE_ENABLE 0x%.8X", iv_groupsAllowed);
+    FAPI_INF("   ATTR_SMF_ENABLED 0x%X", iv_smfEnabled);
 
 fapi_try_exit:
     FAPI_DBG("Exiting EffGroupingSysAttrs::getAttrs");
@@ -292,6 +315,9 @@ struct EffGroupingProcAttrs
     uint64_t iv_chtmBarSizes[NUM_OF_CHTM_REGIONS];  // ATTR_PROC_CHTM_BAR_SIZES
 
     uint64_t iv_occSandboxSize = 0; // ATTR_PROC_OCC_SANDBOX_SIZE
+
+    uint64_t iv_smfBarSize = 0;     // ATTR_PROC_SMF_BAR_SIZE
+
     uint32_t iv_fabricSystemId = 0; // ATTR_PROC_FABRIC_SYSTEM_ID
     uint8_t  iv_fabricGroupId = 0;  // ATTR_PROC_FABRIC_GROUP_ID
     uint8_t  iv_fabricChipId = 0;   // ATTR_PROC_FABRIC_CHIP_ID
@@ -354,6 +380,12 @@ fapi2::ReturnCode EffGroupingProcAttrs::getAttrs(
              "Error getting ATTR_PROC_OCC_SANDBOX_SIZE, l_rc 0x%.8X",
              (uint64_t)fapi2::current_err);
 
+    // Get Secure Memory (SMF) bar size
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_SMF_BAR_SIZE, i_target,
+                           iv_smfBarSize),
+             "Error getting ATTR_PROC_SMF_BAR_SIZE, l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
     // Get Fabric system ID
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, i_target,
                            iv_fabricSystemId),
@@ -388,6 +420,7 @@ fapi2::ReturnCode EffGroupingProcAttrs::getAttrs(
     }
 
     FAPI_INF("  ATTR_PROC_OCC_SANDBOX_SIZE 0x%.16llX", iv_occSandboxSize);
+    FAPI_INF("  ATTR_PROC_SMF_BAR_SIZE 0x%.16llX", iv_smfBarSize);
     FAPI_INF("  ATTR_PROC_FABRIC_SYSTEM_ID 0x%.8X", iv_fabricSystemId);
     FAPI_INF("  ATTR_PROC_FABRIC_GROUP_ID 0x%.8X", iv_fabricGroupId);
     FAPI_INF("  ATTR_PROC_FABRIC_CHIP_ID 0x%.8X", iv_fabricChipId);
@@ -855,6 +888,22 @@ struct EffGroupingBaseSizeData
         const EffGroupingProcAttrs& i_procAttrs);
 
     ///
+    /// @brief Setting SMF base addresses based on bar size
+    ///
+    /// @param[in] i_target       Reference to Processor Chip Target
+    /// @param[in] i_sysAttrs     System attribute settings
+    /// @param[in] i_procAttrs    Proc attribute values
+    /// @param[in] io_groupData   Effective grouping data info
+    ///
+    /// @return FAPI2_RC_SUCCESS if success, else error code.
+    ///
+    fapi2::ReturnCode setSMFBaseSizeData(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const EffGroupingSysAttrs& i_sysAttrs,
+        const EffGroupingProcAttrs& i_procAttrs,
+        EffGroupingData& io_groupData);
+
+    ///
     /// @brief setBaseSizeAttr
     /// Function that set base and size attribute values for both mirror
     /// and non-mirror based on given base/size data.
@@ -881,6 +930,7 @@ struct EffGroupingBaseSizeData
     uint64_t iv_mirror_sizes[NUM_MIRROR_REGIONS];
     uint64_t iv_mirror_sizes_ack[NUM_MIRROR_REGIONS];
 
+    uint64_t iv_smf_bar_base = 0;
     uint64_t iv_occ_sandbox_base = 0;
     uint64_t iv_nhtm_bar_base = 0;
     uint64_t iv_chtm_bar_bases[NUM_OF_CHTM_REGIONS];
@@ -1195,7 +1245,7 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr(
     {
         FAPI_ASSERT(l_mem_sizes[l_index] >= l_htmOccSize,
                     fapi2::MSS_EFF_GROUPING_HTM_OCC_BAR_NOT_POSSIBLE()
-                    .set_AJUSTED_SIZE(l_mem_sizes[l_index])
+                    .set_ADJUSTED_SIZE(l_mem_sizes[l_index])
                     .set_NHTM_TOTAL_BAR_SIZE(l_nhtmSize)
                     .set_CHTM_TOTAL_BAR_SIZE(l_chtmSize)
                     .set_OCC_SANDBOX_BAR_SIZE(i_procAttrs.iv_occSandboxSize)
@@ -1295,6 +1345,197 @@ fapi_try_exit:
     return fapi2::current_err;
 }
 
+// See description in struct definition
+fapi2::ReturnCode EffGroupingBaseSizeData::setSMFBaseSizeData(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const EffGroupingSysAttrs& i_sysAttrs,
+    const EffGroupingProcAttrs& i_procAttrs,
+    EffGroupingData& io_groupData)
+{
+    FAPI_DBG("Entering");
+
+    // Hold mem bases & sizes for mirror/non-mirror
+    uint64_t l_mem_bases[NUM_NON_MIRROR_REGIONS];
+    uint64_t l_mem_sizes[NUM_NON_MIRROR_REGIONS];
+    uint64_t l_smf_bases[NUM_NON_MIRROR_REGIONS];
+    uint64_t l_smf_sizes[NUM_NON_MIRROR_REGIONS];
+    uint64_t l_smf_valid[NUM_NON_MIRROR_REGIONS];
+    uint8_t  l_numRegions = 0;
+    uint8_t  l_memHole = 0;
+    uint8_t  l_index = 0;
+    uint64_t l_accMemSize = 0;
+    uint64_t l_totalSize = 0;
+    uint64_t l_memSizeAfterSmf = 0;
+
+    // Set local variables with attribute values
+    uint64_t l_smfTotalSize = i_procAttrs.iv_smfBarSize;
+    uint64_t l_smfSupported = i_sysAttrs.iv_smfSupported;
+    uint64_t l_smfConfig = i_sysAttrs.iv_smfConfig;
+    uint64_t l_smfEnabled = i_sysAttrs.iv_smfEnabled;
+
+    // No SMF space requested, exit
+    if (l_smfTotalSize == 0)
+    {
+        FAPI_INF("setSMFBaseSizeData: No SMF memory requested.");
+        goto fapi_try_exit;
+    }
+
+    // Determine whether secure memory region can be enabled
+    FAPI_ASSERT(l_smfEnabled != 0,
+                fapi2::MSS_EFF_GROUPING_SMF_NOT_ENABLED_OR_SUPPORTED()
+                .set_SMF_SUPPORTED(l_smfSupported)
+                .set_SMF_CONFIG(l_smfConfig)
+                .set_SMF_ENABLED(l_smfEnabled)
+                .set_SMF_TOTAL_BAR_SIZE(l_smfTotalSize),
+                "EffGroupingBaseSizeData::setSMFBaseSizeData: Requirements to "
+                "enable a secure memory space not met. "
+                "smfSupported 0x%llX, smfConfig 0x%llX, smfEnabled 0x%llX, smfSize 0x%.16llX",
+                l_smfSupported, l_smfConfig, l_smfEnabled, l_smfTotalSize);
+
+    // Setup mem base and size working array depending on mirror setting
+    if (i_sysAttrs.iv_selectiveMode ==
+        fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL)   // Normal
+    {
+        l_numRegions = NUM_NON_MIRROR_REGIONS;
+        memcpy(l_mem_bases, iv_mem_bases, sizeof(iv_mem_bases));
+        memcpy(l_mem_sizes, iv_memory_sizes,  sizeof(iv_memory_sizes));
+    }
+    else // Flipped
+    {
+        l_numRegions = NUM_MIRROR_REGIONS;
+        memcpy(l_mem_bases, iv_mirror_bases, sizeof(iv_mirror_bases));
+        memcpy(l_mem_sizes, iv_mirror_sizes, sizeof(iv_mirror_sizes));
+    }
+
+    // Setup smf base and size working array
+    memset(l_smf_valid, 0, sizeof(l_smf_valid));
+    memset(l_smf_bases, 0, sizeof(l_smf_bases));
+    memset(l_smf_sizes, 0, sizeof(l_smf_sizes));
+
+    // Calculate total available memory
+    for (uint8_t ii = 0; ii < l_numRegions; ii++)
+    {
+        l_totalSize += l_mem_sizes[ii];
+
+        for (uint8_t jj = 0; jj < NUM_OF_ALT_MEM_REGIONS; jj++)
+        {
+            if (io_groupData.iv_data[ii][ALT_VALID(jj)])
+            {
+                l_memHole++;
+            }
+        }
+    }
+
+    FAPI_INF("Total memory size = %.16lld bytes (%d GB) , l_memHole %d",
+             l_totalSize, l_totalSize >> 30, l_memHole);
+
+    // Error if total memory is not enough for requested SMF
+    FAPI_ASSERT(l_totalSize >= l_smfTotalSize,
+                fapi2::MSS_EFF_GROUPING_NO_SPACE_FOR_SMF_BAR()
+                .set_TOTAL_SIZE(l_totalSize)
+                .set_SMF_TOTAL_BAR_SIZE(l_smfTotalSize)
+                .set_MIRROR_PLACEMENT_POLICY(i_sysAttrs.iv_selectiveMode),
+                "EffGroupingBaseSizeData::setSMFBaseSizeData: Required memory "
+                "space for requested SMF BAR is not available. "
+                "Placement policy %u, MemSize 0x%.16llX, SmfSize 0x%.16llX",
+                i_sysAttrs.iv_selectiveMode, l_totalSize, l_smfTotalSize);
+
+    // Calculate which memory region the SMF memory starts
+    l_memSizeAfterSmf = l_totalSize - l_smfTotalSize;
+    FAPI_DBG("Memsize available after SMF: %.16lld (%d GB)",
+             l_memSizeAfterSmf, l_memSizeAfterSmf >> 30);
+
+    l_index = getMemoryRegionIndex(l_mem_bases[0] + l_memSizeAfterSmf,
+                                   i_sysAttrs,
+                                   l_accMemSize);
+
+    // Adjusted memory size for region where SMF starts
+    l_mem_sizes[l_index] = l_mem_sizes[l_index] -
+                           (l_accMemSize - l_memSizeAfterSmf);
+
+    FAPI_DBG("Adjusted memsize at index - l_mem_sizes[%d] = %.16lld (%d GB)",
+             l_index,  l_mem_sizes[l_index], l_mem_sizes[l_index] >> 30);
+
+    if (l_memHole)
+    {
+        FAPI_ASSERT(l_mem_sizes[l_index] >= l_smfTotalSize,
+                    fapi2::MSS_EFF_GROUPING_SMF_BAR_NOT_POSSIBLE()
+                    .set_ADJUSTED_SIZE(l_mem_sizes[l_index])
+                    .set_SMF_TOTAL_BAR_SIZE(l_smfTotalSize)
+                    .set_MIRROR_PLACEMENT_POLICY(i_sysAttrs.iv_selectiveMode),
+                    "EffGroupingBaseSizeData::setSMFBaseSizeData: Memory SMF "
+                    "BAR not possible, Placement policy %u, "
+                    "MemorySizes[%d] 0x%.16llX, SmfSize 0x%.16llX",
+                    i_sysAttrs.iv_selectiveMode, l_index, l_mem_sizes[l_index],
+                    l_smfTotalSize);
+    }
+
+    // Setting SMF base address for ATTR_PROC_SMF_BAR_BASE_ADDR
+    // Also sets addr(15) to indicate secure memory base address
+    iv_smf_bar_base = l_mem_bases[l_index] + l_mem_sizes[l_index];
+    iv_smf_bar_base |= ((uint64_t)1 << (63 - 15));
+
+    // Allocate SMF base address and size for region where SMF starts
+    l_smf_bases[l_index] = l_mem_bases[l_index] + l_mem_sizes[l_index];
+    l_smf_sizes[l_index] = (l_accMemSize - l_memSizeAfterSmf);
+    l_smf_valid[l_index] = 1;
+
+    // Redefine memory region for SMF and zero out memory size of regions used by SMF
+    for (uint8_t ii = l_index + 1; ii < l_numRegions; ii++)
+    {
+        l_smf_bases[ii] = l_mem_bases[ii];
+        l_smf_sizes[ii] = l_mem_sizes[ii];
+        l_mem_sizes[ii] = 0;
+
+        if (l_smf_sizes[ii] != 0)
+        {
+            l_smf_valid[ii] = 1;
+        }
+    }
+
+    // Update mem sizes with working array values
+    if (l_numRegions == NUM_NON_MIRROR_REGIONS)
+    {
+        memcpy(iv_memory_sizes, l_mem_sizes, sizeof(iv_memory_sizes));
+    }
+    else
+    {
+        memcpy(iv_mirror_sizes, l_mem_sizes, sizeof(iv_mirror_sizes));
+    }
+
+    // Update SMF data in groupData variable for ATTR_MSS_MCS_GROUP_32
+    // Note: Lower address is compared against addr(22:35)
+    for (uint8_t ii = 0; ii < io_groupData.iv_numGroups; ii++)
+    {
+        io_groupData.iv_data[ii][SMF_VALID] = l_smf_valid[ii];
+        io_groupData.iv_data[ii][SMF_SIZE] = l_smf_sizes[ii] >> (63 - 35);
+        io_groupData.iv_data[ii][SMF_BASE_ADDR] = l_smf_bases[ii] >> (63 - 35);
+    }
+
+    // Result traces
+    FAPI_INF("EffGroupingBaseSizeData::setSMFBaseSizeData");
+    FAPI_INF("  Placement policy %u, total mem %.16lld (%d GB), smfSize %.16lld (%d GB)",
+             i_sysAttrs.iv_selectiveMode, l_totalSize, l_totalSize >> 30,
+             l_smfTotalSize, l_smfTotalSize >> 30);
+
+    for (uint8_t ii = 0; ii < l_numRegions; ii++)
+    {
+        FAPI_INF("  Index: %d, iv_mem_bases 0x%.16llX, iv_memory_sizes 0x%.16llX",
+                 ii, l_mem_bases[ii], l_mem_sizes[ii]);
+    }
+
+    FAPI_INF("SMF_BASE  %.16lld (%d GB)", iv_smf_bar_base, iv_smf_bar_base >> 30);
+
+    for (uint8_t ii = 0; ii < l_numRegions; ii++)
+    {
+        FAPI_INF("  Index: %d, iv_smf_bases 0x%.16llX, iv_smf_sizes    0x%.16llX",
+                 ii, l_smf_bases[ii], l_smf_sizes[ii]);
+    }
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
 
 // See description in struct definition
 fapi2::ReturnCode EffGroupingBaseSizeData::setBaseSizeAttr(
@@ -1338,7 +1579,7 @@ fapi2::ReturnCode EffGroupingBaseSizeData::setBaseSizeAttr(
     // Set ATTR_PROC_NHTM_BAR_BASE_ADDR
     FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_NHTM_BAR_BASE_ADDR, i_target,
                            iv_nhtm_bar_base),
-             "Error setting ATTR_PROC_HTM_BAR_BASE_ADDR, "
+             "Error setting ATTR_PROC_NHTM_BAR_BASE_ADDR, "
              "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
 
     // Set ATTR_PROC_CHTM_BAR_BASE_ADDR
@@ -1353,6 +1594,12 @@ fapi2::ReturnCode EffGroupingBaseSizeData::setBaseSizeAttr(
              "Error setting ATTR_PROC_OCC_SANDBOX_BASE_ADDR, l_rc 0x%.8X",
              (uint64_t)fapi2::current_err);
 
+    // Set ATTR_PROC_SMF_BAR_BASE_ADDR
+    FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_SMF_BAR_BASE_ADDR, i_target,
+                           iv_smf_bar_base),
+             "Error setting ATTR_PROC_SMF_BAR_BASE_ADDR, "
+             "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
+
     // Mirror mode attribute setting
     if (i_sysAttrs.iv_hwMirrorEnabled != fapi2::ENUM_ATTR_MRW_HW_MIRRORING_ENABLE_FALSE)
     {
@@ -1414,6 +1661,9 @@ fapi2::ReturnCode EffGroupingBaseSizeData::setBaseSizeAttr(
     FAPI_INF("ATTR_PROC_OCC_SANDBOX_BASE_ADDR: 0x%.16llX (%d GB)",
              iv_occ_sandbox_base, iv_occ_sandbox_base >> 30);
 
+    FAPI_INF("ATTR_PROC_SMF_BAR_BASE_ADDR : 0x%.16llX (%d GB)",
+             iv_smf_bar_base, iv_smf_bar_base >> 30);
+
     // Display mirror mode attribute values
     if (i_sysAttrs.iv_hwMirrorEnabled != fapi2::ENUM_ATTR_MRW_HW_MIRRORING_ENABLE_FALSE)
     {
@@ -3469,6 +3719,12 @@ fapi2::ReturnCode p9_mss_eff_grouping(
     // Set memory base and size
     l_baseSizeData.setBaseSizeData(l_sysAttrs, l_groupData);
 
+    // Set SMF base addresses
+    FAPI_TRY(l_baseSizeData.setSMFBaseSizeData(i_target, l_sysAttrs,
+             l_procAttrs, l_groupData),
+             "setSMFBaseSizeData() returns error l_rc 0x%.8X",
+             (uint64_t)fapi2::current_err);
+
     // Set HTM/OCC base addresses
     FAPI_TRY(l_baseSizeData.set_HTM_OCC_base_addr(i_target, l_sysAttrs,
              l_groupData, l_procAttrs),
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.H b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.H
index 3f4f2f465..6b9e5370a 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -55,7 +55,7 @@
 // Constants used for EffGroupingData struct
 const uint8_t DATA_GROUPS   = 16;   // 8 regular groups, 8 mirrored groups
 const uint8_t MIRR_OFFSET   = 8;    // Start of mirrored offset in DATA_GROUPS
-const uint8_t DATA_ELEMENTS = 18;   // 18 items of data for each group
+const uint8_t DATA_ELEMENTS = 21;   // 21 items of data for each group
 
 // Indexes used for EffGroupingData::iv_data DATA ELEMENTS
 const uint8_t PORT_SIZE = 0;         // Memory size of each port in group (GB)
@@ -63,9 +63,12 @@ const uint8_t PORTS_IN_GROUP = 1;    // Number of ports in group
 const uint8_t GROUP_SIZE = 2;        // Memory size of entire group (GB)
 const uint8_t BASE_ADDR = 3;         // Base Address
 #define MEMBER_IDX(X) ((X) + 4)      // List of MC ports in group
-#define ALT_VALID(X) ((X) + 12)      // Alt Memory valid (2 alt memory regions)
+#define ALT_VALID(X) ((X) + 12)      // Alt Memory Valid (2 alt memory regions)
 #define ALT_SIZE(X) ((X) + 14)       // Alt Memory Size
 #define ALT_BASE_ADDR(X) ((X) + 16)  // Alt Base Address
+const uint8_t SMF_VALID = 18;        // SMF Memory Valid
+const uint8_t SMF_SIZE = 19;         // SMF Memory Size
+const uint8_t SMF_BASE_ADDR = 20;    // SMF Base Address
 
 // Number of memory regions
 const uint8_t NUM_NON_MIRROR_REGIONS = 8;
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C
index a2ca88232..d43001262 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C
@@ -42,6 +42,8 @@
 #include <p9_mss_eff_grouping.H>
 #include <p9_mc_scom_addresses.H>
 #include <p9_mc_scom_addresses_fld.H>
+#include <p9n2_mc_scom_addresses.H>
+#include <p9n2_mc_scom_addresses_fld.H>
 #include <map>
 #include <generic/memory/lib/utils/memory_size.H>
 
@@ -125,7 +127,7 @@ struct mcPortGroupInfo_t
      */
     inline mcPortGroupInfo_t()
         : myGroup(0), numPortsInGroup(0), groupSize(0), groupBaseAddr(0),
-          channelId(0)
+          channelId(0), smfMemValid(0), smfMemSize(0), smfBaseAddr(0)
     {
         memset(altMemValid, 0, sizeof(altMemValid));
         memset(altMemSize, 0, sizeof(altMemSize));
@@ -146,6 +148,11 @@ struct mcPortGroupInfo_t
     uint8_t altMemValid[NUM_OF_ALT_MEM_REGIONS];
     uint32_t altMemSize[NUM_OF_ALT_MEM_REGIONS];
     uint32_t altBaseAddr[NUM_OF_ALT_MEM_REGIONS];
+
+    // SMF_MEM
+    uint8_t smfMemValid;
+    uint32_t smfMemSize;
+    uint32_t smfBaseAddr;
 };
 
 /**
@@ -162,7 +169,9 @@ struct mcBarData_t
         : MCFGP_valid(false), MCFGP_chan_per_group(0),
           MCFGP_chan0_group_member_id(0), MCFGP_chan1_group_member_id(0),
           MCFGP_group_size(0), MCFGP_groupBaseAddr(0),
-          MCFGPM_valid(false), MCFGPM_group_size(0), MCFGPM_groupBaseAddr(0)
+          MCFGPM_valid(false), MCFGPM_group_size(0), MCFGPM_groupBaseAddr(0),
+          MCFGPA_SMF_valid(0), MCFGPA_SMF_LOWER_addr(0), MCFGPA_SMF_UPPER_addr(0),
+          MCFGPMA_SMF_valid(0), MCFGPMA_SMF_LOWER_addr(0), MCFGPMA_SMF_UPPER_addr(0)
     {
         memset(MCFGPA_HOLE_valid, 0, sizeof(MCFGPA_HOLE_valid));
         memset(MCFGPA_HOLE_LOWER_addr, 0, sizeof(MCFGPA_HOLE_LOWER_addr));
@@ -190,11 +199,17 @@ struct mcBarData_t
     bool     MCFGPA_HOLE_valid[NUM_OF_ALT_MEM_REGIONS];
     uint32_t MCFGPA_HOLE_LOWER_addr[NUM_OF_ALT_MEM_REGIONS];
     uint32_t MCFGPA_HOLE_UPPER_addr[NUM_OF_ALT_MEM_REGIONS];
+    bool     MCFGPA_SMF_valid;
+    uint32_t MCFGPA_SMF_LOWER_addr;
+    uint32_t MCFGPA_SMF_UPPER_addr;
 
     // Info to program MCFGPMA reg
     bool     MCFGPMA_HOLE_valid[NUM_OF_ALT_MEM_REGIONS];
     uint32_t MCFGPMA_HOLE_LOWER_addr[NUM_OF_ALT_MEM_REGIONS];
     uint32_t MCFGPMA_HOLE_UPPER_addr[NUM_OF_ALT_MEM_REGIONS];
+    bool     MCFGPMA_SMF_valid;
+    uint32_t MCFGPMA_SMF_LOWER_addr;
+    uint32_t MCFGPMA_SMF_UPPER_addr;
 };
 
 ///----------------------------------------------------------------------------
@@ -707,6 +722,33 @@ fapi2::ReturnCode getNonMirrorBarData(const fapi2::Target<T>& i_mcTarget,
 
     }
 
+    // SMF Section of MCFGPA and MCFGPMA
+    if ( i_portInfo[0].smfMemValid )
+    {
+        o_mcBarData.MCFGPA_SMF_valid = 1;
+        o_mcBarData.MCFGPA_SMF_LOWER_addr = i_portInfo[0].smfBaseAddr;
+        o_mcBarData.MCFGPA_SMF_UPPER_addr = i_portInfo[0].smfBaseAddr + i_portInfo[0].smfMemSize;
+    }
+    else
+    {
+        o_mcBarData.MCFGPA_SMF_valid = 0;
+        o_mcBarData.MCFGPA_SMF_LOWER_addr = 0;
+        o_mcBarData.MCFGPA_SMF_UPPER_addr = 0;
+    }
+
+    if ( i_portInfo[1].smfMemValid )
+    {
+        o_mcBarData.MCFGPMA_SMF_valid = 1;
+        o_mcBarData.MCFGPMA_SMF_LOWER_addr = i_portInfo[1].smfBaseAddr;
+        o_mcBarData.MCFGPMA_SMF_UPPER_addr = i_portInfo[1].smfBaseAddr + i_portInfo[1].smfMemSize;
+    }
+    else
+    {
+        o_mcBarData.MCFGPMA_SMF_valid = 0;
+        o_mcBarData.MCFGPMA_SMF_LOWER_addr = 0;
+        o_mcBarData.MCFGPMA_SMF_UPPER_addr = 0;
+    }
+
 fapi_try_exit:
     FAPI_DBG("Exit");
     return fapi2::current_err;
@@ -933,6 +975,14 @@ void getPortData(const bool i_nonMirror,
                         o_portInfo[l_mcPortNum].altBaseAddr[ii] = i_groupData[l_group][ALT_BASE_ADDR(ii)];
                     }
                 }
+
+                // SMF memory regions
+                if (i_groupData[l_group][SMF_VALID])
+                {
+                    o_portInfo[l_mcPortNum].smfMemValid = 1;
+                    o_portInfo[l_mcPortNum].smfMemSize = i_groupData[l_group][SMF_SIZE];
+                    o_portInfo[l_mcPortNum].smfBaseAddr = i_groupData[l_group][SMF_BASE_ADDR];
+                }
             }
 
         } // Port loop
@@ -1224,6 +1274,14 @@ fapi2::ReturnCode writeMCBarData(
         // 3. ---- Set MCFGPA reg -----
         l_scomData = 0;
 
+        // Assert if both HOLE1 and SMF are valid, settings will overlap
+        FAPI_ASSERT((l_data.MCFGPA_HOLE_valid[1] && l_data.MCFGPA_SMF_valid) == 0,
+                    fapi2::MSS_SETUP_BARS_HOLE1_SMF_CONFLICT()
+                    .set_TARGET(l_target)
+                    .set_HOLE1_VALID(l_data.MCFGPA_HOLE_valid[1])
+                    .set_SMF_VALID(l_data.MCFGPA_SMF_valid),
+                    "Error: MCFGPA HOLE1 and SMF are both valid, settings will overlap");
+
         // Hole 0
         if (l_data.MCFGPA_HOLE_valid[0] == true)
         {
@@ -1242,14 +1300,14 @@ fapi2::ReturnCode writeMCBarData(
             // 0b0000000001 = 4GB
             l_scomData.insertFromRight<MCS_MCFGPA_HOLE0_UPPER_ADDRESS,
                                        MCS_MCFGPA_HOLE0_UPPER_ADDRESS_LEN>(
-                                           (l_data.MCFGPMA_HOLE_UPPER_addr[0] >> 2));
+                                           (l_data.MCFGPA_HOLE_UPPER_addr[0] >> 2));
         }
 
         // Hole 1
         if (l_data.MCFGPA_HOLE_valid[1] == true)
         {
             // MCFGPA HOLE1 valid (bit 0)
-            l_scomData.setBit<MCS_MCFGPA_HOLE0_VALID>();
+            l_scomData.setBit<MCS_MCFGPA_HOLE1_VALID>();
 
             // MCFGPA_HOLE1_UPPER_ADDRESS_AT_END_OF_RANGE
             setUpperAddrEndOfRangeBit(l_target, l_scomData);
@@ -1263,7 +1321,26 @@ fapi2::ReturnCode writeMCBarData(
             // 0b0000000001 = 4GB
             l_scomData.insertFromRight<MCS_MCFGPA_HOLE1_UPPER_ADDRESS,
                                        MCS_MCFGPA_HOLE1_UPPER_ADDRESS_LEN>(
-                                           (l_data.MCFGPMA_HOLE_UPPER_addr[1] >> 2));
+                                           (l_data.MCFGPA_HOLE_UPPER_addr[1] >> 2));
+        }
+
+        // SMF
+        if (l_data.MCFGPA_SMF_valid == true)
+        {
+            // MCFGPA SMF valid (bit 0)
+            l_scomData.setBit<P9N2_MCS_MCFGPA_SMF_VALID>();
+
+            // MCFGPA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE
+            l_scomData.setBit<P9N2_MCS_MCFGPA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE>();
+
+            // SMF lower addr
+            l_scomData.insertFromRight<P9N2_MCS_MCFGPA_SMF_LOWER_ADDRESS,
+                                       P9N2_MCS_MCFGPA_SMF_LOWER_ADDRESS_LEN>(
+                                           (l_data.MCFGPA_SMF_LOWER_addr));
+            // SMF upper addr
+            l_scomData.insertFromRight<P9N2_MCS_MCFGPA_SMF_UPPER_ADDRESS,
+                                       P9N2_MCS_MCFGPA_SMF_UPPER_ADDRESS_LEN>(
+                                           (l_data.MCFGPA_SMF_UPPER_addr));
         }
 
         // Write to reg
@@ -1275,6 +1352,14 @@ fapi2::ReturnCode writeMCBarData(
         // 4. ---- Set MCFGPMA reg -----
         l_scomData = 0;
 
+        // Assert if both HOLE1 and SMF are valid, settings will overlap
+        FAPI_ASSERT((l_data.MCFGPMA_HOLE_valid[1] && l_data.MCFGPMA_SMF_valid) == 0,
+                    fapi2::MSS_SETUP_BARS_HOLE1_SMF_CONFLICT()
+                    .set_TARGET(l_target)
+                    .set_HOLE1_VALID(l_data.MCFGPMA_HOLE_valid[1])
+                    .set_SMF_VALID(l_data.MCFGPMA_SMF_valid),
+                    "Error: MCFGPMA HOLE1 and SMF are both valid, settings will overlap");
+
         // Hole 0
         if (l_data.MCFGPMA_HOLE_valid[0] == true)
         {
@@ -1317,6 +1402,25 @@ fapi2::ReturnCode writeMCBarData(
                                            (l_data.MCFGPMA_HOLE_UPPER_addr[1] >> 2));
         }
 
+        // SMF
+        if (l_data.MCFGPMA_SMF_valid == true)
+        {
+            // MCFGPMA SMF valid (bit 0)
+            l_scomData.setBit<P9N2_MCS_MCFGPMA_SMF_VALID>();
+
+            // MCFGPMA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE
+            l_scomData.setBit<P9N2_MCS_MCFGPMA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE>();
+
+            // SMF lower addr
+            l_scomData.insertFromRight<P9N2_MCS_MCFGPMA_SMF_LOWER_ADDRESS,
+                                       P9N2_MCS_MCFGPMA_SMF_LOWER_ADDRESS_LEN>(
+                                           (l_data.MCFGPMA_SMF_LOWER_addr));
+            // SMF upper addr
+            l_scomData.insertFromRight<P9N2_MCS_MCFGPMA_SMF_UPPER_ADDRESS,
+                                       P9N2_MCS_MCFGPMA_SMF_UPPER_ADDRESS_LEN>(
+                                           (l_data.MCFGPMA_SMF_UPPER_addr));
+        }
+
         // Write to reg
         FAPI_INF("Write MCFGPMA reg 0x%.16llX, Value 0x%.16llX",
                  MCS_MCFGPMA, l_scomData);
@@ -1381,6 +1485,9 @@ fapi2::ReturnCode unmaskMCFIR(
         l_mcfirmask_and.clearBit<MCS_MCFIR_MS_WAT_DEBUG_CONFIG_REG_ERROR>();
     }
 
+    // Defect HW451708, HW451711
+    // Leave MCS_MCFIR_INVALID_SMF_ACCESS masked if MCD cl_probes are enabled
+
     for (auto l_pair : i_mcBarDataPair)
     {
         fapi2::Target<T> l_target = l_pair.first;
@@ -1423,7 +1530,7 @@ fapi2::ReturnCode p9_mss_setup_bars(
 
     // Get functional MCS chiplets, should be none for Cumulus
     auto l_mcsChiplets = i_target.getChildren<fapi2::TARGET_TYPE_MCS>();
-    // Get functional MI chiplets, , should be none for Nimbus
+    // Get functional MI chiplets, should be none for Nimbus
     auto l_miChiplets = i_target.getChildren<fapi2::TARGET_TYPE_MI>();
 
     FAPI_INF("Num of MCS %u; Num of MIs %u", l_mcsChiplets.size(), l_miChiplets.size());
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
index 636f345be..91b7635bc 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
@@ -46,10 +46,10 @@
 enum P9_SETUP_SBE_CONFIG_Private_Constants
 {
     // Scratch_reg_1
-    ATTR_EQ_GARD_STARTBIT             = 0,
-    ATTR_EQ_GARD_LENGTH               = 6,
-    ATTR_EC_GARD_STARTBIT             = 8,
-    ATTR_EC_GARD_LENGTH               = 24,
+    ATTR_EQ_GARD_STARTBIT              = 0,
+    ATTR_EQ_GARD_LENGTH                = 6,
+    ATTR_EC_GARD_STARTBIT              = 8,
+    ATTR_EC_GARD_LENGTH                = 24,
 
     // Scratch_reg_2
     ATTR_I2C_BUS_DIV_REF_STARTBIT      = 0,
@@ -58,8 +58,8 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants
     ATTR_OPTICS_CONFIG_MODE_OBUS1_BIT  = 17,
     ATTR_OPTICS_CONFIG_MODE_OBUS2_BIT  = 18,
     ATTR_OPTICS_CONFIG_MODE_OBUS3_BIT  = 19,
-    ATTR_MC_PLL_BUCKET_STARTBIT      = 21,
-    ATTR_MC_PLL_BUCKET_LENGTH        = 3,
+    ATTR_MC_PLL_BUCKET_STARTBIT        = 21,
+    ATTR_MC_PLL_BUCKET_LENGTH          = 3,
     ATTR_OB0_PLL_BUCKET_STARTBIT       = 24,
     ATTR_OB0_PLL_BUCKET_LENGTH         = 2,
     ATTR_OB1_PLL_BUCKET_STARTBIT       = 26,
@@ -98,17 +98,18 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants
     ATTR_SLOW_PCI_REF_CLOCK_BIT        = 5,
 
     // Scratch_reg_6
+    ATTR_SMF_CONFIG                        = 16,
     ATTR_PROC_EFF_FABRIC_GROUP_ID_STARTBIT = 17,
-    ATTR_PROC_EFF_FABRIC_GROUP_ID_LENGTH = 3,
-    ATTR_PROC_EFF_FABRIC_CHIP_ID_STARTBIT = 20,
-    ATTR_PROC_EFF_FABRIC_CHIP_ID_LENGTH = 3,
-    ATTR_PUMP_CHIP_IS_GROUP            = 23,
-    ATTR_PROC_FABRIC_GROUP_ID_STARTBIT = 26,
-    ATTR_PROC_FABRIC_GROUP_ID_LENGTH   = 3,
-    ATTR_PROC_FABRIC_CHIP_ID_STARTBIT  = 29,
-    ATTR_PROC_FABRIC_CHIP_ID_LENGTH    = 3,
-    ATTR_PROC_MEM_TO_USE_STARTBIT = 1,
-    ATTR_PROC_MEM_TO_USE_LENGTH   = 6,
+    ATTR_PROC_EFF_FABRIC_GROUP_ID_LENGTH   = 3,
+    ATTR_PROC_EFF_FABRIC_CHIP_ID_STARTBIT  = 20,
+    ATTR_PROC_EFF_FABRIC_CHIP_ID_LENGTH    = 3,
+    ATTR_PUMP_CHIP_IS_GROUP                = 23,
+    ATTR_PROC_FABRIC_GROUP_ID_STARTBIT     = 26,
+    ATTR_PROC_FABRIC_GROUP_ID_LENGTH       = 3,
+    ATTR_PROC_FABRIC_CHIP_ID_STARTBIT      = 29,
+    ATTR_PROC_FABRIC_CHIP_ID_LENGTH        = 3,
+    ATTR_PROC_MEM_TO_USE_STARTBIT          = 1,
+    ATTR_PROC_MEM_TO_USE_LENGTH            = 6,
 };
 
 
@@ -526,6 +527,7 @@ fapi2::ReturnCode p9_setup_sbe_config(const
     }
     //set_scratch6_reg
     {
+        uint8_t l_smf_config;
         uint8_t l_pump_mode;
         uint8_t l_proc_chip_mem_to_use;
 
@@ -557,6 +559,20 @@ fapi2::ReturnCode p9_setup_sbe_config(const
             l_read_scratch_reg.setBit<24>();
         }
 
+        FAPI_DBG("Reading SMF_CONFIG");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG,
+                               fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                               l_smf_config));
+
+        if (l_smf_config == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED)
+        {
+            l_read_scratch_reg.setBit<ATTR_SMF_CONFIG>();
+        }
+        else
+        {
+            l_read_scratch_reg.clearBit<ATTR_SMF_CONFIG>();
+        }
+
         FAPI_DBG("Reading PUMP MODE");
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE,
                                fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index e8e4abe9d..b92d67fdb 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -884,7 +884,6 @@ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PRO
                            attrVal),
              "Error from FAPI_ATTR_GET for attribute ATTR_ENABLE_MEM_EARLY_DATA_SCOM");
 
-    //Attribute set to 0x01 for CHIP_IS_NODE
     if( attrVal == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_ON )
     {
         sgpeFlag |= SGPE_ENABLE_MEM_EARLY_DATA_SCOM_POS;
@@ -940,6 +939,21 @@ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PRO
 
     ///
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG,
+                           FAPI_SYSTEM,
+                           attrVal),
+             "Error from FAPI_ATTR_GET for attribute ATTR_SMF_CONFIG");
+    FAPI_DBG("SMF Config Attr Value         :   %d", attrVal );
+
+    if( attrVal )
+    {
+        sgpeFlag |= SGPE_PROC_SMF_CONFIG_BIT_POS;
+    }
+
+    FAPI_DBG("SMF Config                    :   %s", attrVal ? "TRUE" : "FALSE" );
+
+    ///
+
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CME_INSTRUCTION_TRACE_ENABLE,
                            i_procTgt,
                            attrVal),