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| author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2016-09-19 14:44:16 +0200 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-09-26 11:32:51 -0400 |
| commit | 1f8764f7c1673eb85a40ab36be14888f84e57545 (patch) | |
| tree | a0130a36c2f85c4fa81693a7af1717dd1708eb55 /src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C | |
| parent | 54d5006a06b398555c0bb5b7f190949f5c065ca2 (diff) | |
| download | talos-hostboot-1f8764f7c1673eb85a40ab36be14888f84e57545.tar.gz talos-hostboot-1f8764f7c1673eb85a40ab36be14888f84e57545.zip | |
FFDC Updates
Change-Id: I75faf871652e5320889961516b203ad5356c7843
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29885
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Deepak Kodihalli <dkodihal@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29887
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C index c35740606..18315b0ec 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -120,7 +120,11 @@ fapi2::ReturnCode p9_sbe_common_align_chiplets(const FAPI_DBG("Loop Count :%d", l_timeout); FAPI_ASSERT(l_timeout > 0, - fapi2::CPLT_NOT_ALIGNED_ERR(), + fapi2::CPLT_NOT_ALIGNED_ERR() + .set_TARGET_CHIPLET(i_target_chiplets) + .set_PERV_CPLT_STAT0(l_data64) + .set_LOOP_COUNT(l_timeout) + .set_HW_DELAY(NS_DELAY), "ERROR:CHIPLET NOT ALIGNED"); FAPI_DBG("For all chiplets: disable alignement"); @@ -185,6 +189,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_sl_clkregion_status == l_regions, fapi2::NEST_SL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_SL(l_sl_clock_status), "Clock running for sl type not matching with expected values"); } @@ -198,6 +203,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_sl_clkregion_status == l_regions, fapi2::NEST_SL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_SL(l_sl_clock_status), "Clock running for sl type not matching with expected values"); } @@ -221,6 +227,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_nsl_clkregion_status == l_regions, fapi2::NEST_NSL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_NSL(l_nsl_clock_status), "Clock running for nsl type not matching with expected values"); } @@ -234,6 +241,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_nsl_clkregion_status == l_regions, fapi2::NEST_NSL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_NSL(l_nsl_clock_status), "Clock running for nsl type not matching with expected values"); } @@ -257,6 +265,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_ary_clkregion_status == l_regions, fapi2::NEST_ARY_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_ARY(l_ary_clock_status), "Clock running for ary type not matching with expected values"); } @@ -270,6 +279,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_ary_clkregion_status == l_regions, fapi2::NEST_ARY_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_ARY(l_ary_clock_status), "Clock running for ary type not matching with expected values"); } @@ -429,7 +439,11 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const FAPI_DBG("Loop Count after CPLT_OPCG_DONE_DC polling:%d", l_timeout); FAPI_ASSERT(l_timeout > 0, - fapi2::CPLT_OPCG_DONE_NOT_SET_ERR(), + fapi2::CPLT_OPCG_DONE_NOT_SET_ERR() + .set_TARGET_CHIPLET(i_target) + .set_PERV_CPLT_STAT0(l_data64) + .set_LOOP_COUNT(l_timeout) + .set_HW_DELAY(NS_DELAY), "ERROR:CHIPLET OPCG DONE NOT SET AFTER CLOCK START STOP CMD"); //To do do checking only for chiplets that dont have Master-slave mode enabled @@ -456,6 +470,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const FAPI_ASSERT(l_sl_clock_status == l_exp_sl_clock_status, fapi2::SL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_SL(l_sl_clock_status), "CLOCK RUNNING STATUS FOR SL TYPE NOT MATCHING WITH EXPECTED VALUES"); @@ -468,6 +483,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const FAPI_ASSERT(l_nsl_clock_status == l_exp_nsl_clock_status, fapi2::NSL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_NSL(l_nsl_clock_status), "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR NSL TYPE"); @@ -480,6 +496,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const FAPI_ASSERT(l_ary_clock_status == l_exp_ary_clock_status, fapi2::ARY_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_ARY(l_ary_clock_status), "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR ARRAY TYPE"); } |
