FFDC Updates

Change-Id: I75faf871652e5320889961516b203ad5356c7843
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29885
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Deepak Kodihalli <dkodihal@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29887
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

2 files changed, 528 insertions, 58 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
index c35740606..18315b0ec 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
@@ -120,7 +120,11 @@ fapi2::ReturnCode p9_sbe_common_align_chiplets(const
     FAPI_DBG("Loop Count :%d", l_timeout);
 
     FAPI_ASSERT(l_timeout > 0,
-                fapi2::CPLT_NOT_ALIGNED_ERR(),
+                fapi2::CPLT_NOT_ALIGNED_ERR()
+                .set_TARGET_CHIPLET(i_target_chiplets)
+                .set_PERV_CPLT_STAT0(l_data64)
+                .set_LOOP_COUNT(l_timeout)
+                .set_HW_DELAY(NS_DELAY),
                 "ERROR:CHIPLET NOT ALIGNED");
 
     FAPI_DBG("For all chiplets: disable alignement");
@@ -185,6 +189,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
 
             FAPI_ASSERT(l_sl_clkregion_status == l_regions,
                         fapi2::NEST_SL_ERR()
+                        .set_TARGET_CHIPLET(i_target)
                         .set_READ_CLK_SL(l_sl_clock_status),
                         "Clock running for sl type not matching with expected values");
         }
@@ -198,6 +203,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
 
             FAPI_ASSERT(l_sl_clkregion_status == l_regions,
                         fapi2::NEST_SL_ERR()
+                        .set_TARGET_CHIPLET(i_target)
                         .set_READ_CLK_SL(l_sl_clock_status),
                         "Clock running for sl type not matching with expected values");
         }
@@ -221,6 +227,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
 
             FAPI_ASSERT(l_nsl_clkregion_status == l_regions,
                         fapi2::NEST_NSL_ERR()
+                        .set_TARGET_CHIPLET(i_target)
                         .set_READ_CLK_NSL(l_nsl_clock_status),
                         "Clock running for nsl type not matching with expected values");
         }
@@ -234,6 +241,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
 
             FAPI_ASSERT(l_nsl_clkregion_status == l_regions,
                         fapi2::NEST_NSL_ERR()
+                        .set_TARGET_CHIPLET(i_target)
                         .set_READ_CLK_NSL(l_nsl_clock_status),
                         "Clock running for nsl type not matching with expected values");
         }
@@ -257,6 +265,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
 
             FAPI_ASSERT(l_ary_clkregion_status == l_regions,
                         fapi2::NEST_ARY_ERR()
+                        .set_TARGET_CHIPLET(i_target)
                         .set_READ_CLK_ARY(l_ary_clock_status),
                         "Clock running for ary type not matching with expected values");
         }
@@ -270,6 +279,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
 
             FAPI_ASSERT(l_ary_clkregion_status == l_regions,
                         fapi2::NEST_ARY_ERR()
+                        .set_TARGET_CHIPLET(i_target)
                         .set_READ_CLK_ARY(l_ary_clock_status),
                         "Clock running for ary type not matching with expected values");
         }
@@ -429,7 +439,11 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const
     FAPI_DBG("Loop Count after CPLT_OPCG_DONE_DC polling:%d", l_timeout);
 
     FAPI_ASSERT(l_timeout > 0,
-                fapi2::CPLT_OPCG_DONE_NOT_SET_ERR(),
+                fapi2::CPLT_OPCG_DONE_NOT_SET_ERR()
+                .set_TARGET_CHIPLET(i_target)
+                .set_PERV_CPLT_STAT0(l_data64)
+                .set_LOOP_COUNT(l_timeout)
+                .set_HW_DELAY(NS_DELAY),
                 "ERROR:CHIPLET OPCG DONE NOT SET AFTER CLOCK START STOP CMD");
 
     //To do do checking only for chiplets that dont have Master-slave mode enabled
@@ -456,6 +470,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const
 
         FAPI_ASSERT(l_sl_clock_status == l_exp_sl_clock_status,
                     fapi2::SL_ERR()
+                    .set_TARGET_CHIPLET(i_target)
                     .set_READ_CLK_SL(l_sl_clock_status),
                     "CLOCK RUNNING STATUS FOR SL TYPE NOT MATCHING WITH EXPECTED VALUES");
 
@@ -468,6 +483,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const
 
         FAPI_ASSERT(l_nsl_clock_status == l_exp_nsl_clock_status,
                     fapi2::NSL_ERR()
+                    .set_TARGET_CHIPLET(i_target)
                     .set_READ_CLK_NSL(l_nsl_clock_status),
                     "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR NSL TYPE");
 
@@ -480,6 +496,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const
 
         FAPI_ASSERT(l_ary_clock_status == l_exp_ary_clock_status,
                     fapi2::ARY_ERR()
+                    .set_TARGET_CHIPLET(i_target)
                     .set_READ_CLK_ARY(l_ary_clock_status),
                     "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR ARRAY TYPE");
     }
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml
index cdd42e6ee..6642ea002 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml
@@ -25,61 +25,514 @@
 <!-- This is an automatically generated file. -->
 <!-- File: p9_sbe_common_errors.xml. -->
 <!-- Halt codes for p9_sbe_common -->
-
 <hwpErrors>
-  <!-- ******************************************************************** -->
-  <hwpError>
-    <sbeError/>
-    <rc>RC_ARY_ERR</rc>
-    <description>ary_thold status not matching the expected value in clock start stop sequence</description>
-    <ffdc>READ_CLK_ARY</ffdc>
-  </hwpError>
-  <!-- ******************************************************************** -->
-  <hwpError>
-    <sbeError/>
-    <rc>RC_NSL_ERR</rc>
-    <description>nsl_thold status not matching the expected value in clock start stop sequence</description>
-    <ffdc>READ_CLK_NSL</ffdc>
-  </hwpError>
-  <!-- ******************************************************************** -->
-  <hwpError>
-    <sbeError/>
-    <rc>RC_SL_ERR</rc>
-    <description>sl_thold status not matching the expected value in clock start stop sequence</description>
-    <ffdc>READ_CLK_SL</ffdc>
-  </hwpError>
-  <!-- ******************************************************************** -->
-  <hwpError>
-    <sbeError/>
-    <rc>RC_CPLT_NOT_ALIGNED_ERR</rc>
-    <description>Chiplet not aligned</description>
-  </hwpError>
-  <!-- ******************************************************************** -->
-  <hwpError>
-    <sbeError/>
-    <rc>RC_CPLT_OPCG_DONE_NOT_SET_ERR</rc>
-    <description>Chiplet OPCG_DONE not set after clock start/stop command</description>
-  </hwpError>
-  <!-- ******************************************************************** -->
-  <hwpError>
-    <sbeError/>
-    <rc>RC_NEST_ARY_ERR</rc>
-    <description>ary_thold status not matching the expected value in clock start stop sequence</description>
-    <ffdc>READ_CLK_ARY</ffdc>
-  </hwpError>
-  <!-- ******************************************************************** -->
-  <hwpError>
-    <sbeError/>
-    <rc>RC_NEST_NSL_ERR</rc>
-    <description>nsl_thold status not matching the expected value in clock start stop sequence</description>
-    <ffdc>READ_CLK_NSL</ffdc>
-  </hwpError>
-  <!-- ******************************************************************** -->
-  <hwpError>
-    <sbeError/>
-    <rc>RC_NEST_SL_ERR</rc>
-    <description>sl_thold status not matching the expected value in clock start stop sequence</description>
-    <ffdc>READ_CLK_SL</ffdc>
-  </hwpError>
-  <!-- ******************************************************************** --> 
+   <!-- ******************************************************************** -->
+    <registerFfdc>
+       <id>ROOT_CTRL_REGISTERS_CFAM</id>
+       <cfamRegister>PERV_ROOT_CTRL0_FSI</cfamRegister>
+       <cfamRegister>PERV_ROOT_CTRL1_FSI</cfamRegister>
+       <cfamRegister>PERV_ROOT_CTRL2_FSI</cfamRegister>
+       <cfamRegister>PERV_ROOT_CTRL3_FSI</cfamRegister>
+       <cfamRegister>PERV_ROOT_CTRL4_FSI</cfamRegister>
+       <cfamRegister>PERV_ROOT_CTRL5_FSI</cfamRegister>
+       <cfamRegister>PERV_ROOT_CTRL6_FSI</cfamRegister>
+       <cfamRegister>PERV_ROOT_CTRL7_FSI</cfamRegister>
+       <cfamRegister>PERV_ROOT_CTRL8_FSI</cfamRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>PERV_CTRL_REGISTERS_CFAM</id>
+       <cfamRegister>PERV_PERV_CTRL0_FSI</cfamRegister>
+       <cfamRegister>PERV_PERV_CTRL1_FSI</cfamRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>FSI2PIB_STATUS</id>
+       <cfamRegister>PERV_FSI2PIB_STATUS_FSI</cfamRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>OSC_SWITCH_SENSE_REGISTER_CFAM</id>
+       <cfamRegister>PERV_SNS1LTH_FSI</cfamRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>OSC_SWITCH_SENSE_REGISTER</id>
+       <scomRegister>PERV_SNS1LTH_SCOM</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>OSC_ERROR_HOLD</id>
+       <scomRegister>PERV_TP_OSCERR_HOLD</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>ROOT_CTRL_REGISTERS</id>
+       <scomRegister>PERV_ROOT_CTRL0_SCOM</scomRegister>
+       <scomRegister>PERV_ROOT_CTRL1_SCOM</scomRegister>
+       <scomRegister>PERV_ROOT_CTRL2_SCOM</scomRegister>
+       <scomRegister>PERV_ROOT_CTRL3_SCOM</scomRegister>
+       <scomRegister>PERV_ROOT_CTRL4_SCOM</scomRegister>
+       <scomRegister>PERV_ROOT_CTRL5_SCOM</scomRegister>
+       <scomRegister>PERV_ROOT_CTRL6_SCOM</scomRegister>
+       <scomRegister>PERV_ROOT_CTRL7_SCOM</scomRegister>
+       <scomRegister>PERV_ROOT_CTRL8_SCOM</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>PERV_CTRL_REGISTERS</id>
+       <scomRegister>PERV_PERV_CTRL0_SCOM</scomRegister>
+       <scomRegister>PERV_PERV_CTRL1_SCOM</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>NET_CTRL_REGISTERS</id>
+       <scomRegister>PERV_NET_CTRL0</scomRegister>
+       <scomRegister>PERV_NET_CTRL1</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>CPLT_CTRL_REGISTERS</id>
+       <scomRegister>PERV_CPLT_CTRL0</scomRegister>
+       <scomRegister>PERV_CPLT_CTRL1</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>CPLT_CONFIG_REGISTERS</id>
+       <scomRegister>PERV_CPLT_CONF0</scomRegister>
+       <scomRegister>PERV_CPLT_CONF1</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>OTHER_CPLT_REGISTERS</id>
+       <scomRegister>PERV_CPLT_STAT0</scomRegister>
+       <scomRegister>PERV_CPLT_MASK0</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>PLL_LOCK_REG</id>
+       <scomRegister>PERV_PLL_LOCK_REG</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>I2C_REGISTERS</id>
+       <scomRegister>PU_CONTROL_REGISTER_B</scomRegister>
+       <scomRegister>PU_STATUS_REGISTER_B</scomRegister>
+       <scomRegister>PU_COMMAND_REGISTER_B</scomRegister>
+       <scomRegister>PU_MODE_REGISTER_B</scomRegister>
+       <scomRegister>PU_WATER_MARK_REGISTER_B</scomRegister>
+       <scomRegister>PU_INTERRUPT_MASK_REGISTER_READ_B</scomRegister>
+       <scomRegister>PU_INTERRUPT_COND_B</scomRegister>
+       <scomRegister>PU_INTERRUPTS_B</scomRegister>
+       <scomRegister>PU_STATUS_REGISTER_ENGINE_B</scomRegister>
+       <scomRegister>PU_EXTENDED_STATUS_B</scomRegister>
+       <scomRegister>PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B</scomRegister>
+       <scomRegister>PU_I2C_BUSY_REGISTER_B</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>OPCG_CTRL_REGISTERS</id>
+       <scomRegister>PERV_OPCG_ALIGN</scomRegister>
+       <scomRegister>PERV_OPCG_REG0</scomRegister>
+       <scomRegister>PERV_OPCG_REG1</scomRegister>
+       <scomRegister>PERV_OPCG_REG2</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+       <id>CC_STATUS_REGISTERS</id>
+       <scomRegister>PERV_SCAN_REGION_TYPE</scomRegister>
+       <scomRegister>PERV_CLK_REGION</scomRegister>
+       <scomRegister>PERV_CLOCK_STAT_SL</scomRegister>
+       <scomRegister>PERV_CLOCK_STAT_NSL</scomRegister>
+       <scomRegister>PERV_CLOCK_STAT_ARY</scomRegister>
+       <scomRegister>PERV_BIST</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+        <id>ERROR_STATUS_OF_CC</id>
+        <scomRegister>PERV_ERROR_STATUS</scomRegister>
+    </registerFfdc>
+    <registerFfdc>
+        <id>CC_REGISTERS</id>
+        <scomRegister>PERV_XSTOP1</scomRegister>
+        <scomRegister>PERV_XSTOP2</scomRegister>
+        <scomRegister>PERV_XSTOP3</scomRegister>
+        <scomRegister>PERV_OPCG_CAPT1</scomRegister>
+        <scomRegister>PERV_OPCG_CAPT2</scomRegister>
+        <scomRegister>PERV_OPCG_CAPT3</scomRegister>
+        <scomRegister>PERV_DBG_CBS_CC</scomRegister>
+     </registerFfdc>    
+   <!-- ******************************************************************** -->
+    <hwpError>
+      <sbeError/>
+      <rc>RC_ARY_ERR</rc>
+      <description>ary_thold status not matching the expected value in clock start stop sequence</description>
+      <ffdc>TARGET_CHIPLET</ffdc>
+      <collectRegisterFfdc>
+	   <id>NET_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CONFIG_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OTHER_CPLT_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OPCG_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CC_STATUS_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>ERROR_STATUS_OF_CC</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>CC_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <ffdc>READ_CLK_ARY</ffdc>
+    </hwpError>
+   <!-- ******************************************************************** -->
+    <hwpError>
+      <sbeError/>
+      <rc>RC_NSL_ERR</rc>
+      <description>nsl_thold status not matching the expected value in clock start stop sequence</description>
+      <ffdc>TARGET_CHIPLET</ffdc>
+      <collectRegisterFfdc>
+	   <id>NET_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CONFIG_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OTHER_CPLT_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OPCG_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CC_STATUS_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>ERROR_STATUS_OF_CC</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>CC_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <ffdc>READ_CLK_NSL</ffdc>
+    </hwpError>
+   <!-- ******************************************************************** -->
+    <hwpError>
+      <sbeError/>
+      <rc>RC_SL_ERR</rc>
+      <description>sl_thold status not matching the expected value in clock start stop sequence</description>
+      <ffdc>TARGET_CHIPLET</ffdc>
+      <collectRegisterFfdc>
+	   <id>NET_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CONFIG_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OTHER_CPLT_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OPCG_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CC_STATUS_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>ERROR_STATUS_OF_CC</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>CC_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <ffdc>READ_CLK_SL</ffdc>
+    </hwpError>
+   <!-- ******************************************************************** -->
+    <hwpError>
+      <sbeError/>
+      <rc>RC_CPLT_NOT_ALIGNED_ERR</rc>
+      <description>Chiplet not aligned</description>
+      <ffdc>TARGET_CHIPLET</ffdc>
+      <collectRegisterFfdc>
+	   <id>NET_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CONFIG_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OTHER_CPLT_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OPCG_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CC_STATUS_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>ERROR_STATUS_OF_CC</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>CC_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <ffdc>PERV_CPLT_STAT0</ffdc>
+      <ffdc>LOOP_COUNT</ffdc>
+      <ffdc>HW_DELAY</ffdc>
+    </hwpError>
+   <!-- ******************************************************************** -->
+    <hwpError>
+      <sbeError/>
+      <rc>RC_CPLT_OPCG_DONE_NOT_SET_ERR</rc>
+      <description>Chiplet OPCG_DONE not set after clock start/stop command</description>
+      <ffdc>TARGET_CHIPLET</ffdc>
+      <collectRegisterFfdc>
+	   <id>NET_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CONFIG_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OTHER_CPLT_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OPCG_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CC_STATUS_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>ERROR_STATUS_OF_CC</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>CC_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <ffdc>PERV_CPLT_STAT0</ffdc>
+      <ffdc>LOOP_COUNT</ffdc>
+      <ffdc>HW_DELAY</ffdc>
+    </hwpError>
+   <!-- ******************************************************************** -->
+    <hwpError>
+      <sbeError/>
+      <rc>RC_NEST_ARY_ERR</rc>
+      <description>ary_thold status not matching the expected value in clock start stop sequence</description>
+      <ffdc>TARGET_CHIPLET</ffdc>
+      <collectRegisterFfdc>
+	   <id>NET_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CONFIG_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OTHER_CPLT_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OPCG_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CC_STATUS_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>ERROR_STATUS_OF_CC</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>CC_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <ffdc>READ_CLK_ARY</ffdc>
+    </hwpError>
+   <!-- ******************************************************************** -->
+    <hwpError>
+      <sbeError/>
+      <rc>RC_NEST_NSL_ERR</rc>
+      <description>nsl_thold status not matching the expected value in clock start stop sequence</description>
+      <ffdc>TARGET_CHIPLET</ffdc>
+      <collectRegisterFfdc>
+	   <id>NET_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CONFIG_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OTHER_CPLT_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OPCG_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CC_STATUS_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>ERROR_STATUS_OF_CC</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>CC_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <ffdc>READ_CLK_NSL</ffdc>
+    </hwpError>
+   <!-- ******************************************************************** -->
+    <hwpError>
+      <sbeError/>
+      <rc>RC_NEST_SL_ERR</rc>
+      <description>sl_thold status not matching the expected value in clock start stop sequence</description>
+      <ffdc>TARGET_CHIPLET</ffdc>
+      <collectRegisterFfdc>
+	   <id>NET_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CPLT_CONFIG_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OTHER_CPLT_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>OPCG_CTRL_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+     </collectRegisterFfdc>
+     <collectRegisterFfdc>
+	   <id>CC_STATUS_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>ERROR_STATUS_OF_CC</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <collectRegisterFfdc>
+	   <id>CC_REGISTERS</id>
+	   <target>TARGET_CHIPLET</target>
+	   <targetType>TARGET_TYPE_PERV</targetType>
+      </collectRegisterFfdc>
+      <ffdc>READ_CLK_SL</ffdc>
+    </hwpError>
+   <!-- ******************************************************************** -->    
 </hwpErrors>