L3 updates -- p9_rng_init_phase1, p9_rng_init_phase2

  whitespace, comment updates
  add register FFDC collection
  both errors indicate a non-functional RNG

Change-Id: Ic05d42cb6b2a2bfa0dbbe07066818775301545b9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41656
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: DHRUVARAJ SUBHASH CHANDRAN <dhruvaraj@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41657
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 63 insertions, 35 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C
index cbf075979..e265fc969 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C
@@ -32,7 +32,7 @@
 // *HWP HWP Owner: Chen Qian <qianqc@cn.ibm.com>
 // *HWP FW Owner: Thi Tran <thi@us.ibm.com>
 // *HWP Team: Nest
-// *HWP Level: 2
+// *HWP Level: 3
 // *HWP Consumed by: HB
 //
 
@@ -56,28 +56,31 @@ fapi2::ReturnCode
 p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
 {
     FAPI_INF("Start");
-
     fapi2::buffer<uint64_t> l_rng_cfg_data;
     fapi2::buffer<uint64_t> l_rng_bar_data;
     fapi2::buffer<uint64_t> l_rng_failed_int_data;
     fapi2::buffer<uint64_t> l_security_switch_data;
 
-    uint16_t  l_rng_cfg_self_test_hard_fail_status = 0;
-    uint8_t   l_nx_rng_bar_enable = 0;
-    uint64_t  l_nx_rng_bar_addr = 0;
-    uint64_t  l_nx_rng_bar_base_addr_offset = 0;
-    uint8_t   l_nx_rng_failed_int_enable = 0;
-    uint64_t  l_nx_rng_failed_int_addr = 0;
-    uint64_t  l_base_addr_nm0;
-    uint64_t  l_base_addr_nm1;
-    uint64_t  l_base_addr_m;
-    uint64_t  l_base_addr_mmio;
-    uint8_t   l_HW403701;
-
-    // 5. RNG is allowed to run for M cycles (M = enough time to complete init; recommend 1 second of time).
-    //    NOTE: accomplished by delay in execution time between phase1/phase2 HWPs
+    uint16_t l_rng_cfg_self_test_hard_fail_status = 0;
+    uint8_t  l_nx_rng_bar_enable = 0;
+    uint64_t l_nx_rng_bar_addr = 0;
+    uint64_t l_nx_rng_bar_base_addr_offset = 0;
+    uint8_t  l_nx_rng_failed_int_enable = 0;
+    uint64_t l_nx_rng_failed_int_addr = 0;
+    uint64_t l_base_addr_nm0;
+    uint64_t l_base_addr_nm1;
+    uint64_t l_base_addr_m;
+    uint64_t l_base_addr_mmio;
+    uint8_t  l_HW403701;
+
+    // 5. RNG is allowed to run for M cycles (M = enough time to complete init;
+    // recommend 1 second of time).
+    // NOTE: accomplished by delay in execution time between phase1/phase2 HWPs
+
     // get the self test hard fail status in RNG CFG register
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW403701, i_target, l_HW403701),
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW403701,
+                           i_target,
+                           l_HW403701),
              "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW403701)");
 
     FAPI_TRY(fapi2::getScom(i_target, PU_NX_RNG_CFG, l_rng_cfg_data),
@@ -85,11 +88,13 @@ p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
 
     if (!l_HW403701)
     {
-        // 6. Host boot checks RNG fail bits again and if a fail is detected then RNG is declared broken
+        // 6. Host boot checks RNG fail bits again and if a fail is detected
+        // then RNG is declared broken
 
         FAPI_DBG("Checking RNG fail status...");
         // exit if failure is reported in self test hard fail status field
-        l_rng_cfg_data.extractToRight<PU_NX_RNG_CFG_FAIL_REG, PU_NX_RNG_CFG_FAIL_REG_LEN>(l_rng_cfg_self_test_hard_fail_status);
+        l_rng_cfg_data.extractToRight<PU_NX_RNG_CFG_FAIL_REG,
+                                      PU_NX_RNG_CFG_FAIL_REG_LEN>(l_rng_cfg_self_test_hard_fail_status);
         FAPI_ASSERT(!l_rng_cfg_self_test_hard_fail_status,
                     fapi2::P9_RNG_INIT_SELF_TEST_FAILED_ERR().
                     set_TARGET(i_target).
@@ -110,8 +115,11 @@ p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     // if instructed to map the BAR:
     // - enable NX RNG MMIO BAR and get the bar address attributes
     // - optionally map NX RNG failed interrupt address
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_ENABLE, i_target, l_nx_rng_bar_enable),
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_ENABLE,
+                           i_target,
+                           l_nx_rng_bar_enable),
              "Error from FAPI_ATTR_GET (ATTR_PROC_NX_BAR_ENABLE)");
+
     FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
              EFF_FBC_GRP_CHIP_IDS,
              l_base_addr_nm0,
@@ -121,9 +129,11 @@ p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
              "Error from p9_fbc_utils_get_chip_base_address");
 
     // get RNG BAR addr
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET, i_target.getParent<fapi2::TARGET_TYPE_SYSTEM>(),
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET,
+                           i_target.getParent<fapi2::TARGET_TYPE_SYSTEM>(),
                            l_nx_rng_bar_base_addr_offset),
              "Error from FAPI_ATTR_GET (ATTR_PROC_NX_BAR_BASE_ADDR_OFFSET)");
+
     // caculate the NX RNG BAR ADDR based on the bar adddr offset
     l_nx_rng_bar_addr = l_base_addr_mmio;
     l_nx_rng_bar_addr += l_nx_rng_bar_base_addr_offset;
@@ -132,23 +142,32 @@ p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     {
         // map NX RNG MMIO BAR
         l_rng_bar_data.setBit<PU_NX_MMIO_BAR_ENABLE>();
-        l_rng_bar_data.insert<PU_NX_MMIO_BAR_BAR, PU_NX_MMIO_BAR_BAR_LEN, PU_NX_MMIO_BAR_BAR>(l_nx_rng_bar_addr);
+        l_rng_bar_data.insert<PU_NX_MMIO_BAR_BAR,
+                              PU_NX_MMIO_BAR_BAR_LEN, PU_NX_MMIO_BAR_BAR>(l_nx_rng_bar_addr);
         FAPI_TRY(fapi2::putScom(i_target, PU_NX_MMIO_BAR, l_rng_bar_data),
                  "Error from putScom (PU_NX_MMIO_BAR)");
 
         // map NX RNG failed interrupt address
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_FAILED_INT_ENABLE,  i_target, l_nx_rng_failed_int_enable),
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_FAILED_INT_ENABLE,
+                               i_target,
+                               l_nx_rng_failed_int_enable),
                  "Error from FAPI_ATTR_GET (ATTR_PROC_NX_RNG_FAILED_INT_ENABLE)");
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_FAILED_INT_ADDR, i_target, l_nx_rng_failed_int_addr),
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_FAILED_INT_ADDR,
+                               i_target,
+                               l_nx_rng_failed_int_addr),
                  "Error from FAPI_ATTR_GET (ATTR_PROC_NX_RNG_FAILED_INT_ADDR)");
 
-        if (l_nx_rng_failed_int_enable == fapi2::ENUM_ATTR_PROC_NX_RNG_FAILED_INT_ENABLE_ENABLE)
+        if (l_nx_rng_failed_int_enable ==
+            fapi2::ENUM_ATTR_PROC_NX_RNG_FAILED_INT_ENABLE_ENABLE)
         {
             l_rng_failed_int_data.setBit<PU_RNG_FAILED_INT_ENABLE>();
-            l_rng_failed_int_data.insert<PU_RNG_FAILED_INT_ADDRESS, PU_RNG_FAILED_INT_ADDRESS_LEN, PU_RNG_FAILED_INT_ADDRESS>
-            (l_nx_rng_failed_int_addr);
+            l_rng_failed_int_data.insert<PU_RNG_FAILED_INT_ADDRESS,
+                                         PU_RNG_FAILED_INT_ADDRESS_LEN, PU_RNG_FAILED_INT_ADDRESS>
+                                         (l_nx_rng_failed_int_addr);
 
-            FAPI_TRY(fapi2::putScom(i_target, PU_RNG_FAILED_INT, l_rng_failed_int_data),
+            FAPI_TRY(fapi2::putScom(i_target,
+                                    PU_RNG_FAILED_INT,
+                                    l_rng_failed_int_data),
                      "Error from putScom (NX RNG Failed Interrupt Address Register");
         }
         else
@@ -166,15 +185,24 @@ p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     FAPI_TRY(fapi2::putScom(i_target, PU_NX_RNG_CFG, l_rng_cfg_data),
              "Error from putScom (NX RNG Status and Control Register)");
 
-    // 8. Host boot sets the NX “sticky bit” that asserts tc_nx_block_rng_scom_wr. If tc_nx_block_rng_scom_wr =
-    // 1 writes to RNG SCOM register addresses 32 - 38 and 40 are blocked. An attempted write sets Power-
-    // Bus Interface FIR Data Register[Write to RNG SCOM reg detected when writes disabled].
-
-    // set NX sticky bit to block future RNG SCOM writes (tc_nx_block_rng_scom_wr)
-    FAPI_TRY(fapi2::getScom(i_target, PU_SECURITY_SWITCH_REGISTER_SCOM, l_security_switch_data),
+    // 8. Host boot sets the NX “sticky bit” that asserts
+    // tc_nx_block_rng_scom_wr. If tc_nx_block_rng_scom_wr = 1 writes to RNG
+    // SCOM register addresses 32 - 38 and 40 are blocked. An attempted
+    // write sets Power-Bus Interface FIR Data Register[Write to RNG SCOM
+    // reg detected when writes disabled].
+
+    // set NX sticky bit to block future RNG SCOM writes
+    // (tc_nx_block_rng_scom_wr)
+    FAPI_TRY(fapi2::getScom(i_target,
+                            PU_SECURITY_SWITCH_REGISTER_SCOM,
+                            l_security_switch_data),
              "Error from getScom (Security Switch Register");
+
     l_security_switch_data.setBit<PU_SECURITY_SWITCH_REGISTER_NX_RAND_NUM_GEN_LOCK>();
-    FAPI_TRY(fapi2::putScom(i_target, PU_SECURITY_SWITCH_REGISTER_SCOM, l_security_switch_data),
+
+    FAPI_TRY(fapi2::putScom(i_target,
+                            PU_SECURITY_SWITCH_REGISTER_SCOM,
+                            l_security_switch_data),
              "Error from putScom (Security Switch Register");
 
 fapi_try_exit: