diff options
author | Joe McGill <jmcgill@us.ibm.com> | 2017-06-11 10:57:45 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-06-20 10:46:37 -0400 |
commit | 266916597d9e01e0b2ee4e807afcdcae1cdda89a (patch) | |
tree | 9b02a79c45e01c1a86d8e6e4364753fdedc9d239 /src/import/chips/p9 | |
parent | 84f985f2a012f411f87e0186ca4979579b763a0f (diff) | |
download | talos-hostboot-266916597d9e01e0b2ee4e807afcdcae1cdda89a.tar.gz talos-hostboot-266916597d9e01e0b2ee4e807afcdcae1cdda89a.zip |
L3 updates -- p9_rng_init_phase1, p9_rng_init_phase2
whitespace, comment updates
add register FFDC collection
both errors indicate a non-functional RNG
Change-Id: Ic05d42cb6b2a2bfa0dbbe07066818775301545b9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41656
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: DHRUVARAJ SUBHASH CHANDRAN <dhruvaraj@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41657
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
5 files changed, 254 insertions, 157 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.C b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.C index 4eeb710a3..13351d955 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.C @@ -33,7 +33,7 @@ // *HWP HWP Owner: Chen Qian <qianqc@cn.ibm.com> // *HWP FW Owner: Thi Tran <thi@us.ibm.com> // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB // @@ -48,32 +48,31 @@ // Constant definitions //------------------------------------------------------------------------------ -// DD1 DEFINITIONS +// P9N DD1 DEFINITIONS // RNG Self Test Register 0 constants // repetition count match count threshold (3 repeated numbers) -const uint8_t NX_RNG_ST0_REPTEST_MATCH_TH_DD1 = 0x01; +const uint8_t NX_RNG_ST0_REPTEST_MATCH_TH_DD1 = 0x01; // adaptive proportion sample size (8b wide sample) -const uint8_t NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_DD1 = 0x02; +const uint8_t NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_DD1 = 0x02; // adaptive proportion window size (2K size) ###CHANGED -const uint8_t NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_DD1 = 0x02; +const uint8_t NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_DD1 = 0x02; // adaptive proportion RRN RNG0 match threshold (136; Assuming H = 6) -const uint16_t NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_DD1 = 0x88; +const uint16_t NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_DD1 = 0x88; // adaptive proportion RRN RNG1 match threshold (136; Assuming H = 6) -const uint16_t NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_DD1 = 0x88; +const uint16_t NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_DD1 = 0x88; // adaptive proportion CRN RNG0 match threshold (72; Assuming H = 8) -const uint16_t NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_DD1 = 0x48; +const uint16_t NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_DD1 = 0x48; // adaptive proportion CRN RNG1 match threshold (72; Assuming H = 8) -const uint16_t NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_DD1 = 0x48; +const uint16_t NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_DD1 = 0x48; // RNG Self Test Register 1 constants // adaptive proportion soft fail threshold (Setting [0:6] to 0x02) -const uint8_t NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_DD1 = 0x02; +const uint8_t NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_DD1 = 0x02; // adaptive proportion 1bit match threshold min (648; Assuming H = 0.8) const uint16_t NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_DD1 = 0x0288; // adaptive proportion 1bit match threshold max (1400; Assuming H = 0.8) const uint16_t NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_DD1 = 0x0578; - // RNG Self Test Register 3 constants // sample rate RRN enable (Use RRNs) const bool NX_RNG_ST3_SAMPTEST_RRN_ENABLE_DD1 = true; @@ -84,22 +83,22 @@ const uint16_t NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_DD1 = 0x4ccc; // sample rate match threshold maximum (64k * 0.55 = 36,044) const uint16_t NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_DD1 = 0xb332; -//DD2 DEFINITIONS +// non P9N DD1 DEFINITIONS // RNG Self Test Register 0 constants // repetition count match count threshold (3 repeated numbers) -const uint8_t NX_RNG_ST0_REPTEST_MATCH_TH_DD2 = 0x01; +const uint8_t NX_RNG_ST0_REPTEST_MATCH_TH_DD2 = 0x01; // adaptive proportion sample size (8b wide sample) -const uint8_t NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_DD2 = 0x02; +const uint8_t NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_DD2 = 0x02; // adaptive proportion window size (2K size) ###CHANGED -const uint8_t NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_DD2 = 0x01; +const uint8_t NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_DD2 = 0x01; // adaptive proportion RRN RNG0 match threshold (136; Assuming H = 6) -const uint16_t NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_DD2 = 0x22; +const uint16_t NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_DD2 = 0x22; // adaptive proportion RRN RNG1 match threshold (136; Assuming H = 6) -const uint16_t NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_DD2 = 0x22; +const uint16_t NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_DD2 = 0x22; // adaptive proportion CRN RNG0 match threshold (72; Assuming H = 8) -const uint16_t NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_DD2 = 0x12; +const uint16_t NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_DD2 = 0x12; // adaptive proportion CRN RNG1 match threshold (72; Assuming H = 8) -const uint16_t NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_DD2 = 0x12; +const uint16_t NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_DD2 = 0x12; // RNG Self Test Register 1 constants // adaptive proportion soft fail threshold (Setting [0:6] to 0x02) @@ -120,26 +119,27 @@ const uint16_t NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_DD2 = 0x7333; const uint16_t NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_DD2 = 0x8CCC; // RNG Read Delay Parameters Register -// Read Retry Ratio (0 = 31/32, 1 = 15/16, 2 = 29/32 ... 15 = 1/2 ... 31 = disabled) +// Read Retry Ratio (0 = 31/32, 1 = 15/16, 2 = 29/32 ... 15 = 1/2 ... +// 31 = disabled) const uint8_t NX_RNG_CQ_RDELAY_READ_RTY_RATIO_DD1 = 0x1F; const uint8_t NX_RNG_CQ_RDELAY_READ_RTY_RATIO_DD2 = 0x1F; // RNG Status And Control Register constants (Applies to both) -const bool NX_RNG_CFG_CONDITIONER_MASK_TOGGLE = false; +const bool NX_RNG_CFG_CONDITIONER_MASK_TOGGLE = false; // sample rate test enable -const bool NX_RNG_CFG_SAMPLE_RATE_TEST_ENABLE = true; +const bool NX_RNG_CFG_SAMPLE_RATE_TEST_ENABLE = true; // repetition count test enable -const bool NX_RNG_CFG_REPTEST_ENABLE = true; +const bool NX_RNG_CFG_REPTEST_ENABLE = true; // adaptive proportion 1bit test enable -const bool NX_RNG_CFG_ADAPTEST_1BIT_ENABLE = true; +const bool NX_RNG_CFG_ADAPTEST_1BIT_ENABLE = true; // adaptive proportion test enable -const bool NX_RNG_CFG_ADAPTEST_ENABLE = true; +const bool NX_RNG_CFG_ADAPTEST_ENABLE = true; // self test register 2 reset period (~59min/clear = 27) -const uint8_t NX_RNG_CFG_ST2_RESET_PERIOD = 0x1B; +const uint8_t NX_RNG_CFG_ST2_RESET_PERIOD = 0x1B; // pace rate (2000) -const uint16_t NX_RNG_CFG_PACE_RATE = 0x07d0; +const uint16_t NX_RNG_CFG_PACE_RATE = 0x07d0; // pace rate (300) for HW403701 -const uint16_t NX_RNG_CFG_PACE_RATE_HW403701 = 0x012c; +const uint16_t NX_RNG_CFG_PACE_RATE_HW403701 = 0x012c; //------------------------------------------------------------------------------ @@ -158,19 +158,29 @@ p9_rng_init_phase1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) fapi2::buffer<uint64_t> l_rng_st3_data; fapi2::buffer<uint64_t> l_rng_rdelay_data; - uint8_t l_dd1 = 0; + uint8_t l_rng_adaptest_dd1 = 0; uint8_t l_HW403701 = 0; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_RNG_ADAPTEST_SETTINGS, i_target, l_dd1) ); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW403701, i_target, l_HW403701) ); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_RNG_ADAPTEST_SETTINGS, + i_target, + l_rng_adaptest_dd1), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_RNG_ADAPTEST_SETTINGS"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW403701, + i_target, + l_HW403701), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW403701"); + + // 1. RNG will start running with FIFO write / self tests disabled (enable + // doesn't gate the osc; it turns off FIFO writes and self test fails); + // rng_enable = 0. - // 1. RNG will start running with FIFO write / self tests disabled (enable doesn't gate the osc; it turns off FIFO - // writes and self test fails); rng_enable = 0. // 2. RNG Conditioner Startup Test runs and reports status. - // Host boot reads Conditioner Startup Test Fail status. If a fail is detected then RNG is declared broken. + // Host boot reads Conditioner Startup Test Fail status. If a fail is + // detected then RNG is declared broken. - // read conditioner startup test fail status, exit if failure has been reported to - // declare RNG broken/unusable + // read conditioner startup test fail status, exit if failure has been + // reported to declare RNG broken/unusable FAPI_TRY(fapi2::getScom(i_target, PU_NX_RNG_CFG, l_rng_cfg_data), "Error from getScom (NX RNG Status and Control Register)"); @@ -180,9 +190,10 @@ p9_rng_init_phase1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) set_RNG_CFG(l_rng_cfg_data), "Conditioner startup test failed"); - // 3. Host boot programs window sizes, pace, self test enables and parameters, read delay parameters. - // program window sizes, pace, self test enables/parameters, and read delay parameters - // get values from self test registers + // 3. Host boot programs window sizes, pace, self test enables and + // parameters, read delay parameters. program window sizes, pace, self test + // enables/parameters, and read delay parameters get values from self test + // registers FAPI_TRY(fapi2::getScom(i_target, PU_NX_RNG_ST0, l_rng_st0_data), "Error from getScom (NX RNG Self Test Register 0)"); FAPI_TRY(fapi2::getScom(i_target, PU_NX_RNG_ST1, l_rng_st1_data), @@ -192,89 +203,115 @@ p9_rng_init_phase1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) FAPI_TRY(fapi2::getScom(i_target, PU_NX_RNG_RDELAY, l_rng_rdelay_data), "Error from putScom (NX RNG Read Delay Parameters Register)"); - if (l_dd1 != 0) + if (l_rng_adaptest_dd1) { - // DD1 - FAPI_INF("Configuring Self Test Registers for DD1"); + FAPI_INF("Configuring Self Test Registers for P9N DD1"); // configure RNG Self Test Register 0 - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_REPTEST_MATCH_TH, PU_NX_RNG_ST0_REPTEST_MATCH_TH_LEN> - (NX_RNG_ST0_REPTEST_MATCH_TH_DD1); - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE, PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_LEN> - (NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_DD1); - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE, PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_LEN> - (NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_DD1); - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH, PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_LEN> - (NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_DD1); - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH, PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_LEN> - (NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_DD1); - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH, PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_LEN> - (NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_DD1); - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH, PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_LEN> - (NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_DD1); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_REPTEST_MATCH_TH, + PU_NX_RNG_ST0_REPTEST_MATCH_TH_LEN> + (NX_RNG_ST0_REPTEST_MATCH_TH_DD1); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE, + PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_LEN> + (NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_DD1); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE, + PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_LEN> + (NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_DD1); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH, + PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_LEN> + (NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_DD1); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH, + PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_LEN> + (NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_DD1); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH, + PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_LEN> + (NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_DD1); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH, + PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_LEN> + (NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_DD1); // configure RNG Self Test Register 1 - l_rng_st1_data.insertFromRight<PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH, PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_LEN> - (NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_DD1); - l_rng_st1_data.insertFromRight<PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN, PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_LEN> - (NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_DD1); - l_rng_st1_data.insertFromRight<PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX, PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_LEN> - (NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_DD1); + l_rng_st1_data.insertFromRight<PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH, + PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_LEN> + (NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_DD1); + l_rng_st1_data.insertFromRight<PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN, + PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_LEN> + (NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_DD1); + l_rng_st1_data.insertFromRight<PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX, + PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_LEN> + (NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_DD1); // configure RNG Self Test Register 3 l_rng_st3_data.writeBit<PU_NX_RNG_ST3_SAMPTEST_RRN_ENABLE> (NX_RNG_ST3_SAMPTEST_RRN_ENABLE_DD1); - l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE, PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_LEN> - (NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_DD1); - l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN, PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_LEN> - (NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_DD1); - l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX, PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_LEN> - (NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_DD1); + l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE, + PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_LEN> + (NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_DD1); + l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN, + PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_LEN> + (NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_DD1); + l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX, + PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_LEN> + (NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_DD1); // configure RNG Read Delay Parameters Register - l_rng_rdelay_data.insertFromRight<PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO, PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO_LEN> - (NX_RNG_CQ_RDELAY_READ_RTY_RATIO_DD1); + l_rng_rdelay_data.insertFromRight<PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO, + PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO_LEN> + (NX_RNG_CQ_RDELAY_READ_RTY_RATIO_DD1); } else { - // DD2 - FAPI_INF("Configuring Self Test Registers for DD2"); + FAPI_INF("Configuring Self Test Registers (non P9N DD1)"); // configure RNG Self Test Register 0 - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_REPTEST_MATCH_TH, PU_NX_RNG_ST0_REPTEST_MATCH_TH_LEN> - (NX_RNG_ST0_REPTEST_MATCH_TH_DD2); - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE, PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_LEN> - (NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_DD2); - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE, PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_LEN> - (NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_DD2); - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH, PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_LEN> - (NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_DD2); - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH, PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_LEN> - (NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_DD2); - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH, PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_LEN> - (NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_DD2); - l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH, PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_LEN> - (NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_DD2); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_REPTEST_MATCH_TH, + PU_NX_RNG_ST0_REPTEST_MATCH_TH_LEN> + (NX_RNG_ST0_REPTEST_MATCH_TH_DD2); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE, + PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_LEN> + (NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_DD2); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE, + PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_LEN> + (NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_DD2); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH, + PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_LEN> + (NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_DD2); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH, + PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_LEN> + (NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_DD2); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH, + PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_LEN> + (NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_DD2); + l_rng_st0_data.insertFromRight<PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH, + PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_LEN> + (NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_DD2); // configure RNG Self Test Register 1 - l_rng_st1_data.insertFromRight<PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH, PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_LEN> - (NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_DD2); - l_rng_st1_data.insertFromRight<PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN, PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_LEN> - (NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_DD2); - l_rng_st1_data.insertFromRight<PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX, PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_LEN> - (NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_DD2); + l_rng_st1_data.insertFromRight<PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH, + PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_LEN> + (NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_DD2); + l_rng_st1_data.insertFromRight<PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN, + PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_LEN> + (NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_DD2); + l_rng_st1_data.insertFromRight<PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX, + PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_LEN> + (NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_DD2); // configure RNG Self Test Register 3 l_rng_st3_data.writeBit<PU_NX_RNG_ST3_SAMPTEST_RRN_ENABLE> (NX_RNG_ST3_SAMPTEST_RRN_ENABLE_DD2); - l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE, PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_LEN> - (NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_DD2); - l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN, PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_LEN> - (NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_DD2); - l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX, PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_LEN> - (NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_DD2); + l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE, + PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_LEN> + (NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_DD2); + l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN, + PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_LEN> + (NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_DD2); + l_rng_st3_data.insertFromRight<PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX, + PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_LEN> + (NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_DD2); // configure RNG Read Delay Parameters Register - l_rng_rdelay_data.insertFromRight<PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO, PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO_LEN> - (NX_RNG_CQ_RDELAY_READ_RTY_RATIO_DD2); + l_rng_rdelay_data.insertFromRight<PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO, + PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO_LEN> + (NX_RNG_CQ_RDELAY_READ_RTY_RATIO_DD2); } FAPI_TRY(fapi2::putScom(i_target, PU_NX_RNG_ST0, l_rng_st0_data), @@ -305,18 +342,21 @@ p9_rng_init_phase1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) (NX_RNG_CFG_ADAPTEST_1BIT_ENABLE); l_rng_cfg_data.writeBit<PU_NX_RNG_CFG_ADAPTEST_ENABLE> (NX_RNG_CFG_ADAPTEST_ENABLE); - l_rng_cfg_data.insertFromRight<PU_NX_RNG_CFG_ST2_RESET_PERIOD, PU_NX_RNG_CFG_ST2_RESET_PERIOD_LEN> - (NX_RNG_CFG_ST2_RESET_PERIOD); + l_rng_cfg_data.insertFromRight<PU_NX_RNG_CFG_ST2_RESET_PERIOD, + PU_NX_RNG_CFG_ST2_RESET_PERIOD_LEN> + (NX_RNG_CFG_ST2_RESET_PERIOD); - if(l_HW403701 != 0) + if (l_HW403701 != 0) { - l_rng_cfg_data.insertFromRight<PU_NX_RNG_CFG_PACE_RATE, PU_NX_RNG_CFG_PACE_RATE_LEN> - (NX_RNG_CFG_PACE_RATE_HW403701); + l_rng_cfg_data.insertFromRight<PU_NX_RNG_CFG_PACE_RATE, + PU_NX_RNG_CFG_PACE_RATE_LEN> + (NX_RNG_CFG_PACE_RATE_HW403701); } else { - l_rng_cfg_data.insertFromRight<PU_NX_RNG_CFG_PACE_RATE, PU_NX_RNG_CFG_PACE_RATE_LEN> - (NX_RNG_CFG_PACE_RATE); + l_rng_cfg_data.insertFromRight<PU_NX_RNG_CFG_PACE_RATE, + PU_NX_RNG_CFG_PACE_RATE_LEN> + (NX_RNG_CFG_PACE_RATE); } FAPI_TRY(fapi2::putScom(i_target, PU_NX_RNG_CFG, l_rng_cfg_data), diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.H b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.H index 3925d8c2d..356051cc6 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase1.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -49,14 +49,13 @@ // *HWP HWP Owner: Chen Qian <qianqc@cn.ibm.com> // *HWP FW Owner: Thi Tran <thi@us.ibm.com> // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB // #ifndef _P9_RNG_INIT_PHASE1_H_ #define _P9_RNG_INIT_PHASE1_H_ - //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ @@ -67,8 +66,8 @@ //------------------------------------------------------------------------------ /// function pointer typedef definition for HWP call support -typedef fapi2::ReturnCode (*p9_rng_init_phase1_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); - +typedef fapi2::ReturnCode (*p9_rng_init_phase1_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); //------------------------------------------------------------------------------ // Function prototypes @@ -84,7 +83,8 @@ extern "C" /// @param[in] i_target Reference to processor chip target /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. /// - fapi2::ReturnCode p9_rng_init_phase1(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + fapi2::ReturnCode p9_rng_init_phase1( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); } // extern "C" diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C index cbf075979..e265fc969 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C @@ -32,7 +32,7 @@ // *HWP HWP Owner: Chen Qian <qianqc@cn.ibm.com> // *HWP FW Owner: Thi Tran <thi@us.ibm.com> // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB // @@ -56,28 +56,31 @@ fapi2::ReturnCode p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { FAPI_INF("Start"); - fapi2::buffer<uint64_t> l_rng_cfg_data; fapi2::buffer<uint64_t> l_rng_bar_data; fapi2::buffer<uint64_t> l_rng_failed_int_data; fapi2::buffer<uint64_t> l_security_switch_data; - uint16_t l_rng_cfg_self_test_hard_fail_status = 0; - uint8_t l_nx_rng_bar_enable = 0; - uint64_t l_nx_rng_bar_addr = 0; - uint64_t l_nx_rng_bar_base_addr_offset = 0; - uint8_t l_nx_rng_failed_int_enable = 0; - uint64_t l_nx_rng_failed_int_addr = 0; - uint64_t l_base_addr_nm0; - uint64_t l_base_addr_nm1; - uint64_t l_base_addr_m; - uint64_t l_base_addr_mmio; - uint8_t l_HW403701; - - // 5. RNG is allowed to run for M cycles (M = enough time to complete init; recommend 1 second of time). - // NOTE: accomplished by delay in execution time between phase1/phase2 HWPs + uint16_t l_rng_cfg_self_test_hard_fail_status = 0; + uint8_t l_nx_rng_bar_enable = 0; + uint64_t l_nx_rng_bar_addr = 0; + uint64_t l_nx_rng_bar_base_addr_offset = 0; + uint8_t l_nx_rng_failed_int_enable = 0; + uint64_t l_nx_rng_failed_int_addr = 0; + uint64_t l_base_addr_nm0; + uint64_t l_base_addr_nm1; + uint64_t l_base_addr_m; + uint64_t l_base_addr_mmio; + uint8_t l_HW403701; + + // 5. RNG is allowed to run for M cycles (M = enough time to complete init; + // recommend 1 second of time). + // NOTE: accomplished by delay in execution time between phase1/phase2 HWPs + // get the self test hard fail status in RNG CFG register - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW403701, i_target, l_HW403701), + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW403701, + i_target, + l_HW403701), "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW403701)"); FAPI_TRY(fapi2::getScom(i_target, PU_NX_RNG_CFG, l_rng_cfg_data), @@ -85,11 +88,13 @@ p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) if (!l_HW403701) { - // 6. Host boot checks RNG fail bits again and if a fail is detected then RNG is declared broken + // 6. Host boot checks RNG fail bits again and if a fail is detected + // then RNG is declared broken FAPI_DBG("Checking RNG fail status..."); // exit if failure is reported in self test hard fail status field - l_rng_cfg_data.extractToRight<PU_NX_RNG_CFG_FAIL_REG, PU_NX_RNG_CFG_FAIL_REG_LEN>(l_rng_cfg_self_test_hard_fail_status); + l_rng_cfg_data.extractToRight<PU_NX_RNG_CFG_FAIL_REG, + PU_NX_RNG_CFG_FAIL_REG_LEN>(l_rng_cfg_self_test_hard_fail_status); FAPI_ASSERT(!l_rng_cfg_self_test_hard_fail_status, fapi2::P9_RNG_INIT_SELF_TEST_FAILED_ERR(). set_TARGET(i_target). @@ -110,8 +115,11 @@ p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) // if instructed to map the BAR: // - enable NX RNG MMIO BAR and get the bar address attributes // - optionally map NX RNG failed interrupt address - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_ENABLE, i_target, l_nx_rng_bar_enable), + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_ENABLE, + i_target, + l_nx_rng_bar_enable), "Error from FAPI_ATTR_GET (ATTR_PROC_NX_BAR_ENABLE)"); + FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target, EFF_FBC_GRP_CHIP_IDS, l_base_addr_nm0, @@ -121,9 +129,11 @@ p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) "Error from p9_fbc_utils_get_chip_base_address"); // get RNG BAR addr - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET, i_target.getParent<fapi2::TARGET_TYPE_SYSTEM>(), + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET, + i_target.getParent<fapi2::TARGET_TYPE_SYSTEM>(), l_nx_rng_bar_base_addr_offset), "Error from FAPI_ATTR_GET (ATTR_PROC_NX_BAR_BASE_ADDR_OFFSET)"); + // caculate the NX RNG BAR ADDR based on the bar adddr offset l_nx_rng_bar_addr = l_base_addr_mmio; l_nx_rng_bar_addr += l_nx_rng_bar_base_addr_offset; @@ -132,23 +142,32 @@ p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { // map NX RNG MMIO BAR l_rng_bar_data.setBit<PU_NX_MMIO_BAR_ENABLE>(); - l_rng_bar_data.insert<PU_NX_MMIO_BAR_BAR, PU_NX_MMIO_BAR_BAR_LEN, PU_NX_MMIO_BAR_BAR>(l_nx_rng_bar_addr); + l_rng_bar_data.insert<PU_NX_MMIO_BAR_BAR, + PU_NX_MMIO_BAR_BAR_LEN, PU_NX_MMIO_BAR_BAR>(l_nx_rng_bar_addr); FAPI_TRY(fapi2::putScom(i_target, PU_NX_MMIO_BAR, l_rng_bar_data), "Error from putScom (PU_NX_MMIO_BAR)"); // map NX RNG failed interrupt address - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_FAILED_INT_ENABLE, i_target, l_nx_rng_failed_int_enable), + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_FAILED_INT_ENABLE, + i_target, + l_nx_rng_failed_int_enable), "Error from FAPI_ATTR_GET (ATTR_PROC_NX_RNG_FAILED_INT_ENABLE)"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_FAILED_INT_ADDR, i_target, l_nx_rng_failed_int_addr), + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_FAILED_INT_ADDR, + i_target, + l_nx_rng_failed_int_addr), "Error from FAPI_ATTR_GET (ATTR_PROC_NX_RNG_FAILED_INT_ADDR)"); - if (l_nx_rng_failed_int_enable == fapi2::ENUM_ATTR_PROC_NX_RNG_FAILED_INT_ENABLE_ENABLE) + if (l_nx_rng_failed_int_enable == + fapi2::ENUM_ATTR_PROC_NX_RNG_FAILED_INT_ENABLE_ENABLE) { l_rng_failed_int_data.setBit<PU_RNG_FAILED_INT_ENABLE>(); - l_rng_failed_int_data.insert<PU_RNG_FAILED_INT_ADDRESS, PU_RNG_FAILED_INT_ADDRESS_LEN, PU_RNG_FAILED_INT_ADDRESS> - (l_nx_rng_failed_int_addr); + l_rng_failed_int_data.insert<PU_RNG_FAILED_INT_ADDRESS, + PU_RNG_FAILED_INT_ADDRESS_LEN, PU_RNG_FAILED_INT_ADDRESS> + (l_nx_rng_failed_int_addr); - FAPI_TRY(fapi2::putScom(i_target, PU_RNG_FAILED_INT, l_rng_failed_int_data), + FAPI_TRY(fapi2::putScom(i_target, + PU_RNG_FAILED_INT, + l_rng_failed_int_data), "Error from putScom (NX RNG Failed Interrupt Address Register"); } else @@ -166,15 +185,24 @@ p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) FAPI_TRY(fapi2::putScom(i_target, PU_NX_RNG_CFG, l_rng_cfg_data), "Error from putScom (NX RNG Status and Control Register)"); - // 8. Host boot sets the NX “sticky bit” that asserts tc_nx_block_rng_scom_wr. If tc_nx_block_rng_scom_wr = - // 1 writes to RNG SCOM register addresses 32 - 38 and 40 are blocked. An attempted write sets Power- - // Bus Interface FIR Data Register[Write to RNG SCOM reg detected when writes disabled]. - - // set NX sticky bit to block future RNG SCOM writes (tc_nx_block_rng_scom_wr) - FAPI_TRY(fapi2::getScom(i_target, PU_SECURITY_SWITCH_REGISTER_SCOM, l_security_switch_data), + // 8. Host boot sets the NX “sticky bit” that asserts + // tc_nx_block_rng_scom_wr. If tc_nx_block_rng_scom_wr = 1 writes to RNG + // SCOM register addresses 32 - 38 and 40 are blocked. An attempted + // write sets Power-Bus Interface FIR Data Register[Write to RNG SCOM + // reg detected when writes disabled]. + + // set NX sticky bit to block future RNG SCOM writes + // (tc_nx_block_rng_scom_wr) + FAPI_TRY(fapi2::getScom(i_target, + PU_SECURITY_SWITCH_REGISTER_SCOM, + l_security_switch_data), "Error from getScom (Security Switch Register"); + l_security_switch_data.setBit<PU_SECURITY_SWITCH_REGISTER_NX_RAND_NUM_GEN_LOCK>(); - FAPI_TRY(fapi2::putScom(i_target, PU_SECURITY_SWITCH_REGISTER_SCOM, l_security_switch_data), + + FAPI_TRY(fapi2::putScom(i_target, + PU_SECURITY_SWITCH_REGISTER_SCOM, + l_security_switch_data), "Error from putScom (Security Switch Register"); fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.H b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.H index 7768a52a3..c4e0df6ef 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -43,14 +43,13 @@ // *HWP HWP Owner: Chen Qian <qianqc@cn.ibm.com> // *HWP FW Owner: Thi Tran <thi@us.ibm.com> // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: HB // #ifndef _P9_RNG_INIT_PHASE2_H_ #define _P9_RNG_INIT_PHASE2_H_ - //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ @@ -61,8 +60,8 @@ //------------------------------------------------------------------------------ /// function pointer typedef definition for HWP call support -typedef fapi2::ReturnCode (*p9_rng_init_phase2_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); - +typedef fapi2::ReturnCode (*p9_rng_init_phase2_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); //------------------------------------------------------------------------------ // Function prototypes @@ -78,7 +77,8 @@ extern "C" /// @param[in] i_target Reference to processor chip target /// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. /// - fapi2::ReturnCode p9_rng_init_phase2(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + fapi2::ReturnCode p9_rng_init_phase2( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); } // extern "C" diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_rng_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_rng_init_errors.xml index bfd489426..763260426 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_rng_init_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_rng_init_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2017 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -24,14 +24,34 @@ <!-- IBM_PROLOG_END_TAG --> <hwpErrors> <!-- ******************************************************************** --> + <registerFfdc> + <id>REG_FFDC_RNG_SELF_TEST_FAIL</id> + <scomRegister>PU_NX_RNG_ST0</scomRegister> + <scomRegister>PU_NX_RNG_ST1</scomRegister> + <scomRegister>PU_NX_RNG_ST2</scomRegister> + <scomRegister>PU_NX_RNG_ST3</scomRegister> + <scomRegister>PU_NX_RNG_RDELAY</scomRegister> + <scomRegister>PU_NX_RNG_CFG</scomRegister> + </registerFfdc> + <!-- ******************************************************************** --> <hwpError> <rc>RC_P9_RNG_INIT_CONDITIONER_STARTUP_TEST_FAILED_ERR</rc> <description> Procedure: p9_rng_init_phase1 - NX RNG Read Conditioner startup test failed after POR + NX RNG Read Conditioner startup test failed after POR, + NX RNG is unusable </description> <ffdc>TARGET</ffdc> <ffdc>RNG_CFG</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_RNG_SELF_TEST_FAIL</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <target>TARGET</target> + </collectRegisterFfdc> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -39,10 +59,19 @@ <description> Procedure: p9_rng_init_phase2 NX RNG Self Test Hard Fail status is non-zero after programmed - initialization + initialization, NX RNG is unusable </description> <ffdc>TARGET</ffdc> <ffdc>SELF_TEST_HARD_FAIL_STATUS</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_RNG_SELF_TEST_FAIL</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <target>TARGET</target> + </collectRegisterFfdc> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> </hwpErrors> |