Add eff_config functionality needed for RIT, fix cas_latency bug & attr files

Change-Id: I508ea4b156ff26ff7c652e28510a535b90030434
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23796
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Hostboot CI
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23799
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 8 insertions, 1 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H
index fa1089a7b..ae06a6987 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.H
@@ -73,6 +73,10 @@ inline fapi2::ReturnCode set_CL_attr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>
 {
     // Declaration of the vector correctly initializes it to the right size
     // in the case the enum for PORTS_PER_MCS changes
+
+    // RIT hackey to match the attribute file (likely fakeSPD is wrong) BRS
+    i_cas_latency = 0x10;
+
     std::vector<uint8_t> l_cls_vect(PORTS_PER_MCS, uint8_t(i_cas_latency) );
 
     // set CAS latency attribute
@@ -96,9 +100,12 @@ fapi_try_exit:
 inline fapi2::ReturnCode set_freq_attrs(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
                                         uint64_t i_dimm_freq)
 {
-    uint64_t l_nest_freq = 1;
+    // TK - RIT, needsto be corrected
+    uint64_t l_nest_freq = 2;
     const auto l_mcbist = i_target.getParent<fapi2::TARGET_TYPE_MCBIST>();
 
+    FAPI_DBG("setting freq attrs for %s", mss::c_str(i_target));
+
     // TK
     //Update for P9, what do we do w/setting nest freq? - AAM
     // how do we select nest freq if we even have to??