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| author | Stephen Glancy <sglancy@us.ibm.com> | 2017-11-17 16:11:51 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-11-27 18:32:14 -0500 |
| commit | 62321660514419ab1413a7bbe61ce19bae442875 (patch) | |
| tree | 17a369bb14a4f2c456397390601b1ed37c757c09 /src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C | |
| parent | 4471b2a5baa51731665f8f0d8b248c3404d44041 (diff) | |
| download | talos-hostboot-62321660514419ab1413a7bbe61ce19bae442875.tar.gz talos-hostboot-62321660514419ab1413a7bbe61ce19bae442875.zip | |
Worksaround AWAN simulation failure
The DIMM behavioral model does not properly invert b-side
inputs in the AWAN simulations. This patch sets removes
initial pattern if simulation is enabled.
Change-Id: Ie00f3fc91ae5a6e17514d378e1d4494ad5c1714b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49879
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49908
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C index 0a33fe947..4c46b2590 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C @@ -106,7 +106,7 @@ extern "C" l_cal_steps_enabled.setBit<mss::INITIAL_PAT_WR>().setBit<mss::TRAINING_ADV>(); // Gets the training steps to calibrate - l_steps = mss::training::steps_factory(l_cal_steps_enabled); + l_steps = mss::training::steps_factory(l_cal_steps_enabled, l_sim); // Keep track of the last error seen by a rank pair fapi2::ReturnCode l_rank_pair_error(fapi2::FAPI2_RC_SUCCESS); |
