diff options
author | Stephen Glancy <sglancy@us.ibm.com> | 2017-11-17 16:11:51 -0600 |
---|---|---|
committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-11-27 18:32:14 -0500 |
commit | 62321660514419ab1413a7bbe61ce19bae442875 (patch) | |
tree | 17a369bb14a4f2c456397390601b1ed37c757c09 /src/import/chips/p9 | |
parent | 4471b2a5baa51731665f8f0d8b248c3404d44041 (diff) | |
download | talos-hostboot-62321660514419ab1413a7bbe61ce19bae442875.tar.gz talos-hostboot-62321660514419ab1413a7bbe61ce19bae442875.zip |
Worksaround AWAN simulation failure
The DIMM behavioral model does not properly invert b-side
inputs in the AWAN simulations. This patch sets removes
initial pattern if simulation is enabled.
Change-Id: Ie00f3fc91ae5a6e17514d378e1d4494ad5c1714b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49879
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49908
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
4 files changed, 15 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C index 9c7060c26..c7438b096 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C @@ -655,9 +655,10 @@ uint64_t custom_read_ctr::calculate_cycles( const fapi2::Target<fapi2::TARGET_TY /// /// @brief Creates the vector of training steps to loop over /// @param[in] i_cal_steps - the bit mask of calibration steps +/// @param[in] i_sim - simulation mode or not /// @return a vector of the calibration steps to run /// -std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& i_cal_steps) +std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& i_cal_steps, const bool i_sim) { std::vector<std::shared_ptr<step>> l_steps; @@ -669,11 +670,17 @@ std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& } // INITIAL_PAT_WR - if(i_cal_steps.getBit<mss::cal_steps::INITIAL_PAT_WR>()) + // Note: simulation contains a bug where the DDR4 model does not match the DDR4 hardware + // As such, if the simulation IPW bug is set, do not create a step for initial pattern write + if(!i_sim && i_cal_steps.getBit<mss::cal_steps::INITIAL_PAT_WR>()) { FAPI_INF("Initial pattern write is enabled"); l_steps.push_back(std::make_shared<initial_pattern_write>()); } + else if(i_sim) + { + FAPI_INF("Initial pattern write was requested, but the simulation for it is bugged! Skipping IPW"); + } // DQS_ALIGN if(i_cal_steps.getBit<mss::cal_steps::DQS_ALIGN>()) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H index 24ebc0e71..37f756098 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H @@ -690,9 +690,10 @@ class custom_read_ctr : public phy_step /// /// @brief Creates the vector of training steps to loop over /// @param[in] i_cal_steps - the bit mask of calibration steps +/// @param[in] i_sim - simulation mode or not /// @return a vector of the calibration steps to run /// -std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& i_cal_steps); +std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& i_cal_steps, const bool i_sim); } // ns training diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index c354bc86b..d16f2c1ee 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -82,6 +82,8 @@ extern "C" uint8_t l_reset_disable = 0; uint8_t l_cal_abort_on_error = i_abort_on_error; + uint8_t l_sim = 0; + FAPI_TRY( mss::is_simulation (l_sim) ); FAPI_TRY( mss::mrw_reset_delay_before_cal(l_reset_disable), "%s Error in p9_mss_draminit_training", mss::c_str(i_target) ); // Flag to abort on error @@ -179,7 +181,7 @@ extern "C" bool l_cal_fail = false; FAPI_INF("Execute cal on rp %d %s", rp, mss::c_str(p)); - for(const auto& l_step : mss::training::steps_factory(l_cal_steps_enabled)) + for(const auto& l_step : mss::training::steps_factory(l_cal_steps_enabled, l_sim)) { FAPI_TRY( l_step->execute( p, rp, l_cal_abort_on_error) ); } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C index 0a33fe947..4c46b2590 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C @@ -106,7 +106,7 @@ extern "C" l_cal_steps_enabled.setBit<mss::INITIAL_PAT_WR>().setBit<mss::TRAINING_ADV>(); // Gets the training steps to calibrate - l_steps = mss::training::steps_factory(l_cal_steps_enabled); + l_steps = mss::training::steps_factory(l_cal_steps_enabled, l_sim); // Keep track of the last error seen by a rank pair fapi2::ReturnCode l_rank_pair_error(fapi2::FAPI2_RC_SUCCESS); |