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author | Jacob Harvey <jlharvey@us.ibm.com> | 2016-08-03 15:49:44 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-08-30 21:55:45 -0400 |
commit | 54bc88b4d29d0d0d288aaccf79b8d4220848187b (patch) | |
tree | 605d5c61bc22e00bb6df7da1e3d05d56caf1b24a /src/import/chips/p9/procedures/hwp/memory/lib/spd | |
parent | e436c6b446ac80fdf050539edc746e0082219b86 (diff) | |
download | talos-hostboot-54bc88b4d29d0d0d288aaccf79b8d4220848187b.tar.gz talos-hostboot-54bc88b4d29d0d0d288aaccf79b8d4220848187b.zip |
Fix eff_config, remove custom_dimm
Change-Id: Icc9bf700cbdf41467c4b0733f878d98b5dd76fed
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27930
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28184
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/spd')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.C | 25 |
1 files changed, 15 insertions, 10 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.C index 0af1e912c..9ce5f2e63 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.C @@ -2279,10 +2279,11 @@ fapi2::ReturnCode decoder::min_write_recovery_time(const fapi2::Target<TARGET_TY { // For General Section rev 1.0 of the SPD, // SPD Byte 41 (bits 3~0) & Byte 42 (bits 7~0) were reserved - // and coded as zeros. There was no concept of - // min write recovery time so this - // is thus hard-wired to zero. - o_value = 0x00; + // and coded as zeros. + // Default as 0x78 for all DDR4 bins for rev 1.0 + // No value given in 1.0 JEDEC spec and no value in SPD - JLH + // 1.1 Has valid values defined and in SPD, this is taken from there + o_value = 0x78; return fapi2::FAPI2_RC_SUCCESS; } @@ -2302,9 +2303,11 @@ fapi2::ReturnCode decoder::min_twtr_s(const fapi2::Target<TARGET_TYPE_DIMM>& i_t { // For General Section rev 1.0 of the SPD, // SPD Byte 43 (bits 3~0) & Byte 44 (bits 7~0) were reserved - // and coded as zeros. There was no concept of twtr_s so this - // is thus hard-wired to zero. - o_value = 0x00; + // and coded as zeros. + // Default as 0x14 for all DDR4 bins for rev 1.0 + // No value given in 1.0 JEDEC spec and no value in SPD - JLH + // 1.1 Has valid values defined and in SPD, this is taken from there + o_value = 0x14; return fapi2::FAPI2_RC_SUCCESS; } @@ -2323,9 +2326,11 @@ fapi2::ReturnCode decoder::min_twtr_l(const fapi2::Target<TARGET_TYPE_DIMM>& i_t { // For General Section rev 1.0 of the SPD, // SPD Byte 43 (bits 7~4) & Byte 45 (bits 7~0) were reserved - // and coded as zeros. There was no concept of twtr_l so this - // is thus hard-wired to zero. - o_value = 0x00; + // and coded as zeros. + // Default as 0x3C for all DDR4 bins for rev 1.0 + // No value given in 1.0 JEDEC spec and no value in SPD - JLH + // 1.1 Has valid values defined and in SPD, this is taken from there + o_value = 0x3C; return fapi2::FAPI2_RC_SUCCESS; } |