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| author | Andre Marin <aamarin@us.ibm.com> | 2017-08-30 10:42:08 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-09-25 22:16:03 -0400 |
| commit | 7085e6bb6afc0c22ac6b0bb5f2e67b59d1d0f993 (patch) | |
| tree | 2a1d0a417eaa76579f20123c213810b57829705e /src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | |
| parent | 84e9979022484372224d5b1a4ed44d7d2989bfe3 (diff) | |
| download | talos-hostboot-7085e6bb6afc0c22ac6b0bb5f2e67b59d1d0f993.tar.gz talos-hostboot-7085e6bb6afc0c22ac6b0bb5f2e67b59d1d0f993.zip | |
Add Write CRC attributes to xml and eff_dimm
Added ATTR_EFF_PACKAGE_RANK_MAP, ATTR_EFF_NIBBLE_MAP, and
ATTR_MSS_EFF_WR_CRC attributes.
Change-Id: Ib665e22ce755282afb012ca0df9c670770fa1dd6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45386
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Dev-Ready: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45406
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index 454892813..ba099f268 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -65,7 +65,7 @@ enum sizes MAX_NUM_IMP = 4, ///< number of impedances valid per slew type MAX_NUM_CAL_SLEW_RATES = 4, ///< 3V/ns, 4V/ns, 5V/ns, 6V/n MAX_DQ_BITS = 72, /// TODO RTC:157753 This is Nimbus specific. Should be attribute/trait of processor. - MAX_DQ_NIBBLES_X4 = MAX_DQ_BITS / BITS_PER_NIBBLE, ///< For x4's there are 18 DQ nibbles for DQ 72 bits + MAX_DQ_NIBBLES = MAX_DQ_BITS / BITS_PER_NIBBLE, ///< For ISDIMMs are 18 DQ nibbles for DQ 72 bits MAX_DRAMS_X8 = MAX_DQ_BITS / BITS_PER_NIBBLE, ///< For x8's there are 9 DRAM for 72 bits MAX_DRAMS_X4 = MAX_DQ_BITS / BITS_PER_BYTE, ///< For x4's there are 18 DRAM for 72 bits @@ -134,6 +134,10 @@ enum times /// enum ffdc_function_codes { + // Used in eff_dimm.C + NIBBLE_MAP_FUNC = 20, + PACKAGE_RANK_MAP_FUNC = 21, + // Used in fw_mark_store.H for MSS_INVALID_RANK_PASSED FWMS_READ = 30, FWMS_WRITE = 31, |
