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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-03-27 15:44:17 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-04-17 11:50:19 -0400 |
| commit | 05f0ee2abdaf68858e506ce800ea98084f9c80d9 (patch) | |
| tree | adb4b5e89ace2424f097f2987167b2c2bb0e74e5 /src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H | |
| parent | d76f1bc4576fbe04a51c5ba45f52b01e0cea6006 (diff) | |
| download | talos-hostboot-05f0ee2abdaf68858e506ce800ea98084f9c80d9.tar.gz talos-hostboot-05f0ee2abdaf68858e506ce800ea98084f9c80d9.zip | |
Fix up setup_cal and vref attrs
Fix bug when setting RD_VREF but not RD_CNTR
Change name of MSS_VREF_CAL_STEP_ENABLE to
MSS_RDVREF_CAL_STEP_ENABLE
Set RD_VREF_CALENABLE_REG in setup_cal
Change-Id: Ie4117a53c2ae2e53e7b753cc2b0b127cab0d4caf
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38484
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38488
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H index d2ed09cd4..310eab57d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H @@ -204,7 +204,7 @@ inline fapi2::ReturnCode cal_timer_setup(const fapi2::Target<T>& i_target, FAPI_TRY( mss::write_ctr_cycles(i_target, l_write_cntr_cycles) ); FAPI_TRY( mss::cal_abort_on_error(cal_abort_on_error) ); - FAPI_TRY( mss::vref_cal_enable(i_target, l_vref_cal_enable) ); + FAPI_TRY( mss::rdvref_cal_enable(i_target, l_vref_cal_enable) ); // First, calculate the total number of cycles this cal should take if everything // runs to completion @@ -216,7 +216,7 @@ inline fapi2::ReturnCode cal_timer_setup(const fapi2::Target<T>& i_target, l_total_cycles += i_cal_steps_enabled.getBit<COARSE_WR>() ? coarse_wr_cycles(i_target) : 0; l_total_cycles += i_cal_steps_enabled.getBit<COARSE_RD>() ? coarse_rd_cycles(i_target) : 0; l_total_cycles += - ((l_vref_cal_enable != 0) && i_cal_steps_enabled.getBit<READ_CTR>()) ? rc::vref_guess_time(i_target) : 0; + ((l_vref_cal_enable != 0) && i_cal_steps_enabled.getBit<READ_CTR_2D_VREF>()) ? rc::vref_guess_time(i_target) : 0; // Now we have to decide if we're going to abort on an error or keep going. If we keep going, // then we want our initial delay to be the expected time to completion - we don't have much |
