Fix up setup_cal and vref attrs

    Fix bug when setting RD_VREF but not RD_CNTR
    Change name of MSS_VREF_CAL_STEP_ENABLE to
    MSS_RDVREF_CAL_STEP_ENABLE
    Set RD_VREF_CALENABLE_REG in setup_cal

Change-Id: Ie4117a53c2ae2e53e7b753cc2b0b127cab0d4caf
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38484
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38488
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

12 files changed, 155 insertions, 33 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
index 53152f649..75d23704d 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C
@@ -4594,10 +4594,10 @@ fapi2::ReturnCode eff_dimm::cal_step_enable()
 }
 
 ///
-/// @brief Determines and sets the vref_enable_bit settings
+/// @brief Determines and sets the rdvref_enable_bit settings
 /// @return fapi2::FAPI2_RC_SUCCESS if okay
 ///
-fapi2::ReturnCode eff_dimm::vref_enable_bit()
+fapi2::ReturnCode eff_dimm::rdvref_enable_bit()
 {
     // Gets the MCS target to use
     const auto& l_mcs = mss::find_target<TARGET_TYPE_MCS>(iv_dimm);
@@ -4614,7 +4614,7 @@ fapi2::ReturnCode eff_dimm::vref_enable_bit()
     std::vector<uint16_t> l_vref_enable(PORTS_PER_MCS, l_vref_enable_value);
 
     // Sets the values
-    return FAPI_ATTR_SET(fapi2::ATTR_MSS_VREF_CAL_ENABLE, l_mcs, UINT16_VECTOR_TO_1D_ARRAY(l_vref_enable, PORTS_PER_MCS));
+    return FAPI_ATTR_SET(fapi2::ATTR_MSS_RDVREF_CAL_ENABLE, l_mcs, UINT16_VECTOR_TO_1D_ARRAY(l_vref_enable, PORTS_PER_MCS));
 }
 
 }//mss
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
index 010e10b59..2ed3602d1 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H
@@ -708,10 +708,10 @@ class eff_dimm
         fapi2::ReturnCode cal_step_enable();
 
         ///
-        /// @brief Determines and sets the vref_enable_bit settings
+        /// @brief Determines and sets the rdvref_enable_bit settings
         /// @return fapi2::FAPI2_RC_SUCCESS if okay
         ///
-        fapi2::ReturnCode vref_enable_bit();
+        fapi2::ReturnCode rdvref_enable_bit();
 
         ///
         /// @brief Sets the RTT_NOM value from SPD
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index 101bceaf3..4a04556a9 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -9433,6 +9433,88 @@ fapi_try_exit:
 }
 
 ///
+/// @brief ATTR_MSS_RDVREF_CAL_ENABLE getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] ref to the value uint16_t
+/// @note Generated by gen_accessors.pl generateParameters (D)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  A bit vector denoting bits in every DP16 on the port to be calibrated. That is,
+/// all of the set bits will be calibrated for all DP16. A value of zero indicates
+/// the calibration should not be
+/// run.
+///
+inline fapi2::ReturnCode rdvref_cal_enable(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint16_t& o_value)
+{
+    uint16_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_RDVREF_CAL_ENABLE, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(i_target)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_RDVREF_CAL_ENABLE: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_RDVREF_CAL_ENABLE getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[out] ref to the value uint16_t
+/// @note Generated by gen_accessors.pl generateParameters (D.1)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  A bit vector denoting bits in every DP16 on the port to be calibrated. That is,
+/// all of the set bits will be calibrated for all DP16. A value of zero indicates
+/// the calibration should not be
+/// run.
+///
+inline fapi2::ReturnCode rdvref_cal_enable(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint16_t& o_value)
+{
+    uint16_t l_value[2];
+    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_RDVREF_CAL_ENABLE, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(l_mca)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_RDVREF_CAL_ENABLE: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_RDVREF_CAL_ENABLE getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[out] uint16_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (E)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  A bit vector denoting bits in every DP16 on the port to be calibrated. That is,
+/// all of the set bits will be calibrated for all DP16. A value of zero indicates
+/// the calibration should not be
+/// run.
+///
+inline fapi2::ReturnCode rdvref_cal_enable(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint16_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint16_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_RDVREF_CAL_ENABLE, i_target, l_value) );
+    memcpy(o_array, &l_value, 4);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_RDVREF_CAL_ENABLE: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
 /// @brief ATTR_MSS_CAL_ABORT_ON_ERROR getter
 /// @param[out] uint8_t& reference to store the value
 /// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H
index d2ed09cd4..310eab57d 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/cal_timers.H
@@ -204,7 +204,7 @@ inline fapi2::ReturnCode cal_timer_setup(const fapi2::Target<T>& i_target,
 
     FAPI_TRY( mss::write_ctr_cycles(i_target, l_write_cntr_cycles) );
     FAPI_TRY( mss::cal_abort_on_error(cal_abort_on_error) );
-    FAPI_TRY( mss::vref_cal_enable(i_target, l_vref_cal_enable) );
+    FAPI_TRY( mss::rdvref_cal_enable(i_target, l_vref_cal_enable) );
 
     // First, calculate the total number of cycles this cal should take if everything
     // runs to completion
@@ -216,7 +216,7 @@ inline fapi2::ReturnCode cal_timer_setup(const fapi2::Target<T>& i_target,
     l_total_cycles += i_cal_steps_enabled.getBit<COARSE_WR>()   ? coarse_wr_cycles(i_target)   : 0;
     l_total_cycles += i_cal_steps_enabled.getBit<COARSE_RD>()   ? coarse_rd_cycles(i_target)   : 0;
     l_total_cycles +=
-        ((l_vref_cal_enable != 0) && i_cal_steps_enabled.getBit<READ_CTR>()) ? rc::vref_guess_time(i_target) : 0;
+        ((l_vref_cal_enable != 0) && i_cal_steps_enabled.getBit<READ_CTR_2D_VREF>()) ? rc::vref_guess_time(i_target) : 0;
 
     // Now we have to decide if we're going to abort on an error or keep going. If we keep going,
     // then we want our initial delay to be the expected time to completion - we don't have much
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index 4c20c1b33..6f9bc77c0 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -800,24 +800,16 @@ fapi2::ReturnCode setup_cal_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
     fapi2::buffer<uint64_t> l_cal_config;
     uint8_t l_sim = 0;
     uint8_t cal_abort_on_error = 0;
-    uint16_t l_vref_cal_enable = 0;
+
 
     FAPI_TRY( mss::cal_abort_on_error(cal_abort_on_error) );
     FAPI_TRY( mss::is_simulation(l_sim) );
-    FAPI_TRY( mss::vref_cal_enable(i_target, l_vref_cal_enable) );
 
     // This is the buffer which will be written to CAL_CONFIG0. It starts
     // life assuming no cal sequences, no rank pairs - but we set the abort-on-error
     // bit ahead of time.
     l_cal_config.writeBit<MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ABORT_ON_ERROR>(cal_abort_on_error);
 
-    // Check the write centering bits - if write centering is defined, don't run 2D. Vice versa.
-    if (i_cal_steps_enabled.getBit<WRITE_CTR>() && i_cal_steps_enabled.getBit<WRITE_CTR_2D_VREF>())
-    {
-        FAPI_INF("Both 1D and 2D write centering were defined - only performing 2D");
-        i_cal_steps_enabled.clearBit<WRITE_CTR>();
-    }
-
     // Sadly, the bits in the register don't align directly with the bits in the attribute.
     // So, arrange the bits accordingly and write the config register.
     {
@@ -846,9 +838,17 @@ fapi2::ReturnCode setup_cal_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
     }
 
     // Blast the VREF config with the proper setting for these cal bits if there were any enable bits set
-    if (l_vref_cal_enable != 0)
+    // TK let's remove the EC check sometime in the future. Added here to double check lab team on attribute overrides
+    if (i_cal_steps_enabled.getBit<READ_CTR_2D_VREF>() && (!mss::chip_ec_feature_skip_hw_vref_cal(i_target)))
     {
+        uint16_t l_vref_cal_enable = 0;
+
         fapi2::buffer<uint64_t> l_data;
+        typedef rcTraits<fapi2::TARGET_TYPE_MCA> TT;
+
+        // Blast the VREF_CAL_ENABLE to the registers that control which dp16's to use for rdvref
+        FAPI_TRY( mss::rdvref_cal_enable(i_target, l_vref_cal_enable) );
+        FAPI_TRY( mss::scom_blastah(i_target, dp16Traits<TARGET_TYPE_MCA>::RD_VREF_CAL_ENABLE_REG, l_vref_cal_enable) );
 
         // The two bits we care about are the calibration enable and skip read centering
         // bits in rc_vref_config1. We always run RDVREF config, but sometimes skip
@@ -856,33 +856,33 @@ fapi2::ReturnCode setup_cal_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
         FAPI_TRY( mss::rc::read_vref_config1(i_target, l_data) );
 
         FAPI_INF("enabling read VREF cal, read centering is %s", i_cal_steps_enabled.getBit<READ_CTR>() ? "yup" : "nope");
-        l_data.setBit<MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CALIBRATION_ENABLE>();
 
-        if ((i_cal_steps_enabled.getBit<READ_CTR>() == mss::LOW) &&
-            (i_cal_steps_enabled.getBit<READ_CTR_2D_VREF>() == mss::LOW))
-        {
+        l_data.setBit<TT::RDVREF_CALIBRATION_ENABLE>();
 
+        // Check to see if READ_CENTERING is disabled, if so, set the bit
+        if (!i_cal_steps_enabled.getBit<READ_CTR>())
+        {
             FAPI_INF("skipping read centering");
-            l_data.clearBit<MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_SKIP_RDCENTERING>();
+            l_data.setBit<TT::SKIP_RDCENTERING>();
         }
 
         FAPI_TRY( mss::rc::write_vref_config1(i_target, l_data) );
     }
 
-    // Configures WR VREF config register to run 1D (write centering only) or 2D (write centering + VREF) calibration
     {
-        std::vector<fapi2::buffer<uint64_t>> l_vref_config;
-        FAPI_TRY( mss::scom_suckah(i_target, mss::dp16Traits<fapi2::TARGET_TYPE_MCA>::WR_VREF_CONFIG0_REG, l_vref_config) );
+        typedef mss::dp16Traits<fapi2::TARGET_TYPE_MCA> TT;
+        std::vector<fapi2::buffer<uint64_t>> l_wr_vref_config;
+        FAPI_TRY( mss::scom_suckah(i_target, TT::WR_VREF_CONFIG0_REG, l_wr_vref_config) );
 
         // Loops and sets or clears the 2D VREF bit on all DPs
-        // Note: 2D VREF needs to be a 0 in the reg if it is to be enabled, hence the not in the write bit function
-        for(auto& l_data : l_vref_config)
+        for(auto& l_data : l_wr_vref_config)
         {
-            l_data.writeBit<MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_1D_CHICKEN_SWITCH>
-            (!i_cal_steps_enabled.getBit<WRITE_CTR_2D_VREF>());
+            // 0: Run only the VREF (2D) write centering algorithm
+            // 1: Run only the 1D
+            l_data.writeBit<TT::WR_VREF_CONFIG0_1D_ONLY_SWITCH>(!i_cal_steps_enabled.getBit<WRITE_CTR_2D_VREF>());
         }
 
-        FAPI_TRY(mss::scom_blastah(i_target,  mss::dp16Traits<fapi2::TARGET_TYPE_MCA>::WR_VREF_CONFIG0_REG, l_vref_config));
+        FAPI_TRY(mss::scom_blastah(i_target, TT::WR_VREF_CONFIG0_REG, l_wr_vref_config));
     }
 
     // loops through all RP's running workarounds and latching the VREF's as need be
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
index 6897a478e..3838ad843 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
@@ -1504,7 +1504,7 @@ fapi2::ReturnCode reset_rd_vref( const fapi2::Target<TARGET_TYPE_MCA>& i_target
         // Turn on the rd vref calibration. We leverage an attribute to control this.
         {
             uint16_t l_vref_cal_enable = 0;
-            FAPI_TRY( mss::vref_cal_enable(i_target, l_vref_cal_enable) );
+            FAPI_TRY( mss::rdvref_cal_enable(i_target, l_vref_cal_enable) );
             FAPI_TRY( mss::scom_blastah(i_target, TT::RD_VREF_CAL_ENABLE_REG, l_vref_cal_enable) );
         }
     }
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
index 1b70a1b0e..09fd26965 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H
@@ -120,7 +120,7 @@ class rcTraits<fapi2::TARGET_TYPE_MCA>
             CMD_PRECEDE_TIME_LEN = MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CMD_PRECEDE_TIME_LEN,
             MPR_PAGE = MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_MPR_PAGE,
             MPR_PAGE_LEN = MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_MPR_PAGE_LEN,
-            CALIBRATION_ENABLE = MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CALIBRATION_ENABLE,
+            RDVREF_CALIBRATION_ENABLE = MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CALIBRATION_ENABLE,
             SKIP_RDCENTERING = MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_SKIP_RDCENTERING,
         };
 
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
index ae4e90374..cfb4d0f59 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
@@ -197,7 +197,7 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>
 
         // Sets up the calibration steps
         FAPI_TRY( l_eff_dimm->cal_step_enable() );
-        FAPI_TRY( l_eff_dimm->vref_enable_bit() );
+        FAPI_TRY( l_eff_dimm->rdvref_enable_bit() );
 
         //Let's do some checking
         FAPI_TRY( mss::check::temp_refresh_mode());
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
index 4d5a3a80d..7c3546e4e 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
@@ -1967,6 +1967,21 @@
     </attribute>
 
     <attribute>
+        <id>ATTR_MSS_RDVREF_CAL_ENABLE</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            A bit vector denoting bits in every DP16 on the port to be calibrated.
+            That is, all of the set bits will be calibrated for all DP16. A value
+            of zero indicates the calibration should not be run.
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint16</valueType>
+        <writeable/>
+        <array>2</array>
+        <mssAccessorName>rdvref_cal_enable</mssAccessorName>
+    </attribute>
+
+    <attribute>
         <id>ATTR_MSS_CAL_ABORT_ON_ERROR</id>
         <targetType>TARGET_TYPE_SYSTEM</targetType>
         <description>
diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
index e4354a87d..7a81d8be3 100644
--- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
+++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
@@ -61,6 +61,9 @@
           <default>32</default>
      </attribute>
      <attribute>
+          <id>ATTR_MSS_RDVREF_CAL_ENABLE</id>
+     </attribute>
+     <attribute>
           <id>ATTR_MSS_MRW_REFRESH_RATE_REQUEST</id>
           <default>0</default>
      </attribute>
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 4a7995c2c..e15387c73 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -32917,6 +32917,27 @@ Measured in GB</description>
 </attribute>
 
 <attribute>
+    <id>MSS_RDVREF_CAL_ENABLE</id>
+    <description>
+        A bit vector denoting bits in every DP16 on the port to be calibrated.
+            That is, all of the set bits will be calibrated for all DP16. A value
+            of zero indicates the calibration should not be run.
+    </description>
+    <simpleType>
+        <uint16_t>
+        </uint16_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_RDVREF_CAL_ENABLE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
     <id>MSS_VREF_DAC_NIBBLE</id>
     <description>
         Value for VREF DAC nibbles
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index d0a0e529d..06f606140 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1881,6 +1881,7 @@
     <attribute><id>EFF_DRAM_RTT_WR</id></attribute>
     <attribute><id>EFF_DRAM_RTT_PARK</id></attribute>
     <attribute><id>EFF_RANK_GROUP_OVERRIDE</id></attribute>
+    <attribute><id>MSS_RDVREF_CAL_ENABLE</id></attribute>
     <attribute><id>MSS_VREF_DAC_NIBBLE</id></attribute>
     <attribute><id>MSS_MVPD_FWMS</id></attribute>
 </targetType>