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| author | Ben Gass <bgass@us.ibm.com> | 2016-05-18 13:01:57 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-03-03 16:02:45 -0500 |
| commit | e0af4445f2a352a8353ae9e29dd5aef43b3fda27 (patch) | |
| tree | 300db1b0996a7e5882b1b5e5e798a0b9247b9fbe /src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C | |
| parent | 877f139a1b5bf76169969c44c8591892d08d6c47 (diff) | |
| download | talos-hostboot-e0af4445f2a352a8353ae9e29dd5aef43b3fda27.tar.gz talos-hostboot-e0af4445f2a352a8353ae9e29dd5aef43b3fda27.zip | |
Translate logical mca regisers in mcs chiplet as mca target type
Fixup memory code which uses the xlt registers
Add dependent epsilon inits
Change-Id: Ib7947502af6c25836310a793a1d9eb93d6ebdf39
Original-Change-Id: I995bcd895a0a7a431dcf350475fd387be70749c9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24733
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server
Tested-by: PPE CI
Tested-by: Hostboot CI
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Dev-Ready: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37394
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C | 14 |
1 files changed, 3 insertions, 11 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C index 296bfddf4..fa6807709 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -76,14 +76,6 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE FAPI_INF("Setting up xlate registers for MCA%d (%d)", mss::pos(i_target), mss::index(i_target)); - // The addressing for the xlt registers is funky. We have a different unit0 address for units 0/2 - // than we do for 1/3. - const uint64_t& l_t0_address = mss::pos(i_target) % 2 ? MCS_0_PORT13_MCP0XLT0 : MCS_0_PORT02_MCP0XLT0; - const uint64_t& l_t1_address = mss::pos(i_target) % 2 ? MCS_0_PORT13_MCP0XLT1 : MCS_0_PORT02_MCP0XLT1; - const uint64_t& l_t2_address = mss::pos(i_target) % 2 ? MCS_0_PORT13_MCP0XLT2 : MCS_0_PORT02_MCP0XLT2; - - FAPI_DBG("xlate scoms registers 0x%016lx, 0x%016lx, 0x%016lx", l_t0_address, l_t1_address, l_t2_address); - // We enable the DIMM select bit for slot1 if we have two DIMM installed l_xlate.writeBit<MCS_PORT13_MCP0XLT0_SLOT1_D_VALUE>(l_dimms.size() == 2); @@ -219,9 +211,9 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE FAPI_DBG("HACK: Cramming 0x%016lx in for MCP0XLT1", l_xlate1); FAPI_DBG("HACK: Cramming 0x%016lx in for MCP0XLT2", l_xlate2); - FAPI_TRY( mss::putScom(i_target.getParent<TARGET_TYPE_MCS>(), l_t0_address, l_xlate) ); - FAPI_TRY( mss::putScom(i_target.getParent<TARGET_TYPE_MCS>(), l_t1_address, l_xlate1) ); - FAPI_TRY( mss::putScom(i_target.getParent<TARGET_TYPE_MCS>(), l_t2_address, l_xlate2) ); + FAPI_TRY( mss::putScom(i_target, MCA_MBA_MCP0XLT0, l_xlate) ); + FAPI_TRY( mss::putScom(i_target, MCA_MBA_MCP0XLT1, l_xlate1) ); + FAPI_TRY( mss::putScom(i_target, MCA_MBA_MCP0XLT2, l_xlate2) ); fapi_try_exit: return fapi2::current_err; |
